HT82M99A HoltekSemiconductor

HT82M99E/HT82M99A
USB Mouse Encoder 8-Bit MCU

Technical Document
· Tools Information
· FAQs
· Application Note
Features
· Flexible total solution for applications that combine · 96 bytes RAM (20H~7FH)
PS/2 and low-speed USB interface, such as mice, · 6MHz/12MHz internal CPU clock
joysticks, and many others · 4-level stacks
· USB Specification Compliance
· Two 7-bit indirect addressing registers
- Conforms to USB specification V2.0
· One 16-bit programmable timer counter with
- Conforms to USB HID specification V2.0
overflow interrupt (shared with PA7, vector 0CH)
· Supports 1 Low-speed USB control endpoint and
· One USB interrupt input (vector 04H)
1 interrupt endpoint
· HALT function and wake-up feature reduce
· Each endpoint has 8 bytes FIFO
power consumption
· Integrated USB transceiver
· PA0~PA7, PB4 and PB7 support wake-up function
· 3.3V regulator output
· Internal Power-On reset (POR)
· External 6MHz or 12MHz ceramic resonator or
· Watchdog Timer (WDT)
crystal
· 12 I/O ports
· 8-bit RISC microcontroller, with 2K´14 EPROM
· 16-pin NSOP, 18-pin DIP/SOP and
(000H~7FFH)
20-pin DIP/SOP/SSOP (150mil) package
General Description
The USB MCU OTP body is suitable for USB mouse de- The mask version HT82M99A is fully pin and functionally
vices. It consists of a Holtek high performance 8-bit compatible with the OTP version HT82M99E device.
www.DataSheet.net/
MCU core for control unit, built-in USB SIE, 2K´14 ROM
and 96 bytes data RAM.
Rev. 2.60 1 April 1, 2011
Datasheet pdf - http://www.DataSheet4U.co.kr/

HT82M99E/HT82M99A
Block Diagram
U S B D + /C L K U S B D -/D A T A V 3 3 O
U S B 1 .1
P S 2
B P
In te rru p t
C ir c u it T M R L M fS Y S /4
T M R H U
X P A 7 /T M R
S T A C K
P ro g ra m P ro g ra m IN T C T M R C
R O M C o u n te r
E N /D IS
W D T S
M S Y S C L K /4
In s tr u c tio n W D T P r e s c a le r W D T U
R e g is te r M D A T A X W D T O S C
M P
U M e m o ry
X
P A C P O R T A
P A 0 ~ P A 6
P A P A 7 /T M R
In s tr u c tio n M U X
D e c o d e r
P B C P O R T B P B 2 ~ P B 4 ,
A L U S T A T U S P B 7
T im in g P B
G e n e ra to r S h ifte r
O S C 2 O S C 1
R E S
V D D A C C www.DataSheet.net/
V S S
Pin Assignment
V S S 1 2 0 O S C 1
V S S 1 1 8 O S C 1 V 3 3 O 2 1 9 O S C 2
V S S 1 1 6 O S C 1 V 3 3 O 2 1 7 O S C 2 U S B D + /C L K 3 1 8 V D D
V 3 3 O 2 1 5 O S C 2 U S B D + /C L K 3 1 6 V D D U S B D -/D A T A 4 1 7 P A 7 /T M R
U S B D + /C L K 3 1 4 V D D U S B D -/D A T A 4 1 5 P A 7 /T M R R E S 5 1 6 P A 6
U S B D -/D A T A 4 1 3 P A 7 /T M R R E S 5 1 4 P A 6 P A 0 6 1 5 P A 5
R E S 5 1 2 P A 6 P A 0 6 1 3 P A 5 P A 1 7 1 4 P A 4
P A 0 6 1 1 P A 5 P A 1 7 1 2 P A 4 P B 2 8 1 3 P A 3
P A 1 7 1 0 P A 4 P B 2 8 1 1 P A 3 P B 3 9 1 2 P A 2
P A 2 8 9 P A 3 P B 3 9 1 0 P A 2 P B 4 1 0 1 1 P B 7
H T 8 2 M 9 9 E /H T 8 2 M 9 9 A H T 8 2 M 9 9 E /H T 8 2 M 9 9 A H T 8 2 M 9 9 E /H T 8 2 M 9 9 A
1 6 N S O P -A 1 8 D IP -A /S O P -A 2 0 D IP -A /S O P -A /S S O P -A
Rev. 2.60 2 April 1, 2011

HT82M99E/HT82M99A
Pin Description
ROM Code
Pin Name I/O Description
Option
Bidirectional 8-bit input/output port. Each bit can be configured as a
wake-up input by ROM code option. The input or output mode is con-
trolled by PAC (PA control register).
Pull-low
Pull-high resistor options: PA0~PA7
PA0~PA6, Pull-high
I/O Pull-low resistor options: PA0~PA3
PA7/TMR Wake-up
CMOS/NMOS/PMOS options: PA0~PA7
CMOS/NMOS/PMOS
Falling edge wake-up options: PA0~PA1, PA4~PA7
Rising and falling edge wake-up options: PA2~PA3
PA7 is wire-bonded with TMR
Bidirectional 8-bit input/output port. Software instructions determine the
Pull-high CMOS output or Schmitt trigger input with pull-high resistor (determined
PB2, PB3 I/O
Pull-low by pull-high options).
Pull-low resistor for options: PB2, PB3
Bidirectional 8-bit input/output port. Software instructions determine the
Pull-high CMOS output or Schmitt trigger input with pull-high resistor (determined
PB4, PB7 I/O
Wake-up by pull-high options).
Falling edge wake-up options: PB4, PB7
VSS ¾ ¾ Negative power supply, ground
RES I ¾ Schmitt trigger reset input. Active low.
VDD ¾ ¾ Positive power supply
V33O O ¾ 3.3V regulator output

USBD+ or PS2 CLK I/O line
USBD+/CLK I/O ¾
USB or PS2 function is controlled by software control register
USBD- or PS2 DATA I/O line
USBD-/DATA I/O ¾
USB or PS2 function is controlled by software control register
OSC1 I OSC1, OSC2 are connected to a 6MHz or 12MHz crystal/resonator
¾
www.DataSheet.net/
OSC2 O (determined by software instructions) for the internal system clock.
Absolute Maximum Ratings

Supply Voltage ...........................VSS-0.3V to VSS+6.0V Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V Operating Temperature...............................0°C to 70°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 2.60 3 April 1, 2011

HT82M99E/HT82M99A
D.C. Characteristics Ta=25°C
Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions
VDD Operating Voltage ¾ ¾ 3.3 ¾ 5.5 V
IDD Operating Current (6MHz Crystal) 5V No load, fSYS=6MHz ¾ 7 9 mA
No load, system HALT,
ISTB1 Standby Current 5V ¾ ¾ 500 mA
USB suspend**
ISTB2 Standby Current (WDT Enabled) 5V No load, system HALT, ¾ ¾ 30 mA
input/output mode,
ISTB3 Standby Current (WDT Disabled) 5V set SUSPEND2 [1CH].4 ¾ ¾ 20 mA
VIL1 Input Low Voltage for I/O Ports 5V ¾ 0 ¾ 0.8 V

VIH1 Input High Voltage for I/O Ports 5V ¾ 2 ¾ VDD V
VIL2 Input Low Voltage (RES) 5V ¾ 0 ¾ 0.4VDD V
VIH2 Input High Voltage (RES) 5V ¾ 0.9VDD ¾ VDD V
Output Sink Current for PA4~PA7,
IOL 5V VOL=0.4V 2 4 ¾ mA
PB4, PB7
Output Source Current for PA4~PA7,
IOH 5V VOH=3.4V -2.5 -4 ¾ mA
PB4, PB7
Output Sink Current for PA0~PA3,
IOL2 5V VOL=0.4V 10 15 ¾ mA
PB2~PB3
Output Source Current for PA0~PA3,
IOH2 5V VOH=3.4V 8 12 ¾ mA
PB2~PB3
Pull-down Resistance for PA0~PA3,
RPD 5V ¾ 10 30 50 kW
PB2~PB3
RPH1 Pull-high Resistance for DATA* ¾ ¾ 1.3 1.5 2.0 kW
RPH2 Pull-high Resistance for CLK ¾ www.DataSheet.net/
¾ 2.0 4.7 6.0 kW
Pull-high Resistance for PA0~PA7,
RPH3 ¾ ¾ 30 50 70 kW
PB2~PB4, PB7
VLVR Low Voltage Reset 5V ¾ 2.4 2.7 3 V
Note: ²*² The DATA pull-high must be implemented by the external 1.5kW.
²**² include 15kW loading of USBD+, USBD- line in host terminal.
A.C. Characteristics Ta=25°C
Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions
fSYS System Clock (Crystal OSC) 5V ¾ 6 ¾ 12 MHz
fRCSYS RC Clock with 8-bit Prescaler Register 5V ¾ 0 32 ¾ kHz
tWDT Watchdog Time-out Period (System Clock) ¾ Without WDT prescaler 1024 ¾ ¾ tRCSYS
tRF USBD+, USBD- Rising & falling Time ¾ ¾ 75 ¾ 300 ns
tRES External Reset Low Pulse Width ¾ ¾ 1 ¾ ¾ ms
tSST System Start-up Timer Period ¾ Wake-up from HALT ¾ 1024 ¾ tSYS
tOSC Crystal Setup ¾ ¾ ¾ 5 10 ms
Note: Power-on period=tWDT+tSST+tOSC

WDT Time-out in normal mode=1/fRCSYS´256´WDTS+tWDT
WDT Time-out in HALT mode=1/fRCSYS´256´WDTS+tSST+tOSC
Rev. 2.60 4 April 1, 2011

HT82M99E/HT82M99A
Functional Description
Execution Flow After accessing a program memory word to fetch an in-
The system clock for the microcontroller is derived from struction code, the contents of the program counter are
either 6MHz or 12MHz crystal oscillator, which used a incremented by one. The program counter then points to
frequency that is determined by the SCLKSEL bit of the the memory word containing the next instruction code.
SCC Register. The default system frequency is 12MHz. When executing a jump instruction, conditional skip ex-
The system clock is internally divided into four non- ecution, loading to the PCL register, performing a sub-
overlapping clocks. One instruction cycle consists of routine call or return from subroutine, initial reset,
four system clock cycles. internal interrupt, external interrupt or return from inter-
Instruction fetching and execution are pipelined in such rupts, the PC manipulates the program transfer by load-
a way that a fetch takes an instruction cycle while de- ing the address corresponding to each instruction.
coding and execution takes the next instruction cycle. The conditional skip is activated by instructions. Once
However, the pipelining scheme causes each instruc- the condition is met, the next instruction, fetched during
tion to be effectively executed in a cycle. If an instruction the current instruction execution, is discarded and a
changes the program counter, two cycles are required to dummy cycle replaces it to get the proper instruction.
complete the instruction. Otherwise proceed with the next instruction.
The lower byte of the program counter (PCL) is a read-
Program Counter - PC
able and writeable register (06H). Moving data into the
The program counter (PC) controls the sequence in PCL performs a short jump. The destination will be
which the instructions stored in the program ROM are within the current program ROM page.
executed and its contents specify a full range of pro-
gram memory. When a control transfer takes place, an additional
dummy cycle is required.
T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4
S y s te m C lo c k
O S C 2 ( R C o n ly )
P C P C P C + 1 P C + 2
F e tc h IN S T (P C ) www.DataSheet.net/
E x e c u te IN S T (P C -1 ) F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C ) F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Program Counter
Mode
*10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0
Initial Reset 0 0 0 0 0 0 0 0 0 0 0
USB Interrupt 0 0 0 0 0 0 0 0 1 0 0
Timer/Event Counter Overflow 0 0 0 0 0 0 0 1 1 0 0
Skip Program Counter+2
Loading PCL *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0
Jump, Call Branch #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0
Return from Subroutine S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
Program Counter
Note: *10~*0: Program counter bits S10~S0: Stack register bits

#10~#0: Instruction code bits @7~@0: PCL bits
Rev. 2.60 5 April 1, 2011

HT82M99E/HT82M99A
Program Memory - ROM ROM data by two table read instructions: ²TABRDC²
The program memory is used to store the program in- and ²TABRDL², transfer the contents of the
structions which are to be executed. It also contains lower-order byte to the specified data memory, and
data, table, and interrupt entries, and is organized into the higher-order byte to TBLH (08H).
2048´14 bits, addressed by the program counter and ta- The three methods are shown as follows:
ble pointer. ¨ The instructions ²TABRDC [m]² (the current page,
one page=256words), where the table locations is
Certain locations in the program memory are reserved defined by TBLP (07H) in the current page. And the
for special usage: ROM code option TBHP is disabled (default).
· Location 000H ¨ The instructions ²TABRDC [m]², where the table lo-
This area is reserved for program initialization. After a cations is defined by registers TBLP (07H) and
chip reset, the program always begins execution at lo- TBHP (01FH). And the ROM code option TBHP is
cation 000H. enabled.
¨ The instructions ²TABRDL [m]², where the table lo-
· Location 004H
cations is defined by Registers TBLP (07H) in the
This area is reserved for the USB interrupt service last page (0700H~07FFH).
program. If the USB interrupt is activated, the interrupt
Only the destination of the lower-order byte in the ta-
is enabled and the stack is not full, the program begins
ble is well-defined, the other bits of the table word are
execution at location 004H.
transferred to the lower portion of TBLH, and the re-
· Location 00CH maining 1-bit words are read as ²0². The Table
This location is reserved for the Timer/Event Counter Higher-order byte register (TBLH) is read only. The ta-
interrupt service program. If a timer interrupt results ble pointer (TBLP, TBHP) is a read/write register (07H,
from a Timer/Event Counter overflow, and the inter- 1FH), which indicates the table location. Before ac-
rupt is enabled and the stack is not full, the program cessing the table, the location must be placed in the
begins execution at location 00CH. TBLP and TBHP (If the OTP option TBHP is disabled,
the value in TBHP has no effect). The TBLH is read
· Table location only and cannot be restored. If the main routine and
Any location in the program memory can be used as the ISR (Interrupt Service Routine) both employ the
look-up tables. There are three method to read the table read instruction, the contents of the TBLH in the
0 0 0 H main routine are likely to be changed by the table read
D e v ic e In itia liz a tio n P r o g r a m instruction used in the ISR. Errors can occur. In other
0 0 4 H words, using the table read instruction in the main rou-
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U S B In te r r u p t S u b r o u tin e tine and the ISR simultaneously should be avoided.

0 0 C H T im e r /E v e n t C o u n te r However, if the table read instruction has to be applied
In te r r u p t S u b r o u tin e in both the main routine and the ISR, the interrupt
P ro g ra m should be disabled prior to the table read instruction. It
n 0 0 H M e m o ry will not be enabled until the TBLH has been backed
L o o k - u p T a b le ( 2 5 6 W o r d s ) up. All table related instructions require two cycles to
n F F H
complete the operation. These areas may function as
normal program memory depending on the require-
ments.
Once TBHP is enabled, the instruction ²TABRDC [m]²
L o o k - u p T a b le ( 2 5 6 W o r d s )
7 F F H reads the ROM data as defined by TBLP and TBHP
1 4 B its value. Otherwise, the ROM code option TBHP is dis-
N o te : n ra n g e s fro m 0 to 7 abled, the instruction ²TABRDC [m]² reads the ROM
Program Memory data as defined by TBLP and the current program
counter bits.
Table Location
Instruction
*10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0
TABRDC [m] P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0
TABRDL [m] 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0
Table Location
Note: *10~*0: Table location bits P10~P8: Current program counter bits when TBHP is disabled
@7~@0: TBLP bits TBHP register bit2~bit0 when TBHP is enabled
Rev. 2.60 6 April 1, 2011

HT82M99E/HT82M99A
Stack Register - STACK B a n k 0

0 0 H In d ir e c t A d d r e s s in g R e g is te r 0
This is a special part of the memory which is used to
0 1 H M P 0
save the contents of the program counter only. The
stack is organized into 4 levels and is neither part of the
0 3 H M P 1
data nor part of the program space, and is neither read-
0 4 H B P
able nor writeable. The activated level is indexed by the
0 5 H A C C
stack pointer (SP) and is neither readable nor writeable.
0 6 H P C L
At a subroutine call or interrupt acknowledge signal, the
0 7 H T B L P
contents of the program counter are pushed onto the
0 8 H T B L H
stack. At the end of a subroutine or an interrupt routine,
0 9 H W D T S
signaled by a return instruction (RET or RETI), the pro-
0 A H S T A T U S
gram counter is restored to its previous value from the IN T C
0 B H
stack. After a chip reset, the SP will point to the top of the
0 C H
stack.
0 D H
If the stack is full and a non-masked interrupt takes 0 E H
place, the interrupt request flag will be recorded but the 0 F H T M R H
acknowledge signal will be inhibited. When the stack 1 0 H T M R L
pointer is decremented (by RET or RETI), the interrupt 1 1 H T M R C
will be serviced. This feature prevents stack overflow al- 1 2 H P A
lowing the programmer to use the structure more easily. 1 3 H P A C
In a similar case, if the stack is full and a ²CALL² is sub- 1 4 H P B
sequently executed, stack overflow occurs and the first 1 5 H P B C
entry will be lost (only the most recent 4 return ad- 1 6 H
dresses are stored). 1 7 H
1 8 H
Data Memory - RAM for Bank 0 1 9 H
1 A H U S C
The data memory is designed with 96´8 bits. The data
1 B H U S R
memory is divided into two functional groups: special
1 C H S C C
function registers and general purpose data memory
1 D H
(96´8). Most are read/write, but some are read only.
1 E H
The unused space before 20H is reserved for future ex- www.DataSheet.net/
1 F H T B H P
panded usage and reading these locations will get 2 0 H
²00H². The general purpose data memory, addressed
from 20H to 7FH, is used for data and control informa- G e n e ra l P u rp o s e
tion under instruction commands. D A T A M E M O R Y
(9 6 B y te s )
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations di- 7 F H
rectly. Except for some dedicated bits, each bit in the
data memory can be set and reset by ²SET [m].i² and Bank 0 RAM Mapping
²CLR [m].i². They are also indirectly accessible through
memory pointer registers (MP0 or MP1).
Rev. 2.60 7 April 1, 2011

HT82M99E/HT82M99A
Data Memory - RAM for Bank 1 Indirect Addressing Register

The special function registers used in the USB interface Locations 00H and 02H are indirect addressing regis-
are located in RAM Bank1. In order to access Bank1 ters that are not physically implemented. Any read/write
register, only the Indirect addressing pointer MP1 can operation on [00H] ([02H]) will access the data memory
be used and the Bank register BP should be set to 1. pointed to by MP0 (MP1). Reading location 00H (02H)
The RAM bank 1 mapping is as shown. indirectly will return the result 00H. Writing indirectly re-
B a n k 1 sults in no operation.
The indirect addressing pointer (MP0) always points to
0 1 H M P 0
Bank0 RAM addresses no matter the value of Bank
Register (BP).
0 3 H M P 1
0 4 H B P The indirect addressing pointer (MP1) can access
0 5 H A C C Bank0 or Bank1 RAM data according to the value of BP
0 6 H P C L which is set to 0 or 1 respectively.
0 7 H T B L P The memory pointer registers (MP0 and MP1) are 7-bit
0 8 H T B L H registers.
0 9 H W D T S
0 A H S T A T U S Accumulator
0 B H IN T C
The accumulator is closely related to ALU operations. It
0 C H
is also mapped to location 05H of the data memory and
0 D H
can carry out immediate data operations. The data
0 E H
movement between two data memory locations must
0 F H T M R H
pass through the accumulator.
1 0 H T M R L
1 1 H T M R C
Arithmetic and Logic Unit - ALU
1 2 H P A
1 3 H P A C This circuit performs 8-bit arithmetic and logic opera-
1 4 H P B tions. The ALU provides the following functions:
1 5 H P B C · Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
1 6 H · Logic operations (AND, OR, XOR, CPL)
1 7 H
· Rotation (RL, RR, RLC, RRC)
1 8 H
· Increment and Decrement (INC, DEC)
1 9 H www.DataSheet.net/
· Branch decision (SZ, SNZ, SIZ, SDZ ....)

1 A H U S C
1 B H U S R The ALU not only saves the results of a data operation
1 C H S C C but also changes the status register.
1 D H
1 E H Status Register - STATUS
1 F H T B H P This 8-bit register (0AH) contains the zero flag (Z), carry
2 0 H flag (C), auxiliary carry flag (AC), overflow flag (OV),
4 1 H P ip e _ c tr l power down flag (PDF), and watchdog time-out flag
4 2 H A W R (TO). It also records the status information and controls
4 3 H S T A L L the operation sequence.
4 4 H P IP E
4 5 H S IE S
With the exception of the TO and PDF flags, bits in the
4 6 H M IS C
status register can be altered by instructions like most
4 7 H other registers. Any data written into the status register
4 8 H F IF O 0 will not change the TO or PDF flag. In addition, opera-
4 9 H F IF O 1 tions related to the status register may give different re-
sults from those intended.
Bank 1 RAM Mapping
Address 00~1FH in RAM Bank0 and Bank1 are located

in the same Registers
Rev. 2.60 8 April 1, 2011

HT82M99E/HT82M99A
Bit No. Label Function

C is set if an operation results in a carry during an addition operation or if a borrow does not
0 C take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
1 AC
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2 Z Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
3 OV
highest-order bit, or vice versa; otherwise OV is cleared.
PDF is cleared by a system power-up or executing the ²CLR WDT² instruction. PDF is set by
4 PDF
executing the ²HALT² instruction.
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is

5 TO
set by a WDT time-out.
6 ¾ Unused bit, read as ²0²
Status (0AH) Register
The TO flag can be affected only by a system power-up, Once an interrupt subroutine is serviced, all the other in-
a WDT time-out or executing the ²CLR WDT² or ²HALT² terrupts will be blocked (by clearing the EMI bit). This
instruction. The PDF flag can be affected only by exe- scheme may prevent any further interrupt nesting. Other
cuting the ²HALT² or ²CLR WDT² instruction or during a interrupt requests may occur during this interval but only
system power-up. the interrupt request flag is recorded. If a certain inter-
rupt requires servicing within the service routine, the
The Z, OV, AC and C flags generally reflect the status of
EMI bit and the corresponding bit of the INTC may be
the latest operations.
set to allow interrupt nesting. If the stack is full, the inter-
In addition, upon entering the interrupt sequence or exe- rupt request will not be acknowledged, even if the re-
cuting a subroutine call, the status register will not be lated interrupt is enabled, until the SP is decremented. If
automatically pushed onto the stack. If the contents of immediate service is desired, the stack must be pre-
the status are important and if the subroutine can cor- vented from becoming full.
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rupt the status register, precautions must be taken to

All these kinds of interrupts have a wake-up capability.
save it properly.
As an interrupt is serviced, a control transfer occurs by
Interrupt pushing the program counter onto the stack, followed by
a branch to a subroutine at a specified location in the
The device provides an external interrupt and internal
program memory. Only the program counter is pushed
timer/event counter interrupts. The Interrupt Control
onto the stack. If the contents of the register or status
Register (INTC;0BH) contains the interrupt control bits
register (STATUS) are altered by the interrupt service
to set the enable/disable and the interrupt request flags.
program which corrupts the desired control sequence,
the contents should be saved in advance.

0 EMI Controls the master (global) interrupt (1=enable; 0=disable)
1 EUI Controls the USB interrupt (1=enable; 0= disable)
3 ETI Controls the Timer/Event Counter interrupt (1=enable; 0=disable)
4 USBF USB interrupt request flag (1=active; 0=inactive)
6 TF Internal timer/event counter request flag (1:active; 0:inactive)
INTC (0BH) Register
Rev. 2.60 9 April 1, 2011

HT82M99E/HT82M99A
The USB interrupts are triggered by the following USB Once the interrupt request flags (TF, USBF) are set, they
events and the related interrupt request flag (USBF; bit will remain in the INTC register until the interrupts are ser-
4 of the INTC) will be set. viced or cleared by a software instruction. It is recom-
· Access of the corresponding USB FIFO from PC mended that a program does not use the ²CALL
· The USB suspend signal from PC subroutine² within the interrupt subroutine. Interrupts of-
· The USB resume signal from PC ten occur in an unpredictable manner or need to be ser-
· USB Reset signal
viced immediately in some applications. If only one stack
is left and enabling the interrupt is not well controlled, the
When the interrupt is enabled, the stack is not full and
original control sequence will be damaged once the
the external interrupt is active, a subroutine call to loca-
²CALL² operates in the interrupt subroutine.
tion 04H will occur. The interrupt request flag (USBF)
and EMI bits will be cleared to disable other interrupts. Oscillator Configuration
When the PC Host access the FIFO of the HT82M99E/ There is an oscillator circuit in the microcontroller.
HT82M99A, the corresponding request bit of the USR is
set, and a USB interrupt is triggered. So user can easily O S C 1
decide which FIFO is accessed. When the interrupt has
been served, the corresponding bit should be cleared by
firmware. When the HT82M99E receives a USB Sus- O S C 2
pend signal from the Host PC, the suspend line (bit0 of C r y s ta l O s c illa to r
the USC) of the HT82M99E is set and a USB interrupt is
System Oscillator
also triggered.
When the HT82M99E/HT82M99A receives a Resume This oscillator is designed for system clocks. The HALT
signal from the Host PC, the resume line (bit3 of the mode stops the system oscillator and ignores an exter-
USC) of the HT82M99E/HT82M99A are set and a USB nal signal to conserve power.
interrupt is triggered. A crystal across OSC1 and OSC2 is needed to provide
Whenever a USB reset signal is detected, the USB in- the feedback and phase shift required for the oscillator.
terrupt is triggered and URST_Flag bit of the USC regis- No other external components are required. In stead of
ter is set. When the interrupt has been served, the bit a crystal, a resonator can also be connected between
should be cleared by firmware. OSC1 and OSC2 to get a frequency reference, but two
external capacitors in OSC1 and OSC2 are required.
The internal timer/even counter interrupt is initialized by
setting the timer/event counter interrupt request flag (;bit The HT82M99E/HT82M99A can operate in 6MHz or
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6 of the INTC), caused by a timer overflow. When the in- 12MHz system clocks. In order to make sure that the
terrupt is enabled, the stack is not full and the TF is set, a USB SIE functions properly, user should correctly con-
subroutine call to location 0CH will occur. The related in- figure the SCLKSEL bit of the SCC Register. The default
terrupt request flag (TF) will be reset and the EMI bit system clock is 12MHz.
cleared to disable further interrupts. The WDT oscillator is a free running on-chip RC oscilla-
During the execution of an interrupt subroutine, other in- tor, and no external components are required. Even if
terrupt acknowledge signals are held until the ²RETI² in- the system enters the power down mode, the system
struction is executed or the EMI bit and the related clock is stopped, but the WDT oscillator still works within
interrupt control bit are set to 1 (if the stack is not full). To a period of approximately 31ms. The WDT oscillator can
return from the interrupt subroutine, ²RET² or ²RETI² be disabled by ROM code option to conserve power.
may be invoked. RETI will set the EMI bit to enable an
Watchdog Timer - WDT
interrupt service, but RET will not.
The WDT clock source is implemented by a dedicated
Interrupts, occurring in the interval between the rising
RC oscillator (WDT oscillator), or instruction clock (sys-
edges of two consecutive T2 pulses, will be serviced on
tem clock divided by 4), determine by ROM code option.
the latter of the two T2 pulses, if the corresponding inter-
This timer is designed to prevent a software malfunction
rupts are enabled. In the case of simultaneous requests
or sequence from jumping to an unknown location with
the following table shows the priority that is applied.
unpredictable results. The Watchdog Timer can be dis-
These can be masked by resetting the EMI bit.
abled by ROM code option. If the Watchdog Timer is dis-
Interrupt Source Priority Vector abled, all the executions related to the WDT result in no
USB interrupt 1 04H operation.
Timer/Event Counter overflow 2 0CH Once the internal WDT oscillator (RC oscillator with a
period of 31ms/5V normally) is selected, it is first divided
Rev. 2.60 10 April 1, 2011

HT82M99E/HT82M99A
S y s te m C lo c k /4 W D T P r e s c a le r
R O M
C o d e 8 - b it C o u n te r 7 - b it C o u n te r
O p tio n
W D T
S e le c t
O S C
8 -to -1 M U X W S 0 ~ W S 2
W D T T im e - o u t
Watchdog Timer
by 256 (8-stage) to get the nominal time-out period of CLRWDT times is equal to two), these two instructions
8ms/5V. This time-out period may vary with tempera- must be executed to clear the WDT; otherwise, the WDT
tures, VDD and process variations. By invoking the may reset the chip as a result of time-out.
WDT prescaler, longer time-out periods can be realized.
Writing data to WS2, WS1, WS0 (bits 2, 1, 0 of the Power Down Operation - HALT
WDTS) can give different time-out periods. If WS2, The HALT mode is initialized by the ²HALT² instruction
WS1, and WS0 are all equal to 1, the division ratio is up and results in the following:
to 1:128, and the maximum time-out period is 1s/5V. If
· The system oscillator will be turned off but the WDT
the WDT oscillator is disabled, the WDT clock may still
oscillator remains running (if the WDT oscillator is se-
come from the instruction clock and operates in the
lected).
same manner except that in the HALT state the WDT
· The contents of the on-chip RAM and registers remain
may stop counting and lose its protecting purpose. In
unchanged.
this situation the logic can only be restarted by external
· The WDT and WDT prescaler will be cleared and re-
logic. The high nibble and bit 3 of the WDTS are re-
counted again (if the WDT clock is from the WDT os-
served for user defined flags, which can only be set to
cillator).
²10000² (WDTS.7~WDTS.3). · All of the I/O ports remain in their original status.
If the device operates in a noisy environment, using the · The PDF flag is set and the TO flag is cleared.
on-chip 32kHz RC oscillator (WDT OSC) is strongly rec- The system can leave the HALT mode by means of an
ommended, since the HALT will stop the system clock. external reset, an interrupt, an external falling edge sig-
WS2 WS1 WS0 Division Ratio nal on port A or a WDT overflow. An external reset
0 0 0 1:1 causes a device initialization and the WDT overflow per-
0 0 1 1:2 forms a ²warm reset². After the TO and PDF flags are
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examined, the cause for chip reset can be determined.

0 1 0 1:4
The PDF flag is cleared by a system power-up or exe-
0 1 1 1:8 cuting the ²CLR WDT² instruction and is set when exe-
1 0 0 1:16 cuting the ²HALT² instruction. The TO flag is set if the
1 0 1 1:32 WDT time-out occurs, and causes a wake-up that only
1 1 0 1:64 resets the program counter and SP; the others remain in
their original status.
1 1 1 1:128
The port A wake-up and interrupt methods can be con-
WDTS (09H) Register
sidered as a continuation of normal execution. Each bit
The WDT overflow under normal operation will initialize in port A can be independently selected to wake-up the
a ²chip reset² and set the status bit ²TO². But in the device by mask option. Awakening from an I/O port stim-
HALT mode, the overflow will initialize a ²warm reset² ulus, the program will resume execution of the next in-
and only the program counter and SP are reset to zero. struction. If it awakens from an interrupt, two sequence
To clear the contents of the WDT (including the WDT may occur. If the related interrupt is disabled or the inter-
prescaler), three methods are adopted; external reset (a rupt is enabled but the stack is full, the program will re-
low level to RES), software instruction and a ²HALT² in- sume execution at the next instruction. If the interrupt is
struction. The software instruction include ²CLR WDT² enabled and the stack is not full, the regular interrupt re-
and the other set - ²CLR WDT1² and ²CLR WDT2². Of sponse takes place. If an interrupt request flag is set to
these two types of instruction, only one can be active de- ²1² before entering the HALT mode, the wake-up func-
pending on the ROM code option - ²CLR WDT times se- tion of the related interrupt will be disabled. Once a
wake-up event occurs, it takes 1024 tSYS (system clock
lection option². If the ²CLR WDT² is selected (i.e.
period) to resume normal operation. In other words, a
CLRWDT times is equal to one), any execution of the
dummy period will be inserted after a wake-up. If the
²CLR WDT² instruction will clear the WDT. In the case
wake-up results from an interrupt acknowledge signal,
that ²CLR WDT² and ²CLR WDT² are chosen (i.e.
Rev. 2.60 11 April 1, 2011

HT82M99E/HT82M99A
the actual interrupt subroutine execution will be delayed The functional unit chip reset status are shown below.
by one or more cycles. If the wake-up results in the next
Program Counter 000H
instruction execution, this will be executed immediately
after the dummy period is finished. Interrupt Disable
To minimize power consumption, all the I/O pins should Prescaler Clear
be carefully managed before entering the HALT status. Clear. After master reset, WDT
WDT
begins counting
Reset
Timer/event Counter Off
There are four ways in which a reset can occur:
Input/output Ports Input mode
· RES reset during normal operation
· RES reset during HALT Stack Pointer Points to the top of the stack
· WDT time-out reset during normal operation
· USB reset
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re -
set² that resets only the Program Counter and Stack V D D
Pointer, leaving the other circuits in their original state. R E S
tS S T
Some registers remain unchanged during other reset
S S T T im e - o u t
conditions. Most registers are reset to the ²initial condi-
tion² when the reset conditions are met. By examining C h ip R e s e t
the PDF and TO flags, the program can distinguish be-
tween different ²chip resets². Reset Timing Chart
TO PDF RESET Conditions

0 0 RES reset during power-up
0 0 RES reset during normal operation H A L T
W a rm R e s e t
0 0 RES wake-up HALT
W D T
1 u WDT time-out during normal operation
1 1 WDT wake-up HALT R E S
C o ld
Note: ²u² stands for ²unchanged²
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R e s e t
S S T
To guarantee that the system oscillator is started and O S C 1 1 0 - b it R ip p le
C o u n te r
stabilized, the SST (System Start-up Timer) provides an
extra delay of 1024 system clock pulses when the sys-
S y s te m R e s e t
tem resets (power-up, WDT time-out or RES reset) or
the system awakes from the HALT state.
Reset Configuration
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will en-
able the SST delay.
V D D
R E S
Reset Circuit
Rev. 2.60 12 April 1, 2011

HT82M99E/HT82M99A
The registers status are summarized in the following table.

WDT
RES Reset WDT
Reset Time-out RES Reset USB-Reset USB-Reset
Register (Normal Time-Out
(Power On) (Normal (HALT) (Normal) (HALT)
Operation) (HALT)*
Operation)
TMRH xxxx xxxx 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu
TMRL xxxx xxxx 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu
TMRC 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u--- 00-0 1--- 00-0 1---
Program
000H 000H 000H 000H 000H 000H 000H
Counter
MP0 1xxx xxxx 1uuu uuuu 1uuu uuuu 1uuu uuuu 1uuu uuuu 1uuu uuuu 1uuu uuuu
MP1 1xxx xxxx 1uuu uuuu 1uuu uuuu 1uuu uuuu 1uuu uuuu 1uuu uuuu 1uuu uuuu
ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
TBLH -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu
STATUS --00 xxxx --1u uuuu --00 uuuu --00 uuuu --11 uuuu --uu uuuu --01 uuuu
INTC -000 0000 -000 0000 --00 uuuu -000 0000 -uuu uuuu -000 0000 -000 0000
WDTS 1000 0111 1000 0111 1000 0111 1000 0111 uuuu uuuu 1000 0111 1000 0111
PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111
PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111
PB 1xx1 11xx 1xx1 11xx 1xx1 11xx 1xx1 11xx uuuu uuuu 1xx1 11xx 1xx1 11xx
PBC 1xx1 11xx 1xx1 11xx 1xx1 11xx 1xx1 11xx uuuu uuuu 1xx1 11xx 1xx1 11xx
USC 11xx 0000 uuxx uuuu 11xx 0000 11xx 0000 uuxx uuuu 1100 0u00 1100 0u00
USR 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu u0uu 0000 u0uu 0000
SCC 0000 0000 uuuu uuuu 0000 0000 0000 0000
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uuuu uuuu uu00 u000 uu00 u000
TBHP ---- -xxx ---- -uuu ---- -uuu ---- -uuu ---- -uuu ---- -uuu ---- -uuu
PIPE_CTL 0000 0010 0000 uuuu 0000 0010 0000 0010 0000 uuuu 0000 0010 0000 0010
AWR 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000
STALL 0000 0010 0000 uuuu 0000 0010 0000 0010 0000 uuuu 0000 0010 0000 0010
PIPE 0000 0000 xxxx xxxx 0000 0000 0000 0000 xxxx xxxx 0000 0000 0000 0000
SIES 0100 0000 uxux xuuu 0100 0000 0x00 0000 uxux xuuu 0000 0000 0000 0000
MISC 0x00 0000 uxuu uuuu 0x00 0000 0x00 0000 uxuu uuuu 0x00 0000 0x00 0000
FIFO0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000
FIFO1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000
Note: ²*² stands for ²warm reset²

²u² stands for ²unchanged²
²x² stands for ²unknown²
Rev. 2.60 13 April 1, 2011

HT82M99E/HT82M99A
Timer/Event Counter which means that the clock source comes from an exter-
A timer/event counter (TMR) is implemented in the nal (TMR) pin. The timer mode functions as a normal
microcontroller. timer with the clock source coming from the fSYS/4
(Timer). The pulse width measurement mode can be
The timer/event counter contains a 16-bit programma- used to count the high or low level duration of the exter-
ble count-up counter and the clock may come from an nal signal (TMR). The counting is based on the fSYS/4.
external source or from the system clock divided by 4.
In the event count or timer mode, once the timer/event
Using the internal clock source, there is only 1 reference counter starts counting, it will count from the current
time-base for the timer/event counter. The internal clock contents in the timer/event counter to FFFFH. Once
source is coming from fSYS/4. The external clock input overflow occurs, the counter is reloaded from the
allows the user to count external events, measure time timer/event counter preload register and generates the
intervals or pulse widths. interrupt request flag (TF; bit 6 of the INTC) at the same
There are 3 registers related to the timer/event counter; time.
TMRH (0FH), TMRL (10H), TMRC (11H). Writing TMRL In the pulse width measurement mode with the TON and
will only put the written data to an internal lower-order TE bits equal to one, once the TMR has received a tran-
byte buffer (8 bits) and writing TMRH will transfer the
sient from low to high (or high to low if the TE bit is ²0²) it
specified data and the contents of the lower-order byte
will start counting until the TMR returns to the original
buffer to TMRH and TMRL preload registers, respec-
level and resets the TON. The measured result will re-
tively. The timer/event counter preload register is
main in the timer/event counter even if the activated
changed by each writing TMRH operations. Reading
transient occurs again. In other words, only one cycle
TMRH will latch the contents of TMRH and TMRL coun-
measurement can be done. Until setting the TON, the
ters to the destination and the lower-order byte buffer,
cycle measurement will function again as long as it re-
respectively. Reading the TMRL will read the contents of
ceives further transient pulse. Note that, in this operat-
the lower-order byte buffer. The TMRC is the
ing mode, the timer/event counter starts counting not
timer/event counter control register, which defines the
according to the logic level but according to the transient
operating mode, counting enable or disable and active
edges. In the case of counter overflows, the counter is
edge.
reloaded from the timer/event counter preload register
The TM0, TM1 bits define the operating mode. The and issues the interrupt request just like the other two
event count mode is used to count external events, modes. To enable the counting operation, the timer ON

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0~2 ¾ Unused bit, read as ²0²

Defines the TMR active edge of the timer/event counter
3 TE
(0=active on low to high; 1=active on high to low)
4 TON Enable/disable the timer counting (0=disable; 1=enable)
Defines the operating mode
01=Event count mode (external clock)
6 TM0
10=Timer mode (internal clock)
7 TM1
11=Pulse width measurement mode
00=Unused
TMRC (11H) Register
D a ta B u s
fS Y S /4
T M 1
T M 0 1 6 B its
T im e r /E v e n t C o u n te r L o w B y te
T M R P r e lo a d R e g is te r B u ffe r
T E R e lo a d
P u ls e W id th 1 6 B its
T M 1 M e a s u re m e n t T im e r /E v e n t C o u n te r O v e r flo w
T M 0 M o d e C o n tro l (T M R H /T M R L )
to In te rru p t
T O N
Timer/Event Counter
Rev. 2.60 14 April 1, 2011

HT82M99E/HT82M99A
bit (TON; bit 4 of TMRC) should be set to 1. In the pulse tures can be reconfigured dynamically under software
width measurement mode, the TON will be cleared au- control. To function as an input, the corresponding latch
tomatically after the measurement cycle is completed. of the control register must write a ²1². The input source
But in the other two modes the TON can only be reset by also depends on the control register. If the control regis-
instructions. The overflow of the timer/event counter is ter bit is ²1², the input will read the pad state. If the con-
one of the wake-up sources. No matter what the opera- trol register bit is ²0², the contents of the latches will
tion mode is, writing a 0 to ET can disable the corre- move to the internal bus. The latter is possible in the
sponding interrupt services. ²read-modify-write² instruction. For output function,
In the case of timer/event counter OFF condition, writing CMOS/NMOS/PMOS configurations can be selected
data to the timer/event counter preload register will also (NMOS and PMOS are available for PA only). These
reload that data to the timer/event counter. But if the control registers are mapped to locations 13H and 15H.
timer/event counter is turned on, data written to it will After a chip reset, these input/output lines remain at high
only be kept in the timer/event counter preload register. levels or in a floating state (depending on the
The timer/event counter will still operate until overflow pull-high/low options). Each bit of these input/output
occurs (a timer/event counter reloading will occur at the
latches can be set or cleared by ²SET [m].i² and ²CLR
same time). When the timer/event counter (reading
[m].i² (m=12H or 14H) instructions.
TMR) is read, the clock will be blocked to avoid errors.
As clock blocking may result in a counting error, this Some instructions first input data and then follow the
must be taken into consideration by the programmer. output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
Input/Output Ports into the CPU, execute the defined operations
There are 12 bidirectional input/output lines in the (bit-operation), and then write the results back to the
microcontroller, labeled from PA to PB, which are latches or the accumulator.
mapped to the data memory of [12H] and [14H] respec- Each line of port A has the capability of waking-up the
tively. All of these I/O ports can be used for input and device.
output operations. For input operation, these ports are
There are pull-high/low (PA only) options available for
non-latching, that is, the inputs must be ready at the T2
I/O lines. Once the pull-high/low option of an I/O line is
rising edge of instruction ²MOV A,[m]² (m=12H or 14H).
selected, the I/O line have pull-high/low resistor. Other-
For output operation, all the data is latched and remains
wise, the pull-high/low resistor is absent. It should be
unchanged until the output latch is rewritten.
noted that a non-pull-high/low I/O line operating in input
Each I/O line has its own control register (PAC and PBC) mode will cause a floating state.
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to control the input/output configuration. With this con-

It is recommended that unused or not bonded out I/O
trol register, CMOS/NMOS/PMOS output or Schmitt
lines should be set as output pins by software instruction
trigger input with or without pull-high/low resistor struc-
to avoid consuming power under input floating state.
V D D
C o n tr o l B it P H
D a ta B u s D Q
W r ite C o n tr o l R e g is te r C K Q
C h ip R e s e t S
P B 2 ~ P B 4 ,
P B 7
R e a d C o n tr o l R e g is te r
D a ta B it
D Q
W r ite D a ta R e g is te r C K Q
S
P o rt O u tp u t
P L
C o n fig u r a tio n
M
U
R e a d D a ta R e g is te r X
P A W a k e -u p
P A W a k e - u p O p tio n
P A 7 /T M R
Input/Output Ports
Rev. 2.60 15 April 1, 2011

HT82M99E/HT82M99A
Low Voltage Reset - LVR The relationship between VDD and VLVR is shown below.
The microcontroller contains a low voltage reset circuit V D D V O P R
in order to monitor the supply voltage of the device. If the 5 .5 V 5 .5 V
supply voltage of the device drops to within the range of
0.9V~VLVR such as might occur when changing the bat-
tery, the LVR will automatically reset the device inter-
nally. V L V R
The LVR includes the following specifications: 2 .7 V

2 .4 V
· For a valid LVR signal, a low voltage (0.9V~VLVR) must
exist for more than 1ms. If the low voltage state does
not exceed 1ms, the LVR will ignore it and will not per-
form a reset function. 0 .9 V
· The LVR uses the ²OR² function with the external
Note: VOPR is the voltage range for proper chip opera-
RES signal to perform a chip reset. tion at 6MHz or 12MHz system clock.
V D D
5 .5 V
V L V R L V R D e te c t V o lta g e
0 .9 V
0 V
R e s e t S ig n a l
R e s e t N o r m a l O p e r a tio n R e s e t
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*1 *2
Low Voltage Reset
Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before entering the normal operation.
*2: A low voltage has to exist for more than 1ms, after that 1ms delay, the device enters a reset mode.
Rev. 2.60 16 April 1, 2011

HT82M99E/HT82M99A
USB with MCU Interface

There are eight registers, including Pipe_ctrl, Address+Remote_WakeUp, STALL, PIPE, SIES, MISC, FIFO 0 and
FIFO 1 in this buffer function.
Register Name Pipe_ctrl Addr.+Remote STALL PIPE SIES MISC FIFO 0 FIFO 1
Mem. Addr. 41H 42H 43H 44H 45H 46H 48H 49H
Reserved Addr. Bank 1, Address 40H, 4AH, 4FH
Register Memory Mapping
Address+Remote_WakeUp register represents current address and remote wake-up function. The initial value is
²00000000² from MSB to LSB.
Register
R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Address
Remote Wake-up Function
Address value
01000010B R/W 0: Not this function
Default value=00000000
1: The function exists
Address+Remote_WakeUp Register
The Pipe_ctrl, STALL and PIPE are bitmap ones. The Pipe_ctrl Register is used for configuring IN (Bit=1) or OUT
(Bit=0) Pipe and only for HT82M99A body. The default is defined as IN Pipe. The PIPE register represents whether the
corresponding endpoint is accessed by host or not. After a USB interrupt signal is being sent out, the MCU can check
which endpoint had been accessed. This register is set only after the host accessed the corresponding endpoint. The
STALL register shows whether the corresponding endpoint works or not. As soon as the endpoint works improperly, the
corresponding bit must be set. The bitmaps are listed as follows:
Register Register Default
R/W Bit7~Bit2 Reserved Bit 1 Bit 0
Name Address Value
Pipe_ctrl R/W 01000001B ¾ Pipe 1 Pipe 0 00000011
STALL R/W 01000011B ¾ Pipe 1 Pipe 0 00000000
PIPE R 01000100B ¾ www.DataSheet.net/

Pipe 1 Pipe 0 00000000
STALL (43H) and PIPE (44H) Registers
The SIES Register is used to indicate the present signal state which the USB SIE received and also determines
whether the USB SIE has to change the device address automatically.
Bit No. Function Read/Write Register Address
7 MNI R/W
6~2 ¾ ¾
01000001B
1 F0_ERR R/W
0 Adr_set R/W
SIES (45H) Registers Table
Rev. 2.60 17 April 1, 2011

HT82M99E/HT82M99A
Function
Read/Write Description
Name
This bit is used to configure the USB SIE to automatically change the device address with
the value of the Address+Remote_WakeUp Register (42H).
When this bit is set to 1 by F/W, the USB SIE will update the device address with the value
of the Address+Remote_WakeUp Register (42H) after the PC Host has successfully read
Adr_set R/W
the data from the device by the IN operation. The USB SIE will clear the bit after updating
the device address.
Otherwise, when this bit is cleared to 0, the USB SIE will update the device address imme-
diately after an address is written to the Address+Remote_WakeUp Register (42H).
This bit is used to indicate when there are some errors that occurred when the FIFO0 is
F0_Err R/W accessed.
This bit is set by the USB SIE and cleared by F/W.
¾ ¾ Unused bit, read as ²0²

NMI R/W This bit is for masking the NAK interrupt when MNI=²1², the default value=²0²
SIES Function Table
The MISC register is actually a command + status to control the desired FIFO action and to show the status of the de-
sired FIFO. Every bit¢s meaning and usage are listed as follows:
Bit No. Function Read/Write Register Address
7 Len0 R/W
6 Ready R
5 Set CMD R/W
4 Sel_pipe1 R/W
01000110B
3 Sel_pipe0 R/W
2 Clear R/W
1 Tx R/W
0 Request www.DataSheet.net/
R/W
MISC (46H) Registers Table
Rev. 2.60 18 April 1, 2011

HT82M99E/HT82M99A
Function
Read/Write Description
Name
After setting the other desired status, FIFO can be requested by setting this bit high active.
Request R/W
After work has been done, this bit must be set low.
Represents the direction and transition end of the MCU accesses. When being set as logic
1, the MCU wants to write data to FIFO. After work has been done, this bit must be set to
Tx R/W logic 0 before terminating the request to represent a transition end. For reading action, this
bit must be set to logic 0 to indicate that the MCU wants to read and must be set to logic 1
after work is done.
Clear R/W Represents MCU clear requested FIFO, even if FIFO is not ready.
Sel_pipe1
R/W Determines which FIFO is desired, ²00² for FIFO 0, ²01² for FIFO 1
Sel_pipe0
Shows that the data in FIFO is setup as command. This bit will be cleared by firmware. So,
Set CMD R/W
even if the MCU is busy, nothing is missed by the SETUP command from the host.
Ready R Indicates that the desired FIFO is ready to work.
Indicates that the host sent a 0-sized packet to the MCU. This bit must be cleared by a
Len0 R/W read action to the corresponding FIFO. Also, this bit will be cleared by the USB SIE after
the next valid SETUP token is received.
MISC Function Table
The HT82M99E/HT82M99A have two 8´8 bidirectional HT82M99E/HT82M99A allows a maximum of 8 bytes of
FIFO for the two endpoints (control and Interrupt). User data in each packet.
can easily read/write the FIFO data by accessing the The HT82M99E/HT82M99A FIFO is written by packet.
corresponding FIFO pointer register (FIFO0, FIFO1). To write to FIFO, the following should be followed:
The following are two examples for reading and writing
· Select a set of FIFO, set in the write mode (MISC TX
the FIFO data:
bit = 1), and set the REQ bit to ²1²
HT82M99E/HT82M99A FIFO is read by packet. To read · Check the ready bit until the status = 1
from FIFO, the following should be followed: · Write through the FIFO pointer register and take down
· Select one set of FIFO, set in the read mode (MISC the data number that has been written
TX bit = 0), and set the REQ bit to ²1².
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· Repeat steps 2 and 3 until writing is complete or the

· Check the ready bit until the status = 1 ready bit becomes 0 which indicates that the FIFO no
· Read through the FIFO pointer register, and record longer allows any data writing.
the data number that has been read. · Set MISC TX bit = 0
· Repeat steps 2 and 3 until the ready bit becomes 0 · Clear the REQ bit to 0. Complete writing.
which indicates the end of the FIFO data reading. User writes the data through the FIFO pointer register,
· Set MISC TX bit = 1 user has to record the number of bytes that have been
· Clear the REQ bit to 0. Complete reading. written. The HT82M99E allows a maximum of 8 bytes of
User reads the data through the FIFO pointer register, data in each packet.
user has to record the number of bytes to be read. The
Rev. 2.60 19 April 1, 2011

HT82M99E/HT82M99A
There are some timing constrains and usages illustrated here. By setting the MISC register, the MCU can perform read-
ing, writing and clearing actions. There are some examples shown in the following table for endpoint FIFO reading, writ-
ing and clearing.
Actions MISC Setting Flow and Status
00H®01H®delay of 2ms, check 41H®read* from FIFO0 register

Read FIFO0 sequence
and check if not ready (01H)®03H®02H
0AH®0BH®delay of 2ms, check 4BH®write* to FIFO1 register and

Write FIFO1 sequence
check if not ready (0BH)®09H®08H
00H®01H®delay of 2ms, check 41H (if ready) or 01H (if not

Check whether FIFO0 can be read or not
ready)®00H
0AH®0BH®delay of 2ms, check 4BH (if ready) or 0BH (if not

Check whether FIFO1 can be written to or not
ready)®0AH
Write 0-sized packet sequence to FIFO 0 02H®03H®delay of 2ms, check 43H®01H®00H
Note: *: There are 2ms gap existing between 2 reading actions or between 2 writing actions
Register Name R/W Register Address Bit7~Bit0
FIFO 0 R/W 01001000B Data7~Data0
FIFO 1 R/W 01001001B Data7~Data0
FIFO Register Address Table
USB Active Pipe Timing

The USB active pipe accessed by the host cannot be used by the MCU simultaneously. When the host finishes its work,
the signal, a USB_INT will be produced to tell the MCU that the pipe can be used and the acted pipe No. will be shown
in the signal, ACT_PIPE as well. The timing is illustrated in the Figure below.
A C T _ P IP E L a s t A c te d P ip e
U S B _ IN T
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USB Active Pipe Timing
Suspend Wake-Up and Remote Wake-Up the Resume line (bit 3 of the USC) is set. In order to
If there is no signal on the USB bus for over 3ms, the make the HT82M99E function properly, the programmer
HT82M99E will go into a suspend mode. The Suspend must set the USBCKEN (bit 3 of the SCC) to 1 and clear
line (bit 0 of the USC) will be set to 1 and a USB interrupt the SUSP2 (bit4 of the SCC). Since the Resume signal
is triggered to indicate that the HT82M99E should jump will be cleared before the Idle signal is sent out by the
to the suspend state to meet the 500mA USB suspend host and the Suspend line (bit 0 of the USC) is going to
current spec. ²0². So when the MCU is detecting the Suspend line
(bit0 of the USC), the Resume line should be remem-
In order to meet the 500mA suspend current, the pro- bered and taken into consideration.
grammer should disable the USB clock by clearing the
After finishing the resume signal, the suspend line will
USBCKEN (bit3 of the SCC) to ²0². The suspend cur-
go inactive and a USB interrupt is triggered. The follow-
rent is 400mA.
ing is the timing diagram:
The user can also further decrease the suspend current
to 250mA by setting the SUSP2 (bit4 of the SCC). But if S U S P E N D
the SUSP2 is set, the user has to make sure not to en-
able the LVR OPT option, otherwise the HT82M99E will U S B R e s u m e S ig n a l
be reset.
When the resume signal is sent out by the host, the U S B _ IN T
HT82M99E will wake-up the MCU by USB interrupt and
Rev. 2.60 20 April 1, 2011

HT82M99E/HT82M99A
The device with remote wake-up function can wake-up and SUSB (bit 5 of the USR). If SPS2=1, and SUSB=0,
the USB Host by sending a wake-up pulse through the HT82M99E is defined as PS2 interface, pin USBD-
RMWK (bit 1 of USC). Once the USB Host receive the is now defined as PS2 Data pin and USBD+ is now de-
wake-up signal from the HT82M99E, it will send a Re- fined as PS2 Clk pin. The user can easily read or write to
sume signal to the device. The timing is as follows: the PS2 Data or PS2 Clk pin by accessing the corre-
sponding bit PS2DAI (bit 4 of the USC), PS2CKI (bit 5 of
S U S P E N D the USC), PS2DAO (bit 6 of the USC) and S2CKO (bit 7
M in . 1 U S B C L K
of the USC) respectively.
R M W K The user should make sure that in order to read the data
properly, the corresponding output bit must be set to ²1².
M in .2 .5 m s For example, if user wants to read the PS2 Data by
U S B R e s u m e S ig n a l
reading PS2DAI, the PS2DAO should be set to ²1². Oth-
erwise it always read a ²0².
U S B _ IN T
If SPS2=0, and SUSB=1, the HT82M99E is defined as a
USB interface. Both the USBD- and USBD+ are driven
To Configure the HT82M99E as PS2 Device by the USB SIE of the HT82M99E. User only writes or
reads the USB data through the corresponding FIFO.
The HT82M99E can be defined as a USB interface or a
PS2 interface by configuring the SPS2 (bit 4 of the USR) Both SPS2 and SUSB default is ²0².
I/O Port Special Registers Definition

· Port-A (12H) - PA
Register Bits Labels Read/Write Functions

I/O (R/W) has pull-low and pull-high ROM code option.
0 PA0 R/W
Has falling edge wake-up ROM code option.
I/O (R/W) has pull-low and pull-high option.
1 PA1 R/W
Has falling edge wake-up option.
2 PA2 R/W
Has falling edge and rising edge wake-up option.
3 PA3 R/W www.DataSheet.net/
PA Has falling edge and rising edge wake-up option.

(12H) I/O (R/W) has pull-high option.
4 PA4 R/W
I/O (R/W) has pull-high option.
5 PA5 R/W
6 PA6 R/W
7 PA7 R/W
Has falling edge wake-up option, pin-shared with timer input pin.
· Port-A Control (13H) - PAC

This port configure the input or output mode of Port-A
· Port-B Control (14H) - PB

0~1 ¾ ¾ Reserved bit.
2 PB2 R/W I/O (R/W), has pull-low and pull-high option.
PB 3 PB3 R/W I/O (R/W), has pull-low and pull-high option.

(14H) 4 PB4 R/W I/O (R/W), has pull-high option, can wake-up.
5~6 ¾ ¾ Reserved bit.
7 PB7 R/W I/O (R/W), has pull-high option and has wake-up capability.
Rev. 2.60 21 April 1, 2011

HT82M99E/HT82M99A
· Port-B Control (15H) - PBC
This port configures the input or output mode of Port-B for I/O mode
USB/PS2 Status and Control Register USC (Address 0X1A)

USB suspend mode status bit. When 1, indicates that the USB
0 SUSPEND R
system entry is in suspend mode.
1 RMOT_WK W USB remote wake-up signal. Default value is 0.
2 URST_FLAG R/W USB bus reset event flag. Default value is 0.
When RESUME_OUT EVENT, RESUME_O is set to 1. Default
3 RESUME_O R
USC value is 0.
(0X1A) 4 PS2_DAI R USBD-/DATA input
5 PS2_CKI R USBD+/CLK input
Output for driving USBD-/DATA pin, when working under 3D PS2
6 PS2_DAO W
mouse function. Default value is 1.
Output for driving USBD-/DATA pin, when working under 3D PS2
7 PS2_CKO W
mouse function. Default value is 1.
Endpoint Interrupt Status Register USR (Address 0X1B)

The USR (USB endpoint interrupt status register) register is used to indicate which endpoint is accessed and to select
the serial bus (PS2 or USB). The endpoint request flags (EP0IF, EP1IF) are used to indicate which endpoints are ac-
cessed. If an endpoint is accessed, the related endpoint request flag will be set to ²1² and a USB interrupt will occur (If a
USB interrupt is enabled and the stack is not full). When the active endpoint request flag is served, the endpoint request
flag has to be cleared to ²0².
When set to ²1², indicates an endpoint 0 interrupt event. Must wait

for the MCU to process the interrupt event and clear this bit by
0 EP0IF R/W
firmware. This bit must be ²0², then the next interrupt event will be
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processed. Default value is ²0².
When set to ²1², indicates an endpoint 1 interrupt event. Must wait

for the MCU to process the interrupt event, then clear this bit by
1 EP1IF R/W
firmware. This bit must be ²0², then the next interrupt event will be
processed. Default value is ²0².
USR 2~3 ¾ R/W Reserved bit, set to ²0²
(0X1B)
When set to ²1², indicates that the chip is working under PS2
4 SELPS2 R/W
mode. Default value is ²0².
When set to ²1², indicates that the chip is working under USB
5 SELUSB R/W
mode. Default value is 0.
6 ¾ R/W Reserved bit, set to ²0²
This flag is used to show that the MCU is in USB mode (Bit=1).
7 USB_flag R/W This bit is R/W by FW and will be cleared to zero after power-on re-
set. The default is ²0².
Rev. 2.60 22 April 1, 2011

HT82M99E/HT82M99A
Clock Control Register SCC (Address 0X1C)

There is a system clock control register implemented to select the clock used in the MCU. This register consists of USB
clock control bit (USBCKEN), second suspend mode control bit (SUSPEND2) and system clock selection (SCLKSEL).
2~0 ¾ R/W Reserved bit.
USB clock control bit. When set to ²1², indicates a USBCK ON,
3 USBCKEN R/W
else USBCK OFF. Default value is ²0².
This bit is used to reduce power consumption in the suspend
mode. In the normal mode this bit must be cleared to zero(De-
4 SUSPEND2 R/W fault=²0²). In the HALT mode this bit should be set high to reduce
power consumption and LVR with no function. In the USB mode
this bit cannot be set high.
SCC
(0X1C) 5 ¾ R/W Reserved bit.
System clock 6MHz or 12MHz option, when working on external
oscillator mode. Default value is ²0².
6 SCLKSEL R/W 0: Operating at external 12MHz mode
1: Operating at external 6MHz mode
Default value is ²0².
This flag is used to show that the MCU is in PS2 mode (Bit=1).
7 PS2_flag R/W This bit is R/W by FW and will be cleared to zero after power-on re-
set. The default is ²0².
Table High Byte Pointer for Current Table Read TBHP (Address 0X1F)
TBHP
2~0 ¾ R/W Store current table read bit10~bit8 data
(0X1F)
Configuration Options
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No. Option
1 WDT clock source: RC (system/4) (default: T1)
2 WDT clock source: enable/disable for normal mode (default: disable)
PA0~PA7 ,PB4, PB7 wake-up by bit (PA2, PA3 both wake-up by falling or rising edge)
3
(default: non wake-up)
4 PA0~PA7 pull-high by bit (default: Pull-high)
5 PB pull-high by nibble (default: Pull-high)
6 2.7 V (error 0.3V) LVR enable/disable (default: enable)
7 PA0~PA3, PB2, PB3 Pull-low by bit (default: non pull-low 30kW)
8 ²CLR WDT², 1 or 2 instructions
9 TBHP enable/disable (default: disable)
10 PA output mode (CMOS/NMOS/PMOS) by bit (default: CMOS)
The LVR voltage is define as 2.7V±0.3V and default is enable.
Rev. 2.60 23 April 1, 2011

HT82M99E/HT82M99A
Application Circuits
Crystal or Ceramic Resonator for Multiple I/O Applications - HT82M99E
5 W * 3 3 W *
V D D V D D P A 0 ~ P A 7
U S B -
* P B 2 ~ P B 4
1 0 m F 1 0 0 k W 0 .1 m F
0 .1 m F 1 M W ***
U S B + P B 7
V S S 2 2 p F
O S C 1 1 .5 k W
** X 1 V 3 3 O
0 .1 m F
* 2 2 p F
5 W 4 7 p F *
O S C 2
1 0 k W 3 3 W *
** U S B D -/D A T A
R E S
0 .1 m F * 0 .1 m F * 4 7 p F * * 4 7 p F
V S S 3 3 W *
U S B D + /C L K
* 4 7 p F
H T 8 2 M 9 9 E
Note: The resistance and capacitance for the reset circuit should be designed in such a way as to ensure that the VDD
is stable and remains within a valid operating voltage range before bringing RES to high.
X1 can use 6MHz or 12MHz, X1 as close OSC1 & OSC2 as possible
Components with * are used for EMC issue.
Components with ** are used for resonator only.
Components with *** are used for 12MHz application.
Crystal or Ceramic Resonator for Multiple I/O Applications - HT82M99A
V D D
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V D D P A 0 ~ P A 7
U S B - 1 0 m F 1 0 0 k W 0 .1 m F P B 2 ~ P B 4
U S B + P B 7
V S S 2 2 p F
O S C 1 1 .5 k W
* X 1 V 3 3 O
0 .1 m F
2 2 p F
O S C 2
* U S B D -/D A T A
R E S
0 .1 m F
V S S
U S B D + /C L K
H T 8 2 M 9 9 A
Note: X1 can use 6MHz or 12MHz, X1 as close OSC1 & OSC2 as possible
Components with * are used for resonator only.
Rev. 2.60 24 April 1, 2011

HT82M99E/HT82M99A
Instruction Set
Introduction subtract instruction mnemonics to enable the necessary
C e n t ra l t o t he s uc c es s f ul oper a t i on o f a n y arithmetic to be carried out. Care must be taken to en-
microcontroller is its instruction set, which is a set of pro- sure correct handling of carry and borrow data when re-
gram instruction codes that directs the microcontroller to sults exceed 255 for addition and less than 0 for
perform certain operations. In the case of Holtek subtraction. The increment and decrement instructions
microcontrollers, a comprehensive and flexible set of INC, INCA, DEC and DECA provide a simple means of
over 60 instructions is provided to enable programmers increasing or decreasing by a value of one of the values
to implement their application with the minimum of pro- in the destination specified.
gramming overheads.
Logical and Rotate Operations
For easier understanding of the various instruction
The standard logical operations such as AND, OR, XOR
codes, they have been subdivided into several func-
and CPL all have their own instruction within the Holtek
tional groupings.
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
Instruction Timing
through the Accumulator which may involve additional
Most instructions are implemented within one instruc- programming steps. In all logical data operations, the
tion cycle. The exceptions to this are branch, call, or ta- zero flag may be set if the result of the operation is zero.
ble read instructions where two instruction cycles are Another form of logical data manipulation comes from
required. One instruction cycle is equal to 4 system the rotate instructions such as RR, RL, RRC and RLC
clock cycles, therefore in the case of an 8MHz system which provide a simple means of rotating one bit right or
oscillator, most instructions would be implemented left. Different rotate instructions exist depending on pro-
within 0.5ms and branch or call instructions would be im- gram requirements. Rotate instructions are useful for
plemented within 1ms. Although instructions which re- serial port programming applications where data can be
quire one more cycle to implement are generally limited rotated from an internal register into the Carry bit from
to the JMP, CALL, RET, RETI and table read instruc- where it can be examined and the necessary serial bit
tions, it is important to realize that any other instructions set high or low. Another application where rotate data
which involve manipulation of the Program Counter Low operations are used is to implement multiplication and
register or PCL will also take one more cycle to imple- division calculations.
ment. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one Branches and Control Transfer
more cycle will be required. Examples of such instruc- Program branching takes the form of either jumps to
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tions would be ²CLR PCL² or ²MOV PCL, A². For the specified locations using the JMP instruction or to a sub-
case of skip instructions, it must be noted that if the re- routine using the CALL instruction. They differ in the
sult of the comparison involves a skip operation then sense that in the case of a subroutine call, the program
this will also take one more cycle, if no skip is involved must return to the instruction immediately when the sub-
then only one cycle is required. routine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
Moving and Transferring Data
the program to jump back to the address right after the
The transfer of data within the microcontroller program CALL instruction. In the case of a JMP instruction, the
is one of the most frequently used operations. Making program simply jumps to the desired location. There is
use of three kinds of MOV instructions, data can be no requirement to jump back to the original jumping off
transferred from registers to the Accumulator and point as in the case of the CALL instruction. One special
vice-versa as well as being able to move specific imme- and extremely useful set of branch instructions are the
diate data directly into the Accumulator. One of the most conditional branches. Here a decision is first made re-
important data transfer applications is to receive data garding the condition of a certain data memory or indi-
from the input ports and transfer data to the output ports. vidual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
Arithmetic Operations jump to the following instruction. These instructions are
The ability to perform certain arithmetic operations and the key to decision making and branching within the pro-
data manipulation is a necessary feature of most gram perhaps determined by the condition of certain in-
microcontroller applications. Within the Holtek put switches or by the condition of internal data bits.
microcontroller instruction set are a range of add and
Rev. 2.60 25 April 1, 2011

HT82M99E/HT82M99A
Bit Operations Other Operations

The ability to provide single bit operations on Data Mem- In addition to the above functional instructions, a range
ory is an extremely flexible feature of all Holtek of other instructions also exist such as the ²HALT² in-
microcontrollers. This feature is especially useful for struction for Power-down operations and instructions to
output port bit programming where individual bits or port control the operation of the Watchdog Timer for reliable
pins can be directly set high or low using either the ²SET program operations under extreme electric or electro-
[m].i² or ²CLR [m].i² instructions respectively. The fea- magnetic environments. For their relevant operations,
ture removes the need for programmers to first read the refer to the functional related sections.
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port Instruction Set Summary
with the correct new data. This read-modify-write pro- The following table depicts a summary of the instruction
cess is taken care of automatically when these bit oper- set categorised according to function and can be con-
ation instructions are used. sulted as a basic instruction reference using the follow-
ing listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using regis-
ters. However, when working with large amounts of x: Bits immediate data
fixed data, the volume involved often makes it inconve- m: Data Memory address
nient to store the fixed data in the Data Memory. To over-
A: Accumulator
come this problem, Holtek microcontrollers allow an
area of Program Memory to be setup as a table where i: 0~7 number of bits
data can be directly stored. A set of easy to use instruc- addr: Program memory address
tions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.
Mnemonic Description Cycles Flag Affected

Arithmetic
ADD A,[m] Add Data Memory to ACC 1 Z, C, AC, OV
ADDM A,[m] Add ACC to Data Memory 1Note Z, C, AC, OV
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ADD A,x Add immediate data to ACC 1 Z, C, AC, OV

ADC A,[m] Add Data Memory to ACC with Carry 1 Z, C, AC, OV
ADCM A,[m] Add ACC to Data memory with Carry 1Note Z, C, AC, OV
SUB A,x Subtract immediate data from the ACC 1 Z, C, AC, OV
SUB A,[m] Subtract Data Memory from ACC 1 Z, C, AC, OV
SUBM A,[m] Subtract Data Memory from ACC with result in Data Memory 1Note Z, C, AC, OV
SBC A,[m] Subtract Data Memory from ACC with Carry 1 Z, C, AC, OV
SBCM A,[m] Subtract Data Memory from ACC with Carry, result in Data Memory 1Note Z, C, AC, OV
DAA [m] Decimal adjust ACC for Addition with result in Data Memory 1Note C
Logic Operation
AND A,[m] Logical AND Data Memory to ACC 1 Z
OR A,[m] Logical OR Data Memory to ACC 1 Z
XOR A,[m] Logical XOR Data Memory to ACC 1 Z
ANDM A,[m] Logical AND ACC to Data Memory 1Note Z
ORM A,[m] Logical OR ACC to Data Memory 1Note Z
XORM A,[m] Logical XOR ACC to Data Memory 1Note Z
AND A,x Logical AND immediate Data to ACC 1 Z
OR A,x Logical OR immediate Data to ACC 1 Z
XOR A,x Logical XOR immediate Data to ACC 1 Z
CPL [m] Complement Data Memory 1Note Z
CPLA [m] Complement Data Memory with result in ACC 1 Z
Increment & Decrement
INCA [m] Increment Data Memory with result in ACC 1 Z
INC [m] Increment Data Memory 1Note Z
DECA [m] Decrement Data Memory with result in ACC 1 Z
DEC [m] Decrement Data Memory 1Note Z
Rev. 2.60 26 April 1, 2011

HT82M99E/HT82M99A
Mnemonic Description Cycles Flag Affected

Rotate
RRA [m] Rotate Data Memory right with result in ACC 1 None
RR [m] Rotate Data Memory right 1Note None
RRCA [m] Rotate Data Memory right through Carry with result in ACC 1 C
RRC [m] Rotate Data Memory right through Carry 1Note C
RLA [m] Rotate Data Memory left with result in ACC 1 None
RL [m] Rotate Data Memory left 1Note None
RLCA [m] Rotate Data Memory left through Carry with result in ACC 1 C
RLC [m] Rotate Data Memory left through Carry 1Note C
Data Move
MOV A,[m] Move Data Memory to ACC 1 None
MOV [m],A Move ACC to Data Memory 1Note None
MOV A,x Move immediate data to ACC 1 None
Bit Operation
CLR [m].i Clear bit of Data Memory 1Note None
SET [m].i Set bit of Data Memory 1Note None
Branch
JMP addr Jump unconditionally 2 None
SZ [m] Skip if Data Memory is zero 1Note None
SZA [m] Skip if Data Memory is zero with data movement to ACC 1note None
SZ [m].i Skip if bit i of Data Memory is zero 1Note None
SNZ [m].i Skip if bit i of Data Memory is not zero 1Note None
SIZ [m] Skip if increment Data Memory is zero 1Note None
SDZ [m] Skip if decrement Data Memory is zero 1Note None
SIZA [m] Skip if increment Data Memory is zero with result in ACC 1Note None
SDZA [m] Skip if decrement Data Memory is zero with result in ACC 1Note None
CALL addr Subroutine call 2 None
RET Return from subroutine 2 None
RET A,x Return from subroutine and load immediate data to ACC 2 None
RETI Return from interrupt 2 None
Table Read www.DataSheet.net/
TABRDC [m] Read table (current page) to TBLH and Data Memory 2Note None
TABRDL [m] Read table (last page) to TBLH and Data Memory 2Note None
Miscellaneous
NOP No operation 1 None
CLR [m] Clear Data Memory 1Note None
SET [m] Set Data Memory 1Note None
CLR WDT Clear Watchdog Timer 1 TO, PDF
CLR WDT1 Pre-clear Watchdog Timer 1 TO, PDF
CLR WDT2 Pre-clear Watchdog Timer 1 TO, PDF
SWAP [m] Swap nibbles of Data Memory 1Note None
SWAPA [m] Swap nibbles of Data Memory with result in ACC 1 None
HALT Enter power down mode 1 TO, PDF
Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.
Rev. 2.60 27 April 1, 2011

HT82M99E/HT82M99A
Instruction Definition
ADC A,[m] Add Data Memory to ACC with Carry

Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation ACC ¬ ACC + [m] + C
Affected flag(s) OV, Z, AC, C
ADCM A,[m] Add ACC to Data Memory with Carry

Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation [m] ¬ ACC + [m] + C
ADD A,[m] Add Data Memory to ACC

Description The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation ACC ¬ ACC + [m]
ADD A,x Add immediate data to ACC

Description The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation ACC ¬ ACC + x
ADDM A,[m] Add ACC to Data Memory

Description The contents of the specified Data Memory and the Accumulator are added. The result is
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stored in the specified Data Memory.

Operation [m] ¬ ACC + [m]
AND A,[m] Logical AND Data Memory to ACC

Description Data in the Accumulator and the specified Data Memory perform a bitwise logical AND op-
eration. The result is stored in the Accumulator.
Operation ACC ¬ ACC ²AND² [m]
Affected flag(s) Z
AND A,x Logical AND immediate data to ACC

Description Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation ACC ¬ ACC ²AND² x
Affected flag(s) Z
ANDM A,[m] Logical AND ACC to Data Memory

Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op-
eration. The result is stored in the Data Memory.
Operation [m] ¬ ACC ²AND² [m]
Affected flag(s) Z
Rev. 2.60 28 April 1, 2011

HT82M99E/HT82M99A
CALL addr Subroutine call

Description Unconditionally calls a subroutine at the specified address. The Program Counter then in-
crements by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruc-
tion.
Operation Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s) None
CLR [m] Clear Data Memory

Description Each bit of the specified Data Memory is cleared to 0.
Operation [m] ¬ 00H
CLR [m].i Clear bit of Data Memory

Description Bit i of the specified Data Memory is cleared to 0.
Operation [m].i ¬ 0
CLR WDT Clear Watchdog Timer

Description The TO, PDF flags and the WDT are all cleared.
Operation WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s) TO, PDF
CLR WDT1 Pre-clear Watchdog Timer

www.DataSheet.net/
Description The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc-
tion with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Re-
petitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
TO ¬ 0
PDF ¬ 0
CLR WDT2 Pre-clear Watchdog Timer

Description The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc-
tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re-
petitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
TO ¬ 0
PDF ¬ 0
Rev. 2.60 29 April 1, 2011

HT82M99E/HT82M99A
CPL [m] Complement Data Memory

Description Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation [m] ¬ [m]
Affected flag(s) Z
CPLA [m] Complement Data Memory with result in ACC

Description Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation ACC ¬ [m]
Affected flag(s) Z
DAA [m] Decimal-Adjust ACC for addition with result in Data Memory
Description Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value re-
sulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by add-
ing 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation [m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s) C
DEC [m] Decrement Data Memory

www.DataSheet.net/
Description Data in the specified Data Memory is decremented by 1.

Operation [m] ¬ [m] - 1
Affected flag(s) Z
DECA [m] Decrement Data Memory with result in ACC

Description Data in the specified Data Memory is decremented by 1. The result is stored in the Accu-
mulator. The contents of the Data Memory remain unchanged.
Operation ACC ¬ [m] - 1
Affected flag(s) Z
HALT Enter power down mode

Description This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation TO ¬ 0
PDF ¬ 1
Rev. 2.60 30 April 1, 2011

HT82M99E/HT82M99A
INC [m] Increment Data Memory

Description Data in the specified Data Memory is incremented by 1.
Operation [m] ¬ [m] + 1
Affected flag(s) Z
INCA [m] Increment Data Memory with result in ACC

Description Data in the specified Data Memory is incremented by 1. The result is stored in the Accumu-
lator. The contents of the Data Memory remain unchanged.
Operation ACC ¬ [m] + 1
Affected flag(s) Z
JMP addr Jump unconditionally

Description The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation Program Counter ¬ addr
MOV A,[m] Move Data Memory to ACC

Description The contents of the specified Data Memory are copied to the Accumulator.
MOV A,x Move immediate data to ACC

Description The immediate data specified is loaded into the Accumulator.
Operation ACC ¬ x
www.DataSheet.net/
MOV [m],A Move ACC to Data Memory

Description The contents of the Accumulator are copied to the specified Data Memory.
Operation [m] ¬ ACC
NOP No operation
Description No operation is performed. Execution continues with the next instruction.
Operation No operation
OR A,[m] Logical OR Data Memory to ACC

Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper-
ation. The result is stored in the Accumulator.
Operation ACC ¬ ACC ²OR² [m]
Affected flag(s) Z
Rev. 2.60 31 April 1, 2011

HT82M99E/HT82M99A
OR A,x Logical OR immediate data to ACC

Description Data in the Accumulator and the specified immediate data perform a bitwise logical OR op-
Operation ACC ¬ ACC ²OR² x
Affected flag(s) Z
ORM A,[m] Logical OR ACC to Data Memory

Description Data in the specified Data Memory and the Accumulator perform a bitwise logical OR oper-
ation. The result is stored in the Data Memory.
Operation [m] ¬ ACC ²OR² [m]
Affected flag(s) Z
RET Return from subroutine

Description The Program Counter is restored from the stack. Program execution continues at the re-
stored address.
Operation Program Counter ¬ Stack
RET A,x Return from subroutine and load immediate data to ACC
Description The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
ACC ¬ x
RETI Return from interrupt

Description The Program Counter is restored from the stack and the interrupts are re-enabled by set-
ting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending
when the RETI instruction is executed, the pending Interrupt routine will be processed be-
www.DataSheet.net/
fore returning to the main program.

EMI ¬ 1
RL [m] Rotate Data Memory left

Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation [m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
RLA [m] Rotate Data Memory left with result in ACC

Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory re-
main unchanged.
Operation ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Rev. 2.60 32 April 1, 2011

HT82M99E/HT82M99A
RLC [m] Rotate Data Memory left through Carry

Description The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation [m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s) C
RLCA [m] Rotate Data Memory left through Carry with result in ACC
Description Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s) C
RR [m] Rotate Data Memory right

Description The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation [m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
RRA [m] Rotate Data Memory right with result in ACC

Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 ro-
tated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation ACC.i ¬ [m].(i+1); (i = 0~6) www.DataSheet.net/
ACC.7 ¬ [m].0
RRC [m] Rotate Data Memory right through Carry

Description The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation [m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s) C
RRCA [m] Rotate Data Memory right through Carry with result in ACC
Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re-
places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s) C
Rev. 2.60 33 April 1, 2011

HT82M99E/HT82M99A
SBC A,[m] Subtract Data Memory from ACC with Carry

Description The contents of the specified Data Memory and the complement of the carry flag are sub-
tracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation ACC ¬ ACC - [m] - C
SBCM A,[m] Subtract Data Memory from ACC with Carry and result in Data Memory
Description The contents of the specified Data Memory and the complement of the carry flag are sub-
tracted from the Accumulator. The result is stored in the Data Memory. Note that if the re-
sult of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation [m] ¬ ACC - [m] - C
SDZ [m] Skip if decrement Data Memory is 0

Description The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation [m] ¬ [m] - 1
Skip if [m] = 0
SDZA [m] Skip if decrement Data Memory is zero with result in ACC
Description The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy in-
struction while the next instruction is fetched, it is a two cycle instruction. If the result is not
www.DataSheet.net/
0, the program proceeds with the following instruction.

Operation ACC ¬ [m] - 1
Skip if ACC = 0
SET [m] Set Data Memory

Description Each bit of the specified Data Memory is set to 1.
Operation [m] ¬ FFH
SET [m].i Set bit of Data Memory

Description Bit i of the specified Data Memory is set to 1.
Operation [m].i ¬ 1
Rev. 2.60 34 April 1, 2011

HT82M99E/HT82M99A
SIZ [m] Skip if increment Data Memory is 0

Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation [m] ¬ [m] + 1
Skip if [m] = 0
SIZA [m] Skip if increment Data Memory is zero with result in ACC
Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy in-
struction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation ACC ¬ [m] + 1
Skip if ACC = 0
SNZ [m].i Skip if bit i of Data Memory is not 0

Description If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this re-
quires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation Skip if [m].i ¹ 0
SUB A,[m] Subtract Data Memory from ACC

Description The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
www.DataSheet.net/
Operation ACC ¬ ACC - [m]

SUBM A,[m] Subtract Data Memory from ACC with result in Data Memory
Description The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation [m] ¬ ACC - [m]
SUB A,x Subtract immediate data from ACC

Description The immediate data specified by the code is subtracted from the contents of the Accumu-
lator. The result is stored in the Accumulator. Note that if the result of subtraction is nega-
tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation ACC ¬ ACC - x
Rev. 2.60 35 April 1, 2011

HT82M99E/HT82M99A
SWAP [m] Swap nibbles of Data Memory

Description The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation [m].3~[m].0 « [m].7 ~ [m].4
SWAPA [m] Swap nibbles of Data Memory with result in ACC

Description The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
SZ [m] Skip if Data Memory is 0

Description If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruc-
tion.
Operation Skip if [m] = 0
SZA [m] Skip if Data Memory is 0 with data movement to ACC

Description The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruc-
tion while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Skip if [m] = 0
www.DataSheet.net/
SZ [m].i Skip if bit i of Data Memory is 0

Description If bit i of the specified Data Memory is 0, the following instruction is skipped. As this re-
quires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation Skip if [m].i = 0
TABRDC [m] Read table (current page) to TBLH and Data Memory
Description The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation [m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
TABRDL [m] Read table (last page) to TBLH and Data Memory
Description The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation [m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Rev. 2.60 36 April 1, 2011

HT82M99E/HT82M99A
XOR A,[m] Logical XOR Data Memory to ACC

Description Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR op-
Operation ACC ¬ ACC ²XOR² [m]
Affected flag(s) Z
XORM A,[m] Logical XOR ACC to Data Memory

Description Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR op-
eration. The result is stored in the Data Memory.
Operation [m] ¬ ACC ²XOR² [m]
Affected flag(s) Z
XOR A,x Logical XOR immediate data to ACC

Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation ACC ¬ ACC ²XOR² x
Affected flag(s) Z
www.DataSheet.net/
Rev. 2.60 37 April 1, 2011

HT82M99E/HT82M99A
Package Information
16-pin NSOP (150mil) Outline Dimensions
1 6 9
A B
1 8
C '
G
D H
E F a
· MS-012
Dimensions in inch
Symbol
Min. Nom. Max.
A 0.228 ¾ 0.244
B 0.150 ¾ 0.157
C 0.012 ¾ 0.020
C¢ 0.386 ¾ 0.402
D ¾ ¾ 0.069
E ¾ 0.050 ¾
F 0.004 ¾ 0.010
G 0.016 ¾ 0.050
¾
www.DataSheet.net/
H 0.007 0.010
a 0° ¾ 8°
Dimensions in mm
Symbol
Min. Nom. Max.
A 5.79 ¾ 6.20
B 3.81 ¾ 3.99
C 0.30 ¾ 0.51
C¢ 9.80 ¾ 10.21
D ¾ ¾ 1.75
E ¾ 1.27 ¾
F 0.10 ¾ 0.25
G 0.41 ¾ 1.27
H 0.18 ¾ 0.25
a 0° ¾ 8°
Rev. 2.60 38 April 1, 2011

HT82M99E/HT82M99A
18-pin DIP (300mil) Outline Dimensions
A A
1 8 1 0 1 8 1 0
B B
1 9 1 9
H H
C C
D D
E G I E G I
F F
Fig1. Full Lead Packages Fig2. 1/2 Lead Packages
· MS-001d (see fig1)
Dimensions in inch
Symbol
Min. Nom. Max.
A 0.880 ¾ 0.920
B 0.240 ¾ 0.280
C 0.115 ¾ 0.195
D 0.115 ¾ 0.150
E 0.014 ¾ 0.022
F 0.045 ¾ 0.070
G ¾ 0.100 ¾
H 0.300 ¾ 0.325
I ¾ www.DataSheet.net/
0.430 ¾
Dimensions in mm
Symbol
Min. Nom. Max.
A 22.35 ¾ 23.37
B 6.10 ¾ 7.11
C 2.92 ¾ 4.95
D 2.92 ¾ 3.81
E 0.36 ¾ 0.56
F 1.14 ¾ 1.78
G ¾ 2.54 ¾
H 7.62 ¾ 8.26
I ¾ 10.92 ¾
Rev. 2.60 39 April 1, 2011

HT82M99E/HT82M99A
Dimensions in inch
Symbol
Min. Nom. Max.
A 0.845 ¾ 0.880
B 0.240 ¾ 0.280
C 0.115 ¾ 0.195
D 0.115 ¾ 0.150
E 0.014 ¾ 0.022
F 0.045 ¾ 0.070
G ¾ 0.100 ¾
H 0.300 ¾ 0.325
I ¾ 0.430 ¾
Dimensions in mm
Symbol
Min. Nom. Max.
A 21.46 ¾ 22.35
B 6.10 ¾ 7.11
C 2.92 ¾ 4.95
D 2.92 ¾ 3.81
E 0.36 ¾ 0.56
F 1.14 ¾ 1.78
G ¾ 2.54 ¾
H 7.62 ¾ 8.26
I ¾ 10.92 ¾
www.DataSheet.net/
Rev. 2.60 40 April 1, 2011

HT82M99E/HT82M99A
· MO-095a (see fig2)
Dimensions in inch
Symbol
Min. Nom. Max.
A 0.845 ¾ 0.885
B 0.275 ¾ 0.295
C 0.120 ¾ 0.150
D 0.110 ¾ 0.150
E 0.014 ¾ 0.022
F 0.045 ¾ 0.060
G ¾ 0.100 ¾
H 0.300 ¾ 0.325
I ¾ 0.430 ¾
Dimensions in mm
Symbol
Min. Nom. Max.
A 21.46 ¾ 22.48
B 6.99 ¾ 7.49
C 3.05 ¾ 3.81
D 2.79 ¾ 3.81
E 0.36 ¾ 0.56
F 1.14 ¾ 1.52
G ¾ 2.54 ¾
H 7.62 ¾ 8.26
I ¾ 10.92 ¾
www.DataSheet.net/
Rev. 2.60 41 April 1, 2011

HT82M99E/HT82M99A
20-pin DIP (300mil) Outline Dimensions
A A
2 0 1 1 2 0 1 1
B B
1 1 0 1 1 0
H H
C C
D D
E F G I E F G I
Fig1. Full Lead Packages Fig2. 1/2 Lead Packages
Dimensions in inch
Symbol
Min. Nom. Max.
A 0.980 ¾ 1.060
B 0.240 ¾ 0.280
C 0.115 ¾ 0.195
D 0.115 ¾ 0.150
E 0.014 ¾ 0.022
F 0.045 ¾ 0.070
G ¾ 0.100 ¾
H 0.300 ¾ 0.325
I ¾ www.DataSheet.net/
0.430 ¾
Dimensions in mm
Symbol
Min. Nom. Max.
A 24.89 ¾ 26.92
B 6.10 ¾ 7.11
C 2.92 ¾ 4.95
D 2.92 ¾ 3.81
E 0.36 ¾ 0.56
F 1.14 ¾ 1.78
G ¾ 2.54 ¾
H 7.62 ¾ 8.26
I ¾ 10.92 ¾
Rev. 2.60 42 April 1, 2011

HT82M99E/HT82M99A
· MO-095a (see fig2)
Dimensions in inch
Symbol
Min. Nom. Max.
A 0.945 ¾ 0.985
B 0.275 ¾ 0.295
C 0.120 ¾ 0.150
D 0.110 ¾ 0.150
E 0.014 ¾ 0.022
F 0.045 ¾ 0.060
G ¾ 0.100 ¾
H 0.300 ¾ 0.325
I ¾ 0.430 ¾
Dimensions in mm
Symbol
Min. Nom. Max.
A 24.00 ¾ 25.02
B 6.99 ¾ 7.49
C 3.05 ¾ 3.81
D 2.79 ¾ 3.81
E 0.36 ¾ 0.56
F 1.14 ¾ 1.52
G ¾ 2.54 ¾
H 7.62 ¾ 8.26
I ¾ 10.92 ¾
www.DataSheet.net/
Rev. 2.60 43 April 1, 2011

HT82M99E/HT82M99A
18-pin SOP (300mil) Outline Dimensions
1 8 1 0
A B
1 9
C '
G
D H
E F a
· MS-013
Dimensions in inch
Symbol
Min. Nom. Max.
A 0.393 ¾ 0.419
B 0.256 ¾ 0.300
C 0.012 ¾ 0.020
C¢ 0.447 ¾ 0.463
D ¾ ¾ 0.104
E ¾ 0.050 ¾
F 0.004 ¾ 0.012
G 0.016 ¾ 0.050
¾
www.DataSheet.net/
H 0.008 0.013
a 0° ¾ 8°
Dimensions in mm
Symbol
Min. Nom. Max.
A 9.98 ¾ 10.64
B 6.50 ¾ 7.62
C 0.30 ¾ 0.51
C¢ 11.35 ¾ 11.76
D ¾ ¾ 2.64
E ¾ 1.27 ¾
F 0.10 ¾ 0.30
G 0.41 ¾ 1.27
H 0.20 ¾ 0.33
a 0° ¾ 8°
Rev. 2.60 44 April 1, 2011

HT82M99E/HT82M99A
20-pin SOP (300mil) Outline Dimensions
2 0 1 1
A B
1 1 0
C '
G
D H
E F a
· MS-013
Dimensions in inch
Symbol
Min. Nom. Max.
A 0.393 ¾ 0.419
B 0.256 ¾ 0.300
C 0.012 ¾ 0.020
C¢ 0.496 ¾ 0.512
D ¾ ¾ 0.104
E ¾ 0.050 ¾
F 0.004 ¾ 0.012
G 0.016 ¾ 0.050
¾
www.DataSheet.net/
H 0.008 0.013
a 0° ¾ 8°
Dimensions in mm
Symbol
Min. Nom. Max.
A 9.98 ¾ 10.64
B 6.50 ¾ 7.62
C 0.30 ¾ 0.51
C¢ 12.60 ¾ 13.00
D ¾ ¾ 2.64
E ¾ 1.27 ¾
F 0.10 ¾ 0.30
G 0.41 ¾ 1.27
H 0.20 ¾ 0.33
a 0° ¾ 8°
Rev. 2.60 45 April 1, 2011

HT82M99E/HT82M99A
20-pin SSOP (150mil) Outline Dimensions
2 0 1 1
A B
1 1 0
C '
G
D H
E F a
Dimensions in inch
Symbol
Min. Nom. Max.
A 0.228 ¾ 0.244
B 0.150 ¾ 0.158
C 0.008 ¾ 0.012
C¢ 0.335 ¾ 0.347
D 0.049 ¾ 0.065
E ¾ 0.025 ¾
F 0.004 ¾ 0.010
G 0.015 ¾ 0.050
H 0.007 ¾ 0.010
www.DataSheet.net/
a 0° ¾ 8°
Dimensions in mm
Symbol
Min. Nom. Max.
A 5.79 ¾ 6.20
B 3.81 ¾ 4.01
C 0.20 ¾ 0.30
C¢ 8.51 ¾ 8.81
D 1.24 ¾ 1.65
E ¾ 0.64 ¾
F 0.10 ¾ 0.25
G 0.38 ¾ 1.27
H 0.18 ¾ 0.25
a 0° ¾ 8°
Rev. 2.60 46 April 1, 2011

HT82M99E/HT82M99A
Product Tape and Reel Specifications

Reel Dimensions
D
T 2
A B C
T 1
16-pin NSOP (150mil), SSOP 20S (150mil)

Symbol Description Dimensions in mm
A Reel Outer Diameter 330.0±1.0
www.DataSheet.net/
B Reel Inner Diameter 100.0±1.5

+0.5/-0.2
C Spindle Hole Diameter 13.0
D Key Slit Width 2.0±0.5

+0.3/-0.2
T1 Space Between Flange 16.8
T2 Reel Thickness 22.2±0.2
SOP 18W, SOP 20W

A Reel Outer Diameter 330.0±1.0
B Reel Inner Diameter 100.0±1.5
C Spindle Hole Diameter 13.0+0.5/-0.2
D Key Slit Width 2.0±0.5

T1 Space Between Flange 24.8+0.3/-0.2
T2 Reel Thickness 30.2±0.2
Rev. 2.60 47 April 1, 2011

HT82M99E/HT82M99A
Carrier Tape Dimensions

P 0 P 1
D t
F
W
B 0
C
D 1 P
K 0
A 0
R e e l H o le
IC p a c k a g e p in 1 a n d th e r e e l h o le s
a r e lo c a te d o n th e s a m e s id e .
16-pin NSOP (150mil)

W Carrier Tape Width 16.0±0.3
P Cavity Pitch 8.0±0.1
E Perforation Position 1.75±0.1
F Cavity to Perforation (Width Direction) 7.5±0.1
+0.10/-0.00
D Perforation Diameter 1.55
+0.25/-0.00
D1 Cavity Hole Diameter 1.50
P0 Perforation Pitch 4.0±0.1
P1 Cavity to Perforation (Length Direction) 2.0±0.1
A0 Cavity Length www.DataSheet.net/
6.5±0.1
B0 Cavity Width 10.3±0.1
K0 Cavity Depth 2.1±0.1
t Carrier Tape Thickness 0.30±0.05
C Cover Tape Width 13.3±0.1
SOP 18W
W Carrier Tape Width 24.0+0.3/-0.1
D Perforation Diameter 1.5±0.1
D1 Cavity Hole Diameter 1.50+0.25/-0.00
A0 Cavity Length 10.9±0.1
Rev. 2.60 48 April 1, 2011

HT82M99E/HT82M99A
SOP 20W
D Perforation Diameter 1.5+0.1/-0.0
SSOP 20S (150mil)


D Perforation Diameter 1.5+0.1/-0.0
www.DataSheet.net/

Rev. 2.60 49 April 1, 2011

HT82M99E/HT82M99A
Holtek Semiconductor Inc. (Headquarters)

No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999 www.DataSheet.net/
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)

4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shenzhen Sales Office)

5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
Holtek Semiconductor (USA), Inc. (North America Sales Office)

46729 Fremont Blvd., Fremont, CA 94538
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2011 by HOLTEK SEMICONDUCTOR INC.

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-
sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 2.60 50 April 1, 2011

HT82M99A HoltekSemiconductor

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HT82M99E/HT82M99A

USB Mouse Encoder 8-Bit MCU

Rev. 2.60 1 April 1, 2011

Datasheet pdf - http://www.DataSheet4U.co.kr/

Rev. 2.60 2 April 1, 2011

Datasheet pdf - http://www.DataSheet4U.co.kr/

RES I ¾ Schmitt trigger reset input. Active low.

VDD ¾ ¾ Positive power supply

V33O O ¾ 3.3V regulator output

OSC2 O (determined by software instructions) for the internal system clock.

Absolute Maximum Ratings

Rev. 2.60 3 April 1, 2011

Datasheet pdf - http://www.DataSheet4U.co.kr/

D.C. Characteristics Ta=25°C

VIL1 Input Low Voltage for I/O Ports 5V ¾ 0 ¾ 0.8 V

A.C. Characteristics Ta=25°C

Note: Power-on period=tWDT+tSST+tOSC

Rev. 2.60 4 April 1, 2011

Datasheet pdf - http://www.DataSheet4U.co.kr/

Note: *10~*0: Program counter bits S10~S0: Stack register bits

Rev. 2.60 5 April 1, 2011

Datasheet pdf - http://www.DataSheet4U.co.kr/

U S B In te r r u p t S u b r o u tin e tine and the ISR simultaneously should be avoided.

Rev. 2.60 6 April 1, 2011

Datasheet pdf - http://www.DataSheet4U.co.kr/

Stack Register - STACK B a n k 0

Rev. 2.60 7 April 1, 2011

Datasheet pdf - http://www.DataSheet4U.co.kr/

Data Memory - RAM for Bank 1 Indirect Addressing Register

· Branch decision (SZ, SNZ, SIZ, SDZ ....)

Address 00~1FH in RAM Bank0 and Bank1 are located

Rev. 2.60 8 April 1, 2011

Datasheet pdf - http://www.DataSheet4U.co.kr/

Bit No. Label Function

TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is

Status (0AH) Register

rupt the status register, precautions must be taken to

Bit No. Label Function

INTC (0BH) Register

Rev. 2.60 9 April 1, 2011

Datasheet pdf - http://www.DataSheet4U.co.kr/

Rev. 2.60 10 April 1, 2011

Datasheet pdf - http://www.DataSheet4U.co.kr/

examined, the cause for chip reset can be determined.

Rev. 2.60 11 April 1, 2011

Datasheet pdf - http://www.DataSheet4U.co.kr/

TO PDF RESET Conditions

Rev. 2.60 12 April 1, 2011

Datasheet pdf - http://www.DataSheet4U.co.kr/

The registers status are summarized in the following table.

Note: ²*² stands for ²warm reset²

Rev. 2.60 13 April 1, 2011

Datasheet pdf - http://www.DataSheet4U.co.kr/

Bit No. Label Function

0~2 ¾ Unused bit, read as ²0²

TMRC (11H) Register

Rev. 2.60 14 April 1, 2011

Datasheet pdf - http://www.DataSheet4U.co.kr/

to control the input/output configuration. With this con-

Rev. 2.60 15 April 1, 2011

Datasheet pdf - http://www.DataSheet4U.co.kr/

The LVR includes the following specifications: 2 .7 V

Rev. 2.60 16 April 1, 2011

Note: 10~0: Program counter bits S10~S0: Stack register bits