Thesis PDF

Dhaka University of Engineering & Technology, Gazipur
Department of Electrical and Electronic Engineering
Implementation and Performance Analysis of Switch-

Tail Ring Counter using Leakage Reduction Technique
Presented by
Md. Shohanur Rahman Student ID: 162078
Md. Sahadot Hossain Student ID: 162112
Md. Rakib Khan Student ID: 162117
Supervisor
Dr. Md. Anwarul Abedin
Professor
Department of EEE, DUET
1
Department of Electrical and Electronic
Engineering
Outlines
Introduction
Literature Review
Motivation
Objectives
Methodology
Result and Discussion
Thesis Management
Sustainable development
KP, CEP and CEA
Conclusion
2
Engineering
Introduction
❑ Switch tail ring counter is one of the most important counters
❑ This counter is widely used as function generator, frequency divider, pattern

recognizer and phase shifter etc.
❑ In modern days it is essential to design this counters in a very small area.
❑ In nano-technology area is reduced with CMOS technology.
❑ Leakage power consumption is an important issue in CMOS VLSI circuits.
❑ Reduction of channel length, threshold voltage and gate oxide thickness increases
the leakage current in a CMOS circuit
❑ Leakage current is going to be a limiting factor for scaling down of transistors.
❑ It is essential to reduce the leakage power in designing digital circuits like counters,
registers and RAM etc.
4
Engineering
Related works
❑ There are several techniques to reduce leakage power.
❑ Each technique provides an efficient way to reduce leakage power; but

disadvantages of each technique limit the application of each type.
❑ The most commonly used techniques are
▪ Transistor stacking,
▪ Multiple threshold CMOS (MTCMOS)
▪ Variable threshold CMOS (VTMOS),etc.
❑ These techniques reduces the leakage power as well as average power dissipation.
❑ In these techniques the leakage current flow is controlled by modifying the circuit.
6
Engineering
Literature review
1. H. P. Rajani and S. Kulkarni. “Novel sleep transistor techniques for low leakage power peripheral
circuits,” International Journal of VLSI Design & Communication Systems, Vol.3, No.4, pp. 81 – 95,
August 2012.
• Two novel circuit techniques for leakage current reduction in inverters with and
without state retention property are presented in this work.
• The proposed circuit techniques are applied to inverters and the results are compared
with earlier inverter leakage minimization techniques
• The leakage power during sleep mode is found to be better by X 63 times for novel
method.
• The total power dissipation has also reduced by a factor of X 3.5, compared to earlier
sleepy keeper technique.
7
Engineering
Literature review (cont.)

2. A. K. Dadoria and K. Khare, “A novel approach for leakage power reduction techniques in 65nm
technologies." International Journal of VLSI Design & Communication Systems, Vol. 5, No. 3, pp 1-
11, June 2014
• A comprehensive study and analysis of various leakage power minimization
techniques have been presented in this paper.
• A novel Leakage reduction technique is developed in Cadence virtuoso with the
combination of stack with sleepy keeper approach with Low Vth & High Vth.
• Sleep transistor with Low Vth & High Vth 13.90, 26.61% & 33.03%, 75.24% with
respect to sleepy Keeper 93.70, 56.01% of Average Power is saved
8
Engineering
Literature review (cont.)

3. M. K. Soni and R. Mehra, “Optimized design and performance analysis of Johnson counter using
45 nm technology,” International Conference on Power Electronics, Intelligent Control and Energy
Systems (ICPEICES), 2016.
• In this paper a low power, high speed and cost efficient 4 bit Johnson counter is
proposed.
• Deployed flip flop circuit uses 14 transistors to realize the negative edge triggered
master slave D flip flop operation.
• The proposed design is found 48.86 % faster with having 43.22 % less power
dissipation than conventional design.
Fig: Johnson counter with D flip flop
9
Engineering
Purpose and Motivation
➢ CMOS technology reduces area and increases the speed.
➢ But there is a problem of leakage power associated with CMOS technology.
➢ As area reduces consequently leakage current increases.
➢ Therefor it is very essential to reduce the leakage power of switch-tail ring counter.
5
Engineering
Objectives
➢ To study different leakage power reduction techniques.
➢ To design (schematic and full custom layout) and Simulate a 4-bit

switch-tail ring counter using Cadence 90 nm Technology.
➢ To analyze the performance of the switch-tail ring counter

with sleepy transistor technique (STT).
3
Engineering
Methodology
➢ The sleep transistor technique(STT) is employed in the proposed leakage reduction
process to reduce the leakage power of a switch tail-ring counter.
➢ An inverter firstly designed with sleep transistor as shown in figure, then a NAND
gate also designed with sleep transistor.
➢ Using this inverter and NAND gate D flip flop is designed which is used to design
a 4-bit switch-tail ring counter in leakage reduction technique.
Sleepy inverter
10
Engineering
Software Used
MICROWIND 3.1
DSCH 2
CADENCE 90 nm Technology
11
Engineering
Inverter with Sleep Transistor Technique
SCHEMATIC
LAYOUT
Simulation Results
15
Engineering
NAND Gate with Sleep Transistor Technique
SCHEMATIC
LAYOUT
Simulation Results
16
Engineering
D Flip Flop With Sleep Transistor Technique

SCHEMATIC
LAYOUT
Simulation Results
17
Engineering
Proposed Switch-tail Ring Counter
Fig: Schematic of proposed switch-tail ring counter with STT
18
Engineering
Layout Of Proposed Switch-tail Ring Counter
Specification
Frequency Threshold Transistor Speed Rise Fall Vdd Width Length Delay Area
Count Time Time
1800 120nm 112 88.67Ghz 3nSec 3nSec 1.2V 240nm 100nm
19
Engineering
Results And Discussion
Fig: Simulation Result Of Proposed Switch-tail Ring Counter Truth table
20
Engineering
Power Dissipation
70 65.35
60
47.31
50
In microwatt
40
CMOS
30
STT
20
10 4.823 3.56
2.98 2.128
0.8768 0.6352
0
inverter NAND GATE D flip flop proposed counter
22
Engineering
Outlooks
➢ Average power dissipation of conventional CMOS switch-tail ring counter was
65.35 W
➢ Average power dissipation of proposed switch-tail ring counter is found 47.31 W
➢ Power dissipation is reduced by 27.6%.
23
Engineering
Thesis management
RACI (Responsible, Accountable, Consulted, Informed) chart
Supervisor Students
Prof. Dr. Md. Md. Shohanur Md. Sahadot Md. Rakib

Anwarul Rahman Hossain Khan
Tasks 162078 162112 162117
Abedin
Thesis Proposal C, I R, A R, A R, A
Thesis Planning C, I R, A R, A R, A
Literature review C, I R, A R, A R, A
Inverter C, I R, A R, A R, A
Design NAND Gate C, I R, A R, A R, A

(schematic and D Flip Flop C, I R, A R, A R, A
layout)
Counter C, I R, A R, A R, A
Simulation C, I R, A R, A R, A
Report Writing C, I R, A R, A R, A
Presentations C, I R, A R, A R, A
12
Engineering
Gantt Chart
Semesters 4/1 4/2
May June July August Sept. Oct. Nov. Dec. Jan. Feb. March April May
Task Name 2021 2021 2021 2021 2021 2021 2021 2021 2022 2022 2022 2022 2022
Planning
Research
Design
Simulation
Presentation
and Report
Writing
13
Engineering
Individual And Team Work

Md. Shohanur Rahman Md. Sahadot Hossain Md. Rakib Khan
Tasks 162078 162112 162117
Thesis Proposal √
√ √
Thesis Planning √
√ √
Literature Review √ √ √
Design √ √
√ √ √
Simulation
Report Writing √
√
Presentations
√ √
14
Engineering
Sustainable Development
24
PO1 Engineering Knowledge
27
√
PO2 Problem Analysis
√
PO3 Design of Solution
√
PO4 Investigation
CEA
√
PO5 Modern T ools Usage
PO6 Engineer and Society
PO7 Environment and Sustainability
PO8 Ethics
Program Outcomes (POs)
√
PO9 Individual Work / Team Work
PO10 Communication
√
PO11 Project Management & Finance
√
PO12 Life Long Learning
Natural Sciences
K1
Mathematics
K2
PO1-PO2
√
Engineering Fundamentals
K3
√
Specialist Knowledge
K4
√
Engineering Design PO3
K5
Engineering Practice PO5

Knowledge Profile
K6
Comprehension PO6-PO8
K7
√
Research Literature PO4
K8
√
Depth of Knowledge Required (K3-K5, K8)
P1
KP, CEP and CEA
PO1-PO7
Range of Conflicting Requirements

P2
√ Depth of Analysis Required

P3
Familiarity of Issues
P4
Extent of Applicable Codes

P5
Extent of Stakeholder
P6
Complex Engineering Problems
Interdependence
P7
Engineering
Range of Resources
A1
PO10
Level of Interactions
A2
Innovation
A3
Consequences to Society/Environment
A4
Familiarity
A5
Complex Engineering Activities
Engineering
Conclusion
29
Engineering
References
➢ International Technology Roadmap for Semiconductors http://www.itrs2.net/
➢ Kim, Se Hun, and Vincent J. Mooney. "Sleepy keeper: a new approach to low-leakage power
VLSI design." 2006 IFIP International Conference on Very Large Scale Integration. IEEE,
2006.
➢ Ghafari, Payam, Mohab Anis, and Mohamed Elmasry. "Impact of technology scaling on
leakage reduction techniques." 2007 IEEE Northeast Workshop on Circuits and Systems. Ieee,
2007.
➢ Rani, M. Janaki, and S. Malarkann. "Leakage power reduction and analysis of CMOS
sequential circuits." International Journal of VLSI Design & Communication Systems 3.1
(2012): 13.
➢ Ghafari, Payam, Mohab Anis, and Mohamed Elmasry. "Impact of technology scaling on
leakage reduction techniques." 2007 IEEE Northeast Workshop on Circuits and Systems. Ieee,
2007.
➢ Singh, Ajay Kumar. Digital VLSI Design. PHI Learning, 2011.
➢ Allam, M.W. & Anis, Mohab & Elmasry, M.I.. (2000). High-speed dynamic logic styles for
scaled-down CMOS and MTCMOS technologies. 155-160. 10.1109/LPE.2000.876774.
30
Engineering
THANK YOU
31

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Dhaka University of Engineering & Technology, Gazipur

Department of Electrical and Electronic Engineering

Implementation and Performance Analysis of Switch-

Result and Discussion

KP, CEP and CEA

❑ This counter is widely used as function generator, frequency divider, pattern

❑ In modern days it is essential to design this counters in a very small area.

❑ In nano-technology area is reduced with CMOS technology.

❑ Leakage power consumption is an important issue in CMOS VLSI circuits.

❑ Leakage current is going to be a limiting factor for scaling down of transistors.

❑ Each technique provides an efficient way to reduce leakage power; but

❑ The most commonly used techniques are

▪ Multiple threshold CMOS (MTCMOS)

▪ Variable threshold CMOS (VTMOS),etc.

Literature review (cont.)

Literature review (cont.)

Fig: Johnson counter with D flip flop

Purpose and Motivation

➢ CMOS technology reduces area and increases the speed.

➢ But there is a problem of leakage power associated with CMOS technology.

➢ As area reduces consequently leakage current increases.

➢ To study different leakage power reduction techniques.

➢ To design (schematic and full custom layout) and Simulate a 4-bit

➢ To analyze the performance of the switch-tail ring counter

NAND Gate with Sleep Transistor Technique

D Flip Flop With Sleep Transistor Technique

Proposed Switch-tail Ring Counter

Fig: Schematic of proposed switch-tail ring counter with STT

Layout Of Proposed Switch-tail Ring Counter

Results And Discussion

Fig: Simulation Result Of Proposed Switch-tail Ring Counter Truth table

➢ Average power dissipation of proposed switch-tail ring counter is found 47.31 W

➢ Power dissipation is reduced by 27.6%.

Prof. Dr. Md. Md. Shohanur Md. Sahadot Md. Rakib

Design NAND Gate C, I R, A R, A R, A

Individual And Team Work

PO6 Engineer and Society

PO7 Environment and Sustainability

Engineering Practice PO5

Range of Conflicting Requirements

√ Depth of Analysis Required

Extent of Applicable Codes

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