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Programa de Proyecto ALU
Programa de Proyecto ALU
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity ALU is
PORT
(
clk : in std_logic;
a_in : in std_logic_vector(3 downto 0);
b_in : in std_logic_vector(3 downto 0);
selec : in std_logic_vector(3 downto 0);
Cn, m : in std_logic;
compara : out std_logic);
end ALU;
else
J <= "0000";
end if;
end process;
end ALU;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU is
PORT
(
clk : in std_logic;
a_in : in std_logic_vector(3 downto 0);
b_in : in std_logic_vector(3 downto 0);
a_out : out std_logic_vector(3 downto 0);
selec : in std_logic_vector(3 downto 0);
Cn, m : in std_logic;
compara : out std_logic);
end ALU;
begin
proceso1 : process (clk,L,N,O,P,J)
begin
if (clk'event and clk ='1') then
L <= a_in;
O <= L;
N <= b_in;
P <= N;
else
J <= "0000";
end if;
end process;
end if;
end process ;
end ALU;
---- V2 DEL PROGRAMA ----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
USE ieee.std_logic_unsigned.all;
entity ALUV2 is
PORT
(
clk : in std_logic;
a_in : in std_logic_vector(3 downto 0);
b_in : in std_logic_vector(3 downto 0);
selec : in std_logic_vector(3 downto 0);
Cn, m : in std_logic;
Cn_4 : out std_logic;
compara : out std_logic;
a_out : out std_logic_vector(3 downto 0));
end ALUV2;
begin
proceso1 : process (clk,L,N,O,P,J)
begin
if (clk'event and clk ='1') then
L <= a_in;
N <= b_in;
end if;
end process ;
end ALUV2;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
USE ieee.std_logic_unsigned.all;
entity ALUV2 is
PORT
(
clk : in std_logic;
a_in : in std_logic_vector(3 downto 0);
b_in : in std_logic_vector(3 downto 0);
selec : in std_logic_vector(3 downto 0);
Cn, m : in std_logic;
Cn_4 : out std_logic;
compara : out std_logic;
a_out : out std_logic_vector(3 downto 0));
end ALUV2;
begin
proceso1 : process (clk,L,N,O,P,J)
begin
if (clk'event and clk ='1') then
L <= a_in;
N <= b_in;
end if;
end process ;
end ALUV2;