KEC-751B (VLSI Design Lab)

PSIT-Pranveer Singh Institute of Technology
Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India
Lab Manual
VLSI Design Lab

(KEC-751B)
Semester: VIIth , Fourth Year

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING KEC453
Table of Contents
❖ Vision & Mission Statements of the Institute

❖ Vision & Mission Statements of the Department
❖ PEOs, POs, PSOs of the Department
❖ Evaluation Scheme, Guidelines
❖ Syllabus
❖ Course Objective, Course Outcomes, Course Layout
❖ Course Outcome- Program Outcome & Course Outcome-
Program Specific Outcome Co-Relation Matrix
❖ Experiments

Institute Vision Statement

To achieve excellence in professional education and create an ecosystem for the
holistic development of all stakeholders.
Institute Mission Statement

To provide an environment of effective learning and innovation transforming
students into dynamic, responsible and productive professionals in their respective
fields, who are capable of adapting to the changing needs of the industry and society.
Department Vision Statement

To become a known Centre of excellence that produces skilled, innovative, ethical
and industry ready Electronics & Communication engineers.
Department Mission Statements

1. To offer qualitative education of global standards in Electronics & Communication
engineering with professional ethics through innovative methods of teaching &
learning.
2. To foster the culture of innovation and research in the field of Electronics &
Communication Engineering.
3. To provide best experiential teaching-learning environment in order to achieve
excellence in technical education.

Program Educational Objectives (PEOs)
Program Educational Objectives

S.N. Description
Educational foundation that prepares them for careers/ higher studies in the field of E&C
PEO1 Engineering.
In-depth knowledge of the core discipline of E&C so that they will be successful in
PEO2 designing new products and finding technically sound, cost effective and socially
acceptable solutions to engineering problems.
Broad based knowledge and approaches to multi disciplines so as to fit in the global
PEO3 environment of multiple disciplines.
Attitude in lifelong learning, applying and adapting new ideas and technologies as their
PEO4 field evolves.
Leadership qualities, be effective communicators to work efficiently with diverse teams,

PEO5 promote and practice appropriate ethical practices.
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING Page 4

Program Outcomes (POs)

Program Outcomes
S.N. Graduate Attributes Description
Engineering knowledge Apply the knowledge of mathematics, science, Electronics &
PO1 Communication engineering fundamentals, and an engineering
specialization to the solution of complex engineering problems.
Problem analysis Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first
PO2
principles of mathematics, natural sciences, and Electronics &
Communication engineering sciences.
Design/Development of Design solutions for complex Electronics & Communication engineering
solutions problems and design system components or processes that meet the
PO3
specified needs with appropriate consideration for the public health and
safety, and the cultural, societal, and environmental considerations
Conduct investigations Use research-based knowledge and research methods including design of
of complex problems experiments, analysis and interpretation of data, and synthesis of the
PO4
information to provide valid conclusions in the field of Electronics &
Communication Engineering.
Modern tool usage Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modeling to complex
PO5
Electronics & Communication engineering activities with an
understanding of the limitations.
The engineer and Apply reasoning informed by the contextual knowledge to assess societal,
society health, safety, legal and cultural issues and the consequent responsibilities
PO6
relevant to the professional Electronics & Communication engineering
practice.
Environment and Understand the impact of the professional Electronics & Communication
PO7 sustainability engineering solutions in societal and environmental contexts, and
demonstrate the knowledge of, and need for sustainable development.
Ethics Apply ethical principles and commit to professional ethics and
PO8
responsibilities and norms of the engineering practice.
Individual and team Function effectively as an individual, and as a member or leader in diverse
PO9
work teams, and in multidisciplinary settings.
Communication Communicate effectively on complex Electronics & Communication
engineering activities with the engineering community and with society at
PO10 large, such as, being able to comprehend and write effective reports and
design documentation, make effective presentations, and give and receive
clear instructions.
Project management Demonstrate knowledge and understanding of the Electronics &
and finance Communication engineering and management principles and apply these
PO11
to one’s own work, as a member and leader in a team, to manage projects
and in multidisciplinary environments.
Life-long learning Recognize the need for, and have the preparation and ability to engage in
PO12 independent and life-long learning in the broadest context of technological
change.

Program Specific Outcomes (PSOs)
Program Specific Outcomes

S.N. Description
PSO1 The ability to analyze and design systems in the areas related to electronics, communication, signal
processing and embedded systems for solving real-world problems.
PSO2 The ability to identify problems in the areas of electronics and communication to provide efficient
solutions using modern tools/algorithms individually or working in a team.

Evaluation Guideline and Scheme
Evaluation Scheme Marks Sub-Total

Performance & Lab
10
Record
25
Internal Viva 10
Attendance 5
External University Exam 25 25
Grand Total 50

Syllabus
Following table outline the syllabus for VLSI Design Lab (KEC-751B) as prescribed by Dr. A.P.J.
Abdul Kalam Technical University, Uttar Pradesh, Lucknow. The Syllabus can also seen on the
university website https://aktu.ac.in/syllabus%202021-2022.html

LAB PLAN
SUBJECT NAME : VLSI Design Lab
SUNJECT CODE : KEC-751B
Lab Schedule: As per the time table
i) Course Objective: Conduct experiments to design, analyze and characterize digital

combinational circuits, Op-amp and amplifiers with their respective parameters.
ii) Course Outcomes
*Level of Bloom’s Taxonomy Level to be met

L1: Knowledge & L2: Comprehension 1
L3: Application & L4: Analysis 2
L5: synthesis & L6: Evaluation 3
CO1 Designing of logic gates.
CO2 Implementation of combinational and sequential circuits using CMOS logic.
CO3 Analyze amplifier circuits.
CO4 Design sequential circuits such as flip flop.
CO5 Do the layout designing for physical analysis of the MOS transistor and MOS based circuits.
Mapping of Course Outcomes with Program Outcomes and Program Specific Outcomes:
Program Outcomes PSO
COs 1 2 3 4 5 6 7 8 9 10 11 12 1 2
CO-1 3 3 2 1 2 2 2
CO-2 3 3 3 1 2 2 2
CO-3 3 3 2 2 3 1 2 2 2
CO-4 3 3 3 2 3 1 2 2 2
CO-5 3 3 3 3 3 2 3 3 2
AVG 3 3 2.6 2.3 2.8 1.2 2.2 2.2 2

List of Experiments
Experiments Prescribed by AKTU

CO to be
Lab No. Lab of Experiments Outcomes
met
1 a.) Transient Analysis of CMOS Inverter Sinusoidal waveform with different CO1, CO2
using step input. frequencies has been obtained.
b.) DC Analysis (VTC) of CMOS Inverter.
2 Design and implementation of Half adder Truth table of half adder has been CO1, CO2
using CMOS logic. verified.
3 To simulate the schematic of the common Analyze the common drain amplifier CO3
drain amplifier and determine the gain. circuits using MOS and determine the
gain, i/p and o/p resistance.
4 Design and simulate op-amp differential Analyze the op-amp differential amplifier CO3
amplifier function. determine the gain.
5 Design a function generator using OPAMP Square, triangular, sinusoidal waveform CO3
and obtained square, triangular and sinusoidal with different frequencies has been
waves. obtained.
6 Design of 3-8 decoder circuits. Proper NAND gate truth table has been CO2
verified.
7 Write a VHDL code for Full Adder and verify Truth table of full adder has been CO2
the results. verified.
8 Write a VHDL code for Full Subtractor and Truth table of full subtractor has been CO2
verify the results. verified.
9 Write a VHDL code for 8x1 multiplexer and Truth table of 8x1 multiplexer has been CO2
verify the results. verified
10 Write a VHDL code for 3 X 8 Decoder and Truth table of 3 X 8 Decoder has been CO2
verify the results. verified
11 Layout design of CMOS inverter and its Analyze the layout design of CMOS CO4
analysis. inverter.

Experiment No. 1
Objective:
a.) Transient Analysis of CMOS Inverter using step input.
b.) DC Analysis (VTC) of CMOS Inverter.
Tool: PSPICE/MULTISIM
Theory:
CMOS inverters (Complementary NOSFET Inverters) are some of the most widely used and adaptable
MOSFET inverters used in chip design. They operate with very little power loss and at relatively high
speed.
A CMOS inverter contains a PMOS and a NMOS transistor connected at the drain and gate terminals, a
supply voltage VDD at the PMOS source terminal, and a ground connected at the NMOS source terminal,
were VIN is connected to the gate terminals and VOUT is connected to the drain terminals.(See diagram)
The circuit below is the simplest CMOS logic gate.
When a low voltage (0 V) is applied at the input, the top transistor (P-type) is conducting (switch closed)
while the bottom transistor behaves like an open circuit. Therefore, the supply voltage (5 V) appears at
the output. Conversely, when a high voltage (5 V) is applied at the input, the bottom transistor (N-type) is
conducting (switch closed) while the top transistor behaves like an open circuit. Hence, the output voltage
is low (0 V).
The function of this gate can be summarized by the following table:
Input Output
High Low
Low High
The output is the opposite of the input - this gate inverts the input.
Notice that always one of the transistors will be an open circuit and no current flows from the supply
voltage to ground.

Transistor Switch Model
The switch model of the MOSFET transistor is defined as follows:
MOSFET Condition MOSFET State of MOSFET

NMOS Vgs<Vtn OFF
NMOS Vgs>Vtn ON
PMOS Vsg<Vtp OFF
PMOS Vsg>Vtp ON
When VIN is low, the NMOS is "off", while the PMOS stays "on": instantly charging VOUT to logic
high. When Vin is high, the NMOS is "on and the PMOS is "on: draining the voltage at VOUT to logic
low.
Procedure
1. Select the components from the library & connect the circuit as shown in figure.
2. Set simulation parameters for DC & Transient simulation; set parameters as shown wherever
required. (Enter timing values)
3. Start the Simulation.
4. Insert the Cartesian Coordinate & Tabular entities to analyze results.
5. Select the output parameters to display on visual entities.

Circuit Diagram:
Result:
Transient Behavior of CMOS Inverter

Voltage Transfer Characteristics of CMOS Inverter
Result: The transient and DC transfer characteristics are verified by simulation.

Pre-Lab Questions:
1. What is the concept of complement?
2. Which device amongst the NMOS and PMOS must be used as pull up and pull down device?
3. Which device is faster?
4. What will be the effect of mobility mismatch of both device?
Post-Lab Questions:
1. Where the threshold lie?
2. What are the characteristics for ideal inverter?
3. Will CMOS inverter give better response than earlier two?

Experiment No. 2
Objective: Design and implementation of Half adder.

Tool: PSPICE/MULTISIM
Theory:
Half adder is a combinational arithmetic circuit that adds two numbers and produces a sum bit (S) and
carry bit (C) as the output. If A and B are the input bits, then sum bit (S) is the X-OR of A and B and the
carry bit (C) will be the AND of A and B. From this it is clear that a half adder circuit can be easily
constructed using one X-OR gate and one AND gate.
Half adder is the simplest of all adder circuit, but it has a major disadvantage. The half adder can
add only two input bits (A and B) and has nothing to do with the carry if there is any in the input. So, if
the input to a half adder has a carry, then it will be neglected it and adds only the A and B bits. That means
the binary addition process is not complete and that’s why it is called a half adder. The truth table,
schematic representation and XOR//AND realization of a half adder are shown in the figure below.
Circuit diagram

a) For Sum
b) for Carry

Result:
A) For sum
B) Carry
The Truth table to half adder are verified by simulation.

Experiment No.3
Objective: - To simulate the schematic of the common drain amplifier.
Tool: - PSPICE/MULTISIM Software
Theory: -
Common drain amplifier is a source follower or buffer amplifier circuit using a MOSFET. The advantage
of this circuit is that the MOSFET can provide current and power gain; the MOSFET draws no current
from the input. It provides low output impedance to any circuit using the output of the follower, meaning
that the output will not drop under load. Its output impedance is not as low as that of an emitter follower
using a bipolar transistor (as you can verify by connecting a resistor from the output to -15V), but it has
the advantage that the input impedance is infinite. The MOSFET is in saturation, so the current across it
is determined by the gate source voltage. Since a current source keeps the current constant, the gate-source
voltage is also constant.
Procedure
2. Set simulation parameters for DC & Transient simulation; set parameters as shown wherever required.
(Enter timing values)


Conclusion: -The schematic for the common drain amplifier is drawn and verified the following: DC
Analysis, DC Analysis, and Transient Analysis.
Pre-Lab Questions:
1. What is the concept of differential amplifiers?
2. Calculate the voltage gain.
3. Why we apply low voltage at input terminal?
Post-Lab Questions:
1. What will be the output of amplifier?

2. What are the characteristics for common drain amplifier?

Experiment No.4
Objective: - Design and simulate op-amp differential amplifier function.
Tool: - PSPICE/MULTISIM Software
Theory: -
The differential amplifier is probably the most widely used circuit building block in analog
integrated circuits, principally op amps. The differential amplifier can be implemented with BJTs or
MOSFETs. The differential amplifier has a unique feature that many circuits don’t have - two inputs. This
circuit amplifies the difference between its input terminals. Other circuits with one input actually have
another input – the ground potential. But, in cases where a signal source (like a sensor) has both of its
terminals biased at several volts above ground, you need to amplify the difference between the terminals.
What about noise that adds an unwanted voltage equally to both terminals of a sensor? The differential
amp rejects the noise and rescues the signal.
A differential amplifier multiplies the voltage difference between two inputs (Vin+ - Vin- ) by some
constant factor Ad, the differential gain. It may have either one output or a pair of outputs where the signal
of interest is the voltage difference between the two outputs. A differential amplifier also tends to reject
the part of the input signals that are common to both inputs (Vin+ + Vin-)/2 . This is referred to as the
common mode signal.
Fig.1

Voltage Gain
If you keep the following resistor ratios equal, R2/R1 = R4/R3, the voltage gain looks like
What about signals common (or equal) at both inputs Vin+ and Vin-? The equation above tells you the
output Vo should be zero! This Common Mode Rejection (CMR) is useful but not perfect! It depends on
the op amp device itself and matching of the resistor values (more below).
Procedure: -
2. Set simulation parameters for DC & Transient simulation; set parameters as shown wherever required.
(Enter timing values)
Circuit diagram: -
Result: -The output voltage is 12.069 of designed circuit.

Conclusion: -
We have calculated output voltage.
Pre-Lab Questions:
1. What is the function of differential amplifiers?
2. Calculate the voltage gain.

3. Draw the circuit diagram of differential amplifier.

Post-Lab Questions:
1. What is differential gain of given amplifier?
2. What is common mode gain given amplifier?

Experiment No. 5
Objective: Design a function generator using OP-AMP and obtained square, triangular and sinusoidal
waves.
Tool: Multisim 11.0.
Theory:
A Function generator is a circuit which generates Sine wave, square wave and Triangular wave. In our
design the circuit is an OP-AMP based square wave generator for producing the square wave and two OP-
AMP based integrators for the generation of triangular wave and sine wave as shown in the above block
diagram. Figure 3.1 shows the circuit diagram of the function generator. The square wave generator
section and the integrator section of the circuit are explained in detail below:
Figure 3.1: Block Diagram of function generator
Square Wave Generator:
The square wave generator is based on a 741 OP-AMP IC. Resistor R1 and capacitor C1 determines the
frequency of the square wave. Resistor R2 and R3 forms a voltage divider setup which feedbacks a fixed
fraction of the output to the non-inverting input of the IC. Initially, when power is not applied the voltage
across the capacitor C1 is 0. When the power supply is switched on, C1 starts charging through the resistor
R1 and the output of the OP-AMP will be high (VCC). A fraction of this high voltage is fed back to the
non-inverting pin by the resistor network R2, R3. When the voltage across the charging capacitor is
increased to a point where the voltage at the inverting pin is higher than the non-inverting pin, the output
of the OP-AMP swings to negative saturation (VEE). The capacitor quickly discharges through R1 and
starts charging in the negative direction again through R1. Now a fraction of the negative high output
(VCC) is fed back to the non-inverting pin by the feedback network R2, R3. When the voltage across the
capacitor has become so negative that the voltage at the inverting pin is less than the voltage at the non-

inverting pin, the output of the OP-AMP swings back to the positive saturation. Now the capacitor
discharges trough R1 and starts charging in positive direction. This cycle is repeated over time and the
result is a square wave swinging between VCC (+15 V) and VEE (-15 V) at the output of the OP-AMP.
If the values of R2 and R3 are made equal, then the frequency of the square wave can be expressed using
the following equation.
Integrator:
Next part of the function generator is the OP-AMP integrator The OP-AMP IC used in this stage is also
741. Resistor R4 in conjunction with R7 sets the gain of the integrator and resistor R4 in conjunction with
C2 sets the bandwidth. The square wave signal is applied to the inverting input of the OP-AMP through
the input resistor R7. The output of the first integrator will be a triangular wave which is again applied to
another integrator which produces sine wave.
Circuit Diagram: The following figure shows the circuit diagram of the function generator.
Figure 3.2: Circuit diagram of function generator

Result and Analysis: Figure 3.3 shows the output of the function generator on a 4-channel oscilloscope.
We have set the amplitude scale at 10 V/division for channel A (Square wave) while for channel B
(Triangular wave) and C (Sine Wave) it is set to 5V/division.
Figure 3.3: Output of function generator

Conclusion: Waveform has been generated.
Possible sources of error:
1. Observational error
2. Gross error
Precautions:
1. Make sure the connections are correct.
2. Always ground the circuit.

Experiment No. 6
Objective: Design of 3-8 decoder circuits.
Tool: PSPICE/MULTISIM.
Theory: A decoder is a combinational logic circuit that is used to change the code into a set of signals. It
is the reverse process of an encoder. A decoder circuit takes multiple inputs and gives multiple outputs.
A decoder circuit takes binary data of ‘n’ inputs into ‘2^n’ unique output. In addition to input pins, the
decoder has a enable pin. This enables the pin when negated, to make the circuit inactive. in this article,
we discuss 3-to-8-line Decoder and demultiplexer. In, 3-to-8-line decoder, it includes three inputs and
eight outputs. Here the inputs are represented through A0, A1 & A2 whereas the outputs are represented
through D0, D1, D2…D7. The selection of 8 outputs can be done based on the three inputs. So, the truth
table of these 3 lines to 8-line decoder is shown below. From the following truth table, we can observe
that simply one of 8 outputs from DO – D7 can be selected depending on 3 select inputs.
Why do we need a Decoder?
The main function of a decoder is to change a code into a set of signals because it is opposite to an encoder,
but the designing decoders is simple. The main difference between a decoder and a demultiplexer is a
combinational circuit that is used to allow only one input as well as direct it into one of the outputs,
whereas a decoder allows several inputs and generates the decoded output.
3 to 8 Decoder.
• A 3 to 8 decoder has three inputs (A0, A1 & A2) and eight outputs (DO to D7).
• Based on the 3 inputs one of the eight outputs is selected.
• The truth table for 3 to 8 decoder is shown in table (1).
• From the truth table, it is seen that only one of eight outputs (DO to D7) is selected based on three
select inputs.
• From the truth table, the logic expressions for outputs can be written as follows:

Table1: Truth-Table of a 3:8 Decoder
Using the above expressions, the circuit of a 3 to 8 decoder can be implemented using three NOT gates
and eight 3-input AND gates as shown in logic fig (1).The three inputs A, B and C are decoded into eight
outputs, each output representing one of the midterms of the 3-input variables.The three inverters provide
the complement of the inputs and each one of the wight AND gates generates one of the midterms.This
decoder can be used for decoding any 3-bit code to provide eight outputs, corresponding to eight different
combinations of the input code.This is also called a 1 of 8 decoder, since only one of eight output lines is
HIGH for a particular input combination.
Logic diagram of 3:8 Decoder

Circuit diagram using multisim:
Result: All the results verified using multisim.

Experiment No. 7
Objective: Synthesis and Simulation of Full Adder.

Tool: Model-SIM
Theory:
Circuit Diagram:
Truth Table:

VHDL CODE using data flow modeling
library IEEE;
use IEEE.std_logic_1164.all;
entity Full_ Adder is
port (
A: in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
Cout : out STD_LOGIC;
S : out STD_LOGIC );
End Full_Adder ;
Architecture behavioral of Full_Adder is
begin
s <= A xor B xorCin;
Cout<= (A and B) or ((A or B) and Cin );
End behavioural;
Result:

Pre-Lab Questions:
1. Write down the full-form of VHDL.
2. What are the main constituents of VHDL programming?
3. What are the types of modeling and why we need different type of modeling?
4. Draw the circuit diagram of full adder.
5. Write down the full-form of IEEE.
Post-Lab Questions:
1. What is the basic command to call the gates?
2. How many gates are available in the library?

Experiment No. 8
Objective: Synthesis and Simulation of Full Subtractor.
Tool: Model-SIM
Theory:
Circuit Diagram:
Truth Table:

VHDL Code: using behavioral modeling using “select” and “when” command
Library ieee;
use ieee.std_logic_1164.all;
entity flsub_select is
port(
a:inbit_vector(2 downto 0);
s:out bit_vector(1 downto 0));
end flsub_select;
architecture beh of flsub_select is
begin
with a select
s<=("00") when "000",
("11") when "001",
("11") when "010",
("01") when "011",
("10") when "100",
("00") when "101",
("00") when "110",
("11") when "111";
endbeh;
Result:

Pre-Lab Questions:
1. Draw the circuit of full subtractor.
2. Write down the truth table for full subtractor.
3. What is the difference between data flow modeling and behavioral modeling?

Experiment No. 9
Objective: Write a VHDL code for 8x1 multiplexer
Tool: Model-SIM
Circuit Diagram:
Truth Table:
VHDL Code:

library IEEE;
entity mux151 is
port (
I :in STD_LOGIC_VECTOR (7 downto 0); --8 i/p lines
S :in STD_LOGIC_VECTOR (2 downto 0); --3 data select lines
en_l:in STD_LOGIC; --active low enable i/p
y :out STD_LOGIC --output line
);
end mux151;
architecture mux151 of mux151 is
begin
process (I,s,en_l)
begin
ifen_l='0' then
case s is
when "000" => y <= I(0);
when "001" => y <= I(1);
when "010" => y <= I(2);
when "011" => y <= I(3);
when "100" => y <= I(4);
when "101" => y <= I(5);
when "110" => y <= I(6);
when "111" => y <= I(7);
when others=>null;
end case;
else y <= '0'; --y=0 when en_l=1
end if;
end process;
end mux151;
Result:

Pre-Lab Questions:
1. Write down the truth table of multiplexer given.
2. Can you model the given mux by dataflow modeling?
3. Why enable signal is used in such type of combinational logics?

Experiment No. 10
Objective: Synthesis and Simulation of 3 X 8 Decoder.

Tool: Model-SIM
Circuit Diagram:
Here the model is presented for the decoder having 3 enable signal in which at least 2 must be high for
proper operation.
Truth Table:

VHDL CODE:
library IEEE;
entity decoder3X8 is
port (
g1 : in STD_LOGIC;
g2a_1: in STD_LOGIC;
g2b_l : in STD_LOGIC;
a : in STD_LOGIC_VECTOR (2 downto 0);
y_l : out STD_LOGIC_VECTOR (0 to 7)
);
end decoder3X8;
architecture deco38 of decoder3X8 is
begin
process (a,g1,g2a_l,g2b_l)
begin
if (g1 and not g2a_l and not g2b_l)='1'then
if a <= "000"then y_l<= "01111111";
elsif a <= "001"then y_l<= "10111111";
elsif a <= "010"then y_l<= "11011111";
elsif a <= "011"then y_l<= "11101111";
elsif a <= "100"then y_l<= "11110111";
elsif a <= "101"then y_l<= "11111011";
elsif a <= "110"then y_l<= "11111101";
elsif a <= "111"then y_l<= "11111110";
else y_ l<= "11111111";
end if;
elsey_l<= "11111111";
end if;
end process;
end deco38;
Result:

Experiment No. 11
Objective: Layout design of CMOS inverter and its analysis.
Tool: Microwind
Theory:The NOT gate or an inverter is an electronic circuit that produces an inverted version of the input
at its output. It is also known as an inverter. If the input variable is A, the inverted output is known as
NOT A. This is also shown as A', or A with a bar over the top, as shown at the outputs. The diagrams
below show two ways that the NAND logic gate can be configured to produce a NOT gate. It can also be
done using NOR logic gates in the same way.

Design layout of inverter circuit
Output waveform:-


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PSIT-Pranveer Singh Institute of Technology

Kanpur-Delhi National Highway (NH-2), Bhauti, Kanpur-209305 (U.P.), India

VLSI Design Lab

Semester: VIIth , Fourth Year

❖ Vision & Mission Statements of the Institute

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING KEC453

Institute Vision Statement

Institute Mission Statement

Department Vision Statement

Department Mission Statements

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING KEC453

Program Educational Objectives (PEOs)

Program Educational Objectives

Leadership qualities, be effective communicators to work efficiently with diverse teams,

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING Page 4

Program Outcomes (POs)

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING Page 5

Program Specific Outcomes (PSOs)

Program Specific Outcomes

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING Page 6

Evaluation Guideline and Scheme

Evaluation Scheme Marks Sub-Total

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING Page 7

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING Page 8

Lab Schedule: As per the time table

i) Course Objective: Conduct experiments to design, analyze and characterize digital

*Level of Bloom’s Taxonomy Level to be met

Program Outcomes PSO

AVG 3 3 2.6 2.3 2.8 1.2 2.2 2.2 2

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING Page 9

Experiments Prescribed by AKTU

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING Page 10

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING Page 11

Transistor Switch Model

The switch model of the MOSFET transistor is defined as follows:

MOSFET Condition MOSFET State of MOSFET

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING Page 12

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING Page 13

Voltage Transfer Characteristics of CMOS Inverter

Result: The transient and DC transfer characteristics are verified by simulation.

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING Page 14

Objective: Design and implementation of Half adder.

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING Page 15

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING Page 16

The Truth table to half adder are verified by simulation.

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING Page 17

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING Page 18

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1. What will be the output of amplifier?

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Result: -The output voltage is 12.069 of designed circuit.

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3. Draw the circuit diagram of differential amplifier.

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Tool: Multisim 11.0.

Figure 3.1: Block Diagram of function generator

Square Wave Generator:

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Figure 3.2: Circuit diagram of function generator

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Figure 3.3: Output of function generator

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