B.E / B.Tech.

PRACTICAL END SEMESTER EXAMINATIONS, NOVEMBER/DECEMBER 2022

Third Semester
EC3352 - DIGITAL SYSTEMS DESIGN
(Regulations 2021)
Time : 3 Hours Answer any one Question Max. Marks 100
Aim/Principle/Apparatus Tabulation/Circuit/ Calculation Viva-Voce Record Total
required/Procedure Program/Drawing & Results
20 30 30 10 10 100

1. Design and implement a combinational circuit using basic gates for arbitrary function like 3 bit
adder and subtractor. (100)

2. Design and implement a combinational circuit using basic gates for Binary to Gray and BCD to
Excess– 3 code converters. (100)

3. Design and implement a combinational circuit using basic gates for Gray to Binary and
Excess– 3 to BCD code converters. (100)

4. (i) Design and Implement a combinational circuit for data selector using basic gates (50)

(ii) Design and implement a combinational circuit for data distributor using basic gates. (50)

5. Design and implement a combinational circuit for 2 bit magnitude comparator using basic gates

(100)

6. (i) Design and Implement a Full adder using two Half adders (50)

(ii) Desing and construct a Half Subtractor using logic gates (50)

7. Design and implement a combinational circuit using basic gates for Gray to Binary and gray to
Binary code converters. (100)

8. Design and Implement a combinational circuit for 4 bit binary adder / subtractor using MSI
Devices. (50)
ii) Design and construct a 4 to 2 encoder (50)
9. Design and implement a 3 bit synchronous counter to count the sequence in gray code order
(100)

10. i) Design and implement a combinational circuit for 4 x 1 MUX using basic gates.
(50)

ii) Design and implement a combinational circuit for data distributor using basic gates. (50)

11. (i) Design and implement a sequential circuit for 3 bit asynchronous counter (50)

(ii) Design and implement a combinational circuit for 2 bit adder. (50)

12. Design and construct 4 bit synchronous down counter using JK flip flop (50)

13. i) Design and implement a sequential circuit for 3 bit asynchronous counter. (50)

ii) Design and construct a 4 to 2 encoder (50)

14. Design and implement a sequential circuit for PISO shift register. (100)

15. Design and implement a sequential circuit for 3 bit synchronous counter for up/down sequence
(100)

16. i) Design and implement a combinational circuit for 1 x 4 demux using basic gates. (50)

ii) Design and implement a sequential circuit for SIPO and SISO shift register.
(50)

17. Design a BCD adder using IC 7483 and logic gates (100)

18. i) Design and implement a sequential circuit for 4 bit ripple counter.
(50)

ii) Design and construct a 2 to 4 decoder using logic gates . (50)

19. (i) Design and construct a 4 to 2 encoder and 2 to 4 decoder using logic gates (50)

(ii)Design and implement a sequential circuit for SIPO and SISO shift register (50)
20. (i) Design and implement a sequential circuit for BCD asynchronous counter (50)

(ii) Design and construct a combinational circuit that subtract 2 one bit binary numbers and
produce output difference (D) and borrow (B) by using suitable logic gates and verify its truth
table. (50)