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3.
1 8051 : Architecture, Memory organization and Machine cycle
3.1 8051 Microcontroller Architecture, Memory

organization and Machine cycle
Module:3 Microcontroller Architecture: Intel 8051

Course: BECE204L – Microprocessors and Microcontrollers
-Dr Richards Joe Stanislaus
Assistant Professor - SENSE
Email: 51749@vitstudent.ac.in / richards.stanislaus@vit.ac.in
3.1 8051 : Architecture, Memory organization and Machine cycle
Module:3 Microcontroller Architecture:

Intel 8051
• Microcontroller 8051 - Organization and Architecture, RAM-

ROM Organization, Machine Cycle, Instruction set: Addressing
modes, Data Processing - Stack, Arithmetic, Logical; Branching –
Unconditional and Conditional, Assembly programming.
Mohammad Ali Mazidi, Janice G. Mazidi, Rolin D. McKinlay, The 8051 Microcontroller and
Embedded Systems, 2014, 2nd Edition, Pearson, India.
1.1 8085 Introduction

• The Intel MCS-51 (commonly termed 8051) is a Harvard
architecture, complex instruction set
computing (CISC) Architecture, single chip microcontroller (µC)
series developed by Intel in 1980 for use in embedded systems
• Intel's original MCS-51 family was developed using N-type metal-
oxide-semiconductor (NMOS) technology
• But later versions, identified by a letter C in their name (e.g.,
80C51) used complementary metal–oxide–semiconductor
(CMOS) technology and consume less power
1.2a 8051 Features

• 8-bit CPU • 16-bit Program Counter
• 4K bytes on-chip program • 8-bit Processor Status Word
memory (ROM) (PSW) & Stack Pointer
• 128 bytes on-chip data • Two 16-bit timer/counters : T0
memory (RAM) and T1
• 32 I/O pins arranged as four 8- • Two external and three internal
bit ports (P0 - P3) vectored interrupts
• 32 general purpose registers • One full duplex serial I/O (UART)
each of 8-bit
• Special Function Registers
(SFRs) of 128 bytes
1.2b Features: 8051 Family series

1.2b Features: 8051 Family series

• Although the 8051 is the most popular member of the 8051 family, you
will not see “8051″ in the part number.
• This is because the 8051 is available in different memory types, such
as UV-EPROM, flash, and NV-RAM, all of which have different part
numbers.
• The UV-EPROM version of the 8051 is the 8751.
The flash ROM version is marketed by many companies including Atmel
Corp. and Dallas Semiconductor.
• The Atmel Flash 8051 is called AT89C51, while Dallas Semiconductor
calls theirs DS89C4xO (DS89C420/430/440).
• The NV-RAM version of the 8051 made by Dallas Semiconductor is
called DS5000.
• There is also an OTP (one-time programmable) version of the 8051 made
by various manufacturers.
1.2b Features: Major manufacturers

• ATMEL
• ANALOG DEVICES
• ST MICROELECTRONICS
• DALLAS
• MAXIM
• SILICON LABS
• TEXAS INSTRUMENTS
• MICROCHIP
• ZILOG
1.2c Features: ATMEL Series

Packagin
Part Number ROM RAM I/O pins Timer Interrupt Vcc
g
AT89C51 4K 128 32 2 6 5V 40
AT89C52 8K 256 32 3 8 5V 40
AT89C1051 1K 64 15 1 3 3V 20
AT89C2051 2K 128 32 3 8 3V 20
AT89LV51 4K 128 32 2 6 3V 40
AT89LV52 8K 128 32 3 8 3V 40
2.1 8051 Pin diagram and pin details

• Although 8051 family members (e.g., 8751, 89C51, 89C52,
DS89C4xO) come in different packages, such as DIP (dual in-line
package), QFP (quad flat package), and LLC (leadless chip carrier)
• They all have 40 pins that are dedicated to various functions such
as I/O, RD, WR, address, data, and interrupts.
• Some companies provide a 20-pin version of the 8051 with a
reduced number of I/O ports for less demanding applications.
• However, since the vast majority of developers use the 40-pin chip,
we will concentrate on that.
• For the 8052 chip some of the pins have extra functions and they
will be discussed as we study them.
2.1 8051 Pin diagram and

pin details


• In 40 pin package, a total of 32 pins are set aside
for the four ports PO, P1, P2, and P3, where each
port takes 8 pins.
• The rest of the pins are designated as Vcc, GND,
XTAL1, XTAL2, RST, EA, PSEN, and ALE.
• Of these pins, six (Vcc, GND, XTAL1, XTAL2, RST,
and EA) are used by all members of the 8051 and
8031 families.
• In other words, they must be connected in order for
the system to work, regardless of whether the
microcontroller is of the 8051 or 8031 family.
• The other two pins, PSEN and ALE, are used mainly
in 8031-based systems.

• Pin-40 : Vcc is the main power source. Usually its
+5V DC.
• Pins 32-39: Port 0 (P0.0 to P0.7) – In addition to
serving as I/O port, lower order address and data
bus signals are multiplexed with this port (to serve
the purpose of external memory interfacing). This
is a bi directional I/O port (the only one in 8051)
and external pull up resistors are required to function
this port as I/O.
• Pins- 21-28: Port 2 (P 2.0 to P 2.7) – in addition to
serving as I/O port, higher order address bus
signals are multiplexed with this quasi bi
directional port.
• Pin 20:- Vss – it represents ground (0 V) connection.

• Pin-31:- ALE - Address Latch Enable. It is especially used for 8031
IC to connect it to the external memory. It can be used while deciding
whether P0 pins will be used as Address bus or Data bus.
When ALE = 1, then the P0 pins work as Data bus and
when ALE = 0, then the P0 pins act as Address bus.
• Pin-30:- EA - External Access input is used to enable or disallow
external memory interfacing.
If there is no external memory requirement, this pin is pulled high by
connecting it to Vcc.
• Pin- 29:- PSEN or Program Store Enable. This is an active low pin,
i.e., it gets activated after applying a low pulse. It is an output pin and
used along with the EA pin in 8031 based (i.e. ROMLESS) Systems to
allow storage of program code in external ROM.

• Pins 18 and 19:- XTAL1 & XTAL2
Used for interfacing an external crystal to provide system clock.
• Pins 10 – 17:- Port 3 (P 3.0 to P 3.7)
It is also of 8 bits and can be used as Input/Output.
This port provides some extremely important signals.
P3.0 and P3.1 are RxD (Receiver) and TxD (Transmitter)
respectively and are collectively used for Serial Communication.
P3.2 and P3.3 pins are used for external interrupts.
P3.4 and P3.5 are used for timers T0 and T1 respectively.
P3.6 and P3.7 are Write (WR) and Read (RD) pins.

• Pin 9:- RESET pin is used to set the 8051 microcontroller to its
initial values, while the microcontroller is working or at the initial start
of application.
The RESET pin must be set high for 2 machine cycles.
• Pins 1 – 8:- Port 1 (P 1.0 to P 1.7).
It is an 8-bit port (pin 1 through 8) and can be used either as input
or output.
Unlike other ports, this port does not serve any other functions.
Port 1 is an internally pulled up, quasi bi directional I/O port.
3. 8051 Architecture
detailed:
2.2 8051 Architecture: detailed:

2.2 8051 Architecture: detailed:

3. 8051 Architecture (simplified)

3. 8051 Architecture: 1. CPU

• Central Processor Unit (CPU) is the brain of any processing device
of the microcontroller.
• It monitors and controls all operations that are performed on the
Microcontroller units.
• The User has no control over the work of the CPU directly.
• It reads program written in ROM memory and
executes them and does the expected task of that application.
3. 8051 Architecture: 2. Interrupt control

• There are five interrupt sources in 8051 Microcontroller and
interrupt control section control all these interrupts.
• Two external interrupts (INT0 & INT1),
two timer (TF0 & TF1) interrupts and
one serial port (RI / TI) interrupt.
• The Microcontroller 8051 can be configured in such a way that it
temporarily terminates or
pause the main program at the occurrence of interrupt.
When subroutine is completed then the execution of main program

starts as usual.
3. 8051 Architecture: 3. RAM & ROM

• Microcontroller 8051 has
4K of Code Memory or Program memory that is it has 4KB ROM
and
RAM of 128 bytes.
• The memory which is used to store the program of Microcontroller,
is known as code memory or Program memory .
It is known as 'ROM'(Read Only Memory).
• Microcontroller also requires a memory to store data or operands
temporarily.
This memory is known as Data Memory and we use 'RAM'(Random
Access Memory) for this purpose.
3. 8051 Architecture: 4. BUS Control

• Bus control section of 8051 is responsible for controlling the
operation of address and data bus.
• Bus: Basically Bus is a collection of wires which work as a
communication channel or medium for transfer of Data.
• Buses are of two types:
Address Bus: Microcontroller 8051 has a 16 bit address bus. It
used to address memory locations.
Data Bus: Microcontroller 8051 has 8 bits data bus. It is used to
carry data.
3. 8051 Architecture: 5. Crystal Oscillator

• Crystal Oscillator: Since Microcontroller is a digital circuit device,
therefore it requires clock for its operation.
• For this purpose, Microcontroller 8051 has oscillator circuitry section
which works as a clock source for Central Processing Unit.
• As the output pulses of oscillator are stable therefore it enables
synchronized work of all parts of 8051 Microcontroller.
3. 8051 Architecture: 6. IO ports

• I/O Ports: To connect any external devices or peripherals we require
I/O interfacing ports in the microcontroller.
• All 8051 microcontrollers have 4 I/O ports each comprising 8 bits
which can be configured as input (1) or an output (0), depends on its
logic state.
• Accordingly, in total of 32 input/output pins enabling the
microcontroller to be connected to peripheral devices are available
for use.
3. 8051 Architecture: 7. Timers/Counters

• 8051 Microcontroller 8051 two 16-bit timers and counters:
Timer 0 and Timer 1.
• They can be used either as timers to generate a time delay or as
counters to count events happening outside the microcontroller.
• Since the 8051 has an 8-bit architecture,
each 16-bit is accessed as
two separate registers of low byte and high byte.
3. 8051 Architecture: 8. Serial Port

• Serial port: The 8051 contains one Serial port or UART (Universal
Asynchronous Receiver Transmitter)
• The serial port is full-duplex so, it can transmit and receive
simultaneously
• Two port pins are used to provide the serial interface
P3.0 is the receive pin (RXD)
P3.1 is the transmit pin (TXD)
• This serial port that can be programmed to operate in one of four
different modes and at a range of frequencies.
3. 8051 Architecture: RECAP

4. 8051 Memory Organization

• The 8051 has two types of memory and these are
Program Memory and
Data Memory.
• Program Memory (ROM) is used to permanently save the program
being executed,
while Data Memory (RAM) is used for temporarily storing data and
intermediate results created and used during the operation of the
microcontroller.
• Depending on the model in use (8051 microcontroller family in
general) at most a few Kb of ROM and 128 or 256 bytes of RAM is
used.
4. 8051 Memory Organization:

1. Program memory (ROM)
• The 8051 has 4K (4096 locations) of internal or on-chip ROM.
And it can be expanded up to 64K.
• This is used for storing the system program. 212 = 4096, therefore
the internal ROM locations go from 000H to 0FFFH.
• Even though such an amount of memory is sufficient for writing most
of the programs, there are situations when it is necessary to use
additional memory as well.

1. Program memory (ROM)
• Pin EA=0 In this case,
the microcontroller
completely ignores
internal program memory
and executes only the
program stored in
external memory.
• Pin EA=1 In this case,
the microcontroller
executes first the
program from built-in
ROM, then the program
stored in external memory

2. DATA memory (RAM)

2.1 DATA memory (RAM): Register Banks
• Registers are used to store data or
operands during executions.
Register banks form the lowest 32 bytes
on internal RAM memory.
• There are 4 register banks designated bank
#0,#1, #2 and #3. Each bank has 8 registers
which are designated as R0,R1…R7.
• At a time only one register bank is selected
(using RS1 & RS0 bits in PSW register) for
operations and the registers inside the
selected bank are accessed using
mnemonics R0..R1.. etc.
• By default register bank #0 is selected
(after a system reset).

2.1 DATA memory (RAM): Register Banks

2.2 DATA memory (RAM): BIT Addressable area
• The 8051 supports a special feature which
allows access to bit variables.
This is where individual memory bits in
Internal RAM can be set or cleared.
• The Bit Addressable area of the RAM is 16
bytes (128 bits) next to register banks of
Internal RAM located between 20h and
2Fh. In all there are 128 bits numbered
00h to 7Fh.
• Being bit variables any one variable can
have a value 0 or 1. A bit variable can be set
with a command such as SETB and cleared
with a command such as CLR.

2.2 DATA memory (RAM):
BIT Addressable area
• Example instructions are
SETB 25h ; sets the bit 25h (becomes 1)
CLR 25h ; clears bit 25h (becomes 0)
• Bit addressable area is mainly used to store bit
variables from application program,
like status of an output device like LED or
Motor (ON/OFF) etc.
• We need only a bit to store this status and
using a complete byte addressable area for
storing this is really bad programming practice,
since it results in wastage of memory.

2.3 DATA memory (RAM): SCRATCH PAD RAM
• These 80 bytes of Internal RAM memory scratch pad RAM are available
for general-purpose data storage.
Scratch pad RAM is from 30H to 7FH and this includes stack too.
• However, these 80 bytes are used by the system stack and in practice
little space is left for general storage.
• Access to this area of memory is fast compared to access to the main
memory and special instructions with single byte operands are used.

2.3 DATA memory (RAM): SCRATCH PAD RAM
• The scratch pad RAM can be accessed using direct or indirect
addressing modes.
• Examples of direct addressing:
MOV A, 6Ah ; reads contents of address 6Ah to accumulator
• Examples for indirect addressing (use registers R0 or R1):
MOV R1, #6Ah ; move immediate 6Ah to R1
MOV A, @R1 ; move indirect: R1 contains address of Internal
RAM which contains data that is moved to A.

2.4 DATA memory (RAM): SFRs
SFR: Special Function Register
• SFRs are accessed just like normal Internal RAM locations.
• The SFRs are located within the Internal Memory
in the address range 80h to FFh.
• Each SFR has a very specific function.
Note: some of the SFR registers are bit addressable.
• Each SFR has an address (within the range 80h to FFh) and
a name which reflects the purpose of the SFR.

SFR: Special Function Register
• Although 128 byes of the SFR address space is defined only 21
SFR registers are defined in the standard 8051.
• Rest of locations are intentionally left unoccupied in order to
enable the manufacturers to further develop microcontrollers
keeping them compatible with the previous versions.
• Main function of SFR:
is to control timers, counters, serial I/O, port I/O, and
peripherals that are present in 8051 microcontroller.
4. 8051 Memory
Organization:
2.4 DATA memory
(RAM): SFRs
SFR Register layout


• The 21 Special Function Registers of 8051 Microcontroller are
categorized in to six groups.
1. Math or CPU Registers: A and B
2. Status Register: PSW (Program Status Word)
3. I/O Port Latches: P0 (Port 0), P1 (Port 1), P2 (Port 2) and P3 (Port
3)
4. Pointer Registers: DPTR (Data Pointer – DPL,DPH), SP (Stack
Pointer)
5. Peripheral Control Registers: PCON, SCON, TCON, TMOD, IE
and IP
6. Peripheral Data Registers: TL0, TH0, TL1, TH1 and SBUF

2.4.1a DATA memory (RAM): SFRs: A register
• A register:
• The most important of all special function register is
Accumulator which is also known as ACC or A.
• The Accumulator holds the result of most of arithmetic and logic
operations.
It is also used to store 8 bit data and to hold one of operand of
ALU units during arithmetical and logical operations.
• More than half instructions used by the 8051 microcontroller use
somehow the accumulator.
• ACC is usually accessed by direct addressing and its physical
address is E0H.

2.4.1a DATA memory (RAM): SFRs: A register
• A register:
• Accumulator is an 8-bit register and it is both byte and bit
addressable.
• To access the individual bits of accumulator, use the format ACC.X
in the instruction where “X” denotes bit to be accessed.

2.4.1b DATA memory (RAM): SFRs: B register
• B register:
• It is special 8-bit math register and it is bit and byte accessible.
• It is used in conjunction with A register as an input operand for ALU
to perform multiplication and division operation.
• It can also be used as general purpose register to store 8-bit data.

3)
Pointer)
and IP

2.4.2 DATA memory (RAM): SFRs: PSW register
• PSW register:
• It is 8 bit register and it is bit and byte accessible.
• It contains several status bits that reflects the status of the
operation that is being carried out in the processor.
• It has 4 conditional flags or math flags (CY, AC, OV, P) which sets
or resets according to condition of result.
• It has 3 control flags (F0, RS0, RS1) by setting or resetting bit
required operation or function can be achieved.

• PSW register:
• It is 8 bit register and it is bit and byte accessible.
• It contains several status bits that reflects the status of the operation that is being carried out in the
processor.
• It has 4 conditional flags or math flags (CY, AC, OV, P) which sets or resets according to condition of
result.
• It has 3 control flags (F0, RS0, RS1) by setting or resetting bit required operation or function can be
achieved.

• PSW register:
• CY, the carry flag: This flag is set whenever there is a carry out
from the D7 bit. This flag bit is affected after an 8-bit addition or
subtraction.
• AC, the auxiliary carry flag: If there is a carry from D3 to D4
during an ADD or SUB operation, this bit is set; otherwise, it is
cleared. This flag is used by instructions that perform BCD (binary
coded decimal) arithmetic.
• F0, the Flag 0 : The PSW.5 and PSW.1 bits are general-purpose
status flag bits and can be used by the programmer for any
purpose. In other words, they are user definable.

• PSW register:
• RS0, RS1 - Register bank select bits. These two bits are used to
select one of four register banks of RAM. By setting and clearing
these bits, registers R0-R7 are stored in one of four banks of RAM.

• PSW register:
• OV, overflow flag: This flag is set whenever the result of a signed
number operation is too large, causing the high-order bit to
overflow into sign bit.
In general, the carry flag is used to detect errors in unsigned
arithmetic operations.
The overflow flag is only used to detect errors in signed
arithmetic operations
• P, the parity flag: The parity flag reflects the number of 1 s in the A
(accumulator) register only. If the A register contains an odd
number of 1’s, then P = 1. Therefore, P = 0 if A has an even
number of 1s.

3. I/O Port Latches: P0 (Port 0), P1 (Port 1), P2 (Port 2) and P3
(Port 3)
Pointer)
and IP

2.4.3 DATA memory (RAM): SFRs: Input/Output
registers P0, P1, P2, P3
• Input/Output registers P0, P1, P2, P3:
There are 4 ports with in total of 32 input/output pins are
available for connection to peripheral environment.
• So 4 Input/Output ports named P0, P1, P2 and P3 has got four
corresponding port registers P0, P1, P2 and P3. All 4 port registers
are bit as well as byte addressable.
• Data must be written into port registers first to send it out to any
other external device through ports.
• Similarly any data received through ports must be read from port
registers for performing any operation.



• If a bit is cleared (0), the appropriate pin will be configured as an
output, while if it is set (1), the appropriate pin will be configured as
an input.
• Upon reset and power-on, all port bits are set (1), which means
that all appropriate pins will be configured as inputs.

3)
Pointer)
and IP

2.4.4a DATA memory (RAM): SFRs:
DPTR Register
• DPTR Register:
• It is a 16 bit register used to hold address of external or internal
RAM where data is stored or result is to be stored.
• It can be divided into two 8-bit registers, DPH-data pointer higher
order and DPL-data pointer lower order.
• Each register can be used as general purpose register to store 8
bit data and can also be used to store memory location.
• It functions as Base register in base relative addressing mode
and indirect jump.

2.4.4a DATA memory (RAM): SFRs:
DPTR Register
• DPTR Register:

2.4.4b DATA memory (RAM): SFRs:
Stack Pointer
• SP Register:
• It is 8-bit register. It is byte addressable.
• It is used to hold the internal RAM memory location addresses
which are used as stack memory.
• When the data is to be placed on stack by push instruction, the
content of stack pointer is incremented by 1.
• When data is retrieved from stack, content of stack of stack pointer
is decremented by 1.

Stack Pointer
• SP Register:
• A value stored in the Stack Pointer points to the first free stack
address and permits stack availability.
• Upon any reset and power-on, the value 7 is stored in the Stack
Pointer, which means that the space of RAM reserved for the stack
starts at this location.

ProgramCounter (NOT A PART OF SFR)
• Program Counter:
• It is used to hold 16 bit address of internal RAM, external RAM
or external ROM locations.
• The Program Counter (PC) is a 2-byte address which tells the 8051
where the next instruction to be executed from memory.
• When the 8051 is initialized PC always starts at 0000h and is
incremented each time an instruction is executed.

3)
Pointer)
and IP
• The peripheral based registers will be discussed later

5. Machine Cycle of 8051
• The CPU takes a certain number of clock cycles to execute an

instruction.
• In the 8051 family, these clock cycles are referred to as machine
cycles.
• A single machine cycle: the minimum amount of time in which a
single 8051 instruction can be executed, although many instructions
take multiple cycles.

• Pulse - One complete oscillation of the clock source;
State - Two pulses;
Machine Cycle - six states.

• If an instruction takes one machine cycle to execute, it will take
12 pulses of the crystal to execute.
• 8051 is designed to operate between 4MHz to 40MHz and
generally operates with a crystal frequency 11.0592 MHz.
• Since we know the crystal is pulsing 11,059,200 times per second
and that one machine cycle is 12 pulses.
we can calculate how many instruction cycles the 8051 can
execute per second: 11,059,000 / 12 = 921,583 single cycles
and
One such instruction takes: 1/ 921,583=1.085µs time to execute


• This means that the 8051 can execute 921,583 single-cycle
instructions per second.
• For example, if you are using exclusively 2-cycle instructions you
would find that the 8051 would execute 460,791 instructions per
second.
• The 8051 also has two really slow instructions that require a full 4
cycles to execute-those instructions you’d find performance to be
about 230,395 instructions per second.

• Lets find the time period of the machine cycle in each case for the
following crystal frequency of different 8051 based systems: 11.0592
MHz, 16 MHz, 20 MHz.
Answer: 11.0592 MHz: 11.0592/12 = 921.6 KHz
Machine cycle = 1/921.6 KHz = 1.085us [us=microsecond]
16 MHz: 16MHz/12 = 1.333 MHz
Machine cycle = 1/1.333 MHz = 0.75us [us=microsecond]
20MHz: 20MHz/12 = 1.66 MHz
Machine Cycle = 1/1.66 MHz = 0.60us [us=microsecond]
Lets find how long it takes to execute each of the following

instructions, for a crystal frequency of 11.0592 MHz. The
machine cycle of a system of 1.085us
INSTRUCTION MACHINE CYCLE TIME TO EXECUTE

MOV R2,#55H 1
DEC R2 1
DJNZ R2,target 2
LJMP 2
SJMP 2
NOP 1
MUL AB 4
Lets find how long it takes to execute each of the following

instructions, for a crystal frequency of 11.0592 MHz. The
machine cycle of a system of 1.085us.
INSTRUCTION MACHINE CYCLE TIME TO EXECUTE

MOV R2,#55H 1 1x1.085 us = 1.085 us
DEC R2 1 1x1.085 us = 1.085 us
DJNZ R2,target 2 2x1.085 us = 2.17 us
LJMP 2 2x1.085 us = 2.17 us
SJMP 2 2x1.085 us = 2.17 us
NOP 1 1x1.085 us = 1.085 us
MUL AB 4 4x1.085 us = 4.34 us
3.2 8051 Addressing modes


Intel 8051
• Microcontroller 8051 - Organization and Architecture, RAM-ROM

Organization, Machine Cycle, Addressing modes, Instruction set:
Data Processing - Stack, Arithmetic, Logical; Branching –
1. Addressing Modes
• Addressing mode is a way to address an operand. Operand means
the data we are operating upon.
• There are five major addressing modes available in the 8051:
– Immediate
– Direct
– Register
- Register indirect
– Indexed
1. Addressing Modes
a. IMMEDIATE ADDRESSING MODE
• This addressing mode is named as “immediate” because it transfers
an 8-bit data immediately to the accumulator (destination operand).
• In general we can write MOV A, #data.
MOV A, #6AH
• The ‘#’ symbol before 6AH indicates that operand is a data (8 bit).
If ‘#’ is not present then the hexadecimal number would be taken as

address.
1. Addressing Modes
1. Addressing Modes
• The opcode for MOV A, # data is 74H.
The opcode is saved in program memory at 0202 address.
The data 6AH is saved in program memory 0203.
• When the opcode 74H is read, the next step taken would be to
transfer whatever data at the next program memory address
(here at 0203) to accumulator A (E0H is the address of
accumulator).
• This instruction is of two bytes. So after the execution of this
instruction, program counter will add 2 and move to 0204 of program
memory.
• This instruction is executed in one cycle
1. Addressing Modes
1. Addressing Modes
1. Addressing Modes
1. Addressing Modes
b. DIRECT ADDRESSING MODE
• Here the address of the data (source data ) is given as operand.
Lets take an example.
MOV A, 04H
• Here 04H is the address of register 4 of register bank#0.
When this instruction is executed, what ever data is stored in
register 04H is moved to accumulator.
• In the figure register 04H holds the data 1FH. So the data 1FH is
moved to accumulator.
1. Addressing Modes
1. Addressing Modes
• The opcode for instruction MOV A, address is E5H.
When the instruction at 0202 is executed (E5H),
accumulator is made active and ready to receive data.
• Then program control goes to next address that is 0203 and
look up the address of the location (04H) where the source data
(to be transferred to accumulator) is located.
• At 04H the control finds the data 1F and transfers it to accumulator
and hence the execution is completed.
1. Addressing Modes
1. Addressing Modes
Moving data to SFRs

1. Addressing Modes
c. REGISTER ADDRESSING MODE
• In this addressing mode we use the register name directly (as
source operand). At a time registers can take value from
R0,R1…to R7.An example is shown below.
MOV A, R4
• In register direct addressing mode, data is transferred
from the register (based on which register bank is selected)
to accumulator.
• PSW.3 and PSW.4bits are known as register bank select bits as
they are used to select register banks.
1. Addressing Modes
1. Addressing Modes
1. Addressing Modes
1. Addressing Modes
d. REGISTER INDIRECT ADDRESSING MODE
• In this addressing mode, address of the data (source data to
transfer) is given in the register operand.
MOV A, @R0
• Here the value inside R0 is considered as an address,
which holds the data to be transferred to accumulator
• If R0 holds the value 20H, and
we have a data 2F H stored at the address 20H,
then the value 2FH will get transferred to accumulator after
executing this instruction.
1. Addressing Modes
1. Addressing Modes
• The opcode for MOV A, @R0 is E6H.
Assuming that register bank #0 is selected.
So the R0 of register bank #0 holds the data 20H.
• Program control moves to 20H
where it locates the data 2FH and
it transfers 2FH to accumulator.
• This is a single byte instruction and
the program counter increments 1 and moves to 0203 of
program memory.
• Only R0 and R1 (of All register banks) are allowed to form a
register indirect addressing instruction..
1. Addressing Modes
e. INDEXED ADDRESSING MODE
MOVC A, @A+DPTR and MOVC A, @A+PC
• where DPTR is data pointer and PC is program counter
(both are 16 bit registers).
• The source operand is @A+DPTR and
we will get the location of the source data (to transfer).
• It is nothing but adding contents of DPTR with present content of

accumulator. This addition will result a new data which is taken as
the address of source data (to transfer).
• The data at this address is then transferred to accumulator.
1. Addressing Modes
1. Addressing Modes
• The opcode for the instruction is 93H.
DPTR holds the value 01FE, where 01 is located in DPH (higher 8 bits)
and FE is located in DPL (lower 8 bits).
• Accumulator now has the value 02H.
A 16 bit addition is performed and
now 01FE H+02 H results in 0200 H.
• What ever data is in address 0200 H will get transferred to
accumulator.
• The previous value inside accumulator (02H) will get replaced with new
data from 0200H. New data in the accumulator is shown in dotted line
box.
1. Addressing Modes
• This is a 1 byte instruction with 2 cycles needed for execution.
So, the execution time required for this instruction is high compared to
other addressing modes (which all were 1 cycle).
• The other example MOVC A, @A+PC works the same way as above
example.
The only difference is, instead of adding DPTR with accumulator, here
data inside program counter (PC) is added with accumulator to
obtain the target address
3.3 8051 Instruction set


Intel 8051
• Microcontroller 8051 - Organization and Architecture, RAM-ROM

Organization, Machine Cycle, Instruction set: Addressing modes,
Data Processing - Stack, Arithmetic, Logical; Branching –
1. Instruction Set
• The process of writing program for the microcontroller mainly
consists of
giving instructions (commands) in the specific order in which
they should be executed
in order to carry out a specific task.
• As electronics cannot “understand” what for example an instruction
“if the push button is pressed- turn the light on” means,
then a certain number of simpler and precisely defined orders
that decoder can recognize must be used.
• All commands are known as INSTRUCTION SET.
1. Instruction Set
• All microcontrollers compatible with the 8051 have in total of 255
instructions, i.e. 255 different words available for program writing.
• Many instructions are considered to be “different”, even though they
perform the same operation,
so there are only 111 truly different commands.
• For example:
ADD A,R0,
ADD A,R1, ... ADD A,R7
are instructions that perform the same operation (addition of the
accumulator and register). Taking into account that all instructions
perform only 53 operations (addition, subtraction, copy etc.)
1. Instruction Set
8051 instructions have 8-bit opcode
• There are 256 possible instructions of which 255 are implemented
• Every 8-bit opcode from 00 to FF is used except for A5.
• Some instructions have one or two additional bytes for data or
address
• There are 139 1-byte instructions,
92 2-byte instructions, and
24 3-byte instruction
1. Instruction Set
Depending on operation they perform, all instructions are divided in 5
groups:
• Arithmetic Instructions
• Logic Instructions
• Program Branching Instructions
• Boolean or Bit-oriented Instructions
• Data Transfer Instructions
1. Instruction Set
DATA PROGRAM
ARITHMETIC LOGICAL BOOLEAN
TRANSFER BRANCHING
JMP / SJMP / AJMP/
MOV ADD / ADDC ANL CLR
LJMP
MOVC SUBB ORL SETB LCALL / ACALL
MOVX INC XRL MOV RET / RETI
PUSH DEC ANL JZ / JNZ
POP MUL ORL JC /JNC
XCH DIV CPL JB / JNB
XCHD DA A JBC
CLR CJNE
CPL DJNZ
RL / RLC NOP
RR / RRC
SWAP
1. Instruction Set
a. ARITHMETIC INSTRUCTIONS
• Using Arithmetic Instructions, you can perform addition,
subtraction, multiplication and division.
• The arithmetic instructions also include increment by one,
decrement by one and Decimal Adjust Accumulator.
• The arithmetic instructions has no knowledge about the data
format i.e. signed, unsigned, ASCII, BCD, etc.
• The operations performed by the arithmetic instructions affect flags
like carry, overflow, zero, etc. in the PSW
1. Instruction Set
• The Mnemonics associated with the Arithmetic Instructions of the
8051 Microcontroller Instruction Set are:
ADD CLR
ADDC CPL
SUBB RL
MUL RLC
DIV RR
INC RRC
DEC SWAP
DA A
1. Instruction Set
• ADD:
8 bit addition with accumulator (A) and second operand
Result is always in accumulator.
CY flag is set/reset appropriately
• ADDC
8 bit addition between accumulator, a second operand and the
previous value of CY flag
Useful for 16 bit addition in two steps.
Decrement R2 and
Jump when Not zero to
AGAIN
Analysis of 6.2
1. Instruction Set
• SUBB:
Subtract with borrow
Subtract an operand and previous value of borrow (carry) flag from
accumulator (A)
A = A - <operand> - CY
Result is always saved in accumulator.
1. Instruction Set
• MUL AB / DIV AB
Multiply A by B and place the result in A:B
Divide A by B and place the result in A:B
• Multiplication – single byte product
• Result in A and B with

Lower byte in A and
Higher byte in B
1. Instruction Set
• MUL AB / DIV AB
Multiply A by B and place the result in A:B
Divide A by B and place the result in A:B
• Divide – single byte division (If B is zero, A/B will set Over flow flag)
• Result in A and B with
Quotient byte in A and
Remainder byte in B
1. Instruction Set
1. Instruction Set
1. Instruction Set
1. Instruction Set
1. Instruction Set
1. Instruction Set
1. Instruction Set
b. LOGICAL INSTRUCTIONS
• The Logical Instructions perform logical operations like
AND, OR, XOR.
• Logical Instruction are performed on Bytes of data on a bit-by-bit
basis.
• ANL
• ORL
• XRL
1. Instruction Set
b. LOGICAL INSTRUCTIONS
1. Instruction Set
c. BOOLEAN or BIT ORIENTED INSTRUCTIONS
• The Boolean or Bit Manipulation Instructions will deal with bit
variables.
• We know that there is a special bit-addressable area in the RAM
and some of the Special Function Registers (SFRs) are also bit
addressable.
• CLR
• SETB
• CPL
• MOV
• ANL
• ORL
1. Instruction Set
1. Instruction Set
1. Instruction Set
Single bit operations with carry

Swap A
1. Instruction Set
d. PROGRAM BRANCHING INSTRUCTIONS
• These instructions control the flow of program logic.
SJMP JZ / JNZ
LJMP JC / JNC
AJMP JB / JNB
JMP JBC
LCALL CJNE
ACALL DJNZ
RET NOP
RETI
1. Instruction Set
• These instructions control the flow of program logic.
1. Instruction Set
1. Instruction Set
1. Instruction Set
1. Instruction Set
1. Instruction Set
1. Instruction Set
1. Instruction Set
1. Instruction Set
Delay using nested loop

1. Instruction Set
e. DATA TRANSFER INSTRUCTIONS
• The Data Transfer Instructions are associated with transfer with data
between registers or external program memory or external data
memory. MOV
MOVC
MOVX
PUSH
POP
XCH
XCHD
1. Instruction Set
1. Instruction Set
1. Instruction Set
2. Arithmetic Flags
• Flag: It is a 1-bit register that indicates the status of the result
from an operation
• Flags are either at a flag-state of value 0 or 1
• Arithmetic flags indicate the status of the results from mathematical
operations (+, -, *, /)
• There are 4 arithmetic flags in the 8051:
Carry (C), Auxiliary Carry (AC),
Overflow (OV), Parity (P)
• All the above flags are stored in the Program Status Word(PSW)
2. Arithmetic Flags
• Instructions that affect Flag
2. Arithmetic Flags
• Instructions that affect Flag
Show how the flag register is affected by the following

instructions.
MOV A, #0F5h ; A = F5h
ADD A, #0Bh ; A = F5 + 0B = 00
Solution F5h 1111 0101

+ 0Bh + 0000 1011
100h 0000 0000
After the addition, register A (destination) contains 00 and the flags
are:
CY = 1 since there is a carry out from D7
P = 0 because the number of 1s is zero
AC = 1 since there is a carry from D3 to D4
Overflow problem
Rotate left
Rotate Right
Rotate Right through carry

Rotate left through carry

Machine cycle examples: Loop

4.1 8051 IO Ports
4.1 8051 IO Ports
Module:4 Microcontroller 8051 Peripherals

4.1 8051 IO Ports
• I/O Ports, Timers-Counters, Serial Communication and Interrupts.
4.1 8051 IO Ports
1. 8051: IO Ports
4.1 8051 IO Ports
1. 8051: IO Ports
• All 8051 microcontrollers have 4 I/O ports each comprising 8 bits
which can be configured as inputs or outputs.
• In total of 32 input/output pins enabling the microcontroller to be
connected to peripheral devices are available for use.
• Pin configuration, i.e. whether it is to be configured as an input (1) or an
output (0), depends on its logic state.
• When the first 0 is written to a port, it becomes output port.
For reconfiguring it as input, 1 must be sent to the port (programmed)
• All the ports upon RESET are configured as input, ready to be used as
input ports
4.1 8051 IO Ports
1.1 PORT - 0
• Port 0 occupies a total of 8 pins (pins 32-39). It can be used for input
or output.
• To use the pins of port 0 as both input and output ports, each pin
must be connected externally to a 10K ohm pull-up resistor. This is
due to the fact that P0 is an open drain, unlike P1, P2, and P3.
• Dual role of port-0: Port 0 is also designated as AD0-AD7, allowing it
to be used for both address and data. When ALE = 0, it provides
data D0-D7, but when ALE =1 it has address and data with the help
of a 74LS373 latch.
4.1 8051 IO Ports
1.1 PORT - 0
4.1 8051 IO Ports
1.2 PORT - 1
• Port 1 occupies a total of 8 pins (pins 1 through 8). ‰
Port 1 can be
used as input or output
• In contrast to port 0, this port does not need any pull-up resistors
since it already has pull-up resistors internally
• Upon reset, port 1 is configured as an input port
• To make port 1 an input port, it must be programmed as such by
writing 1 to all its bits
4.1 8051 IO Ports
1.3 PORT - 2
• Port 2 occupies a total of 8 pins (pins 21- 28). It can be used as
input or output. Upon reset, Port 2 is configured as an input port.
• Just like P1, P2 does not need any pull-up resistors since it
already has pull-up resistors internally.
• In many 8051-based system, P2 is used as simple I/O
but in 8031-based systems, port 2 must be used along with P0 to
provide the 16-bit address for the external memory
• Port 2 is also designated as A8 –A15, indicating its dual function
and Port 0 provides the lower 8 bits via A0 –A7.
4.1 8051 IO Ports
1.4 PORT - 3
• Port 3 occupies a total of 8 pins, pins 10 through 17.
• It can be used as input or output.
Upon reset, Port 3 is configured as an input port.
• P3 does not need any pull-up resistors, the same as P1 and P2
did not.
• Port 3 has the additional function of providing some extremely
important signals such as interrupts.
4.1 8051 IO Ports
1.4 PORT - 3
4.1 8051 IO Ports
2.1 Pins current limitation

• When configured as outputs (logic zero (0)), single port pins can
receive a current of 10mA.
• If all 8 bits of a port are active, a total current must be limited to
15mA (port P0: 26mA).
• If all ports (32 bits) are active, total maximum current must be
limited to 71mA.
• When these pins are configured as inputs (logic 1), built-in pull-up
resistors provide very weak current, but strong enough to activate
up to 4 TTL inputs of LS series.
4.1 8051 IO Ports
2.2 LOGICAL STRUCTURE OF 8051 I/O

PORTS
PORT – 1, 2 & 3 PORT - 0

4.1 8051 IO Ports
2.3a Writing 0 to port (output port )

• Internal CPU
bus provides
logic as 0 here.
• When clock
is initiated,
Q becomes 0,
𝑄 becomes 1,
Transistor
is in saturation,
Switch ON state,
Port pin is grounded to 0.
4.1 8051 IO Ports
2.3b Writing 1 to port (output port)

• Internal CPU
bus provides
logic as 1 here.
• When clock
is initiated,
Q becomes 1,
𝑄 becomes 0,
Transistor
is in cutoff,
Switch OFF state,
Port pin is open,
No o/p current,
Vcc(1) at Port pin.
4.1 8051 IO Ports
2.3c Reading the latch (status of output previously

provided by CPU – in both cases of 0 or 1)
• In both cases, when output is provided after clock, Q holds the
status (as 0 or 1)
When read latch is enabled, this Q output of flipflop is read back
through same internal bus by the processor. This is called reading
the latch.(status of output provided previously by the processor)
4.1 8051 IO Ports
2.4a Reading the port (when 1 is external input)

• To read input
Internal CPU bus
sends 1 to D input,
which makes 𝑄=0.
This cuts off Transistor.
• Now: when
external input = 1,
Read PIN is enabled,
(in buffer)
to read external input at
internal CPU bus
4.1 8051 IO Ports
2.4b Reading the port (when 0 is external input)

• To read input
Internal CPU bus
sends 1 to D input,
which makes 𝑄=0.
This cuts off Transistor.
• Now: when
external input = 0,
Read PIN is enabled,
(in buffer)
to read external input at
internal CPU bus.
4.1 8051 IO Ports
2.5 Difference between reading a port (port pin is

input) vs reading a latch (output sent by CPU)
• There is a difference between reading a latch and reading the output
port pin.
• Reading a latch: Usually the instructions that read the latch,
read a value,
possibly change it,
and then rewrite it to the latch.
These are called "read-modify-write" instructions. Examples are-
• ORL P2, A; P2 <-- P2 or A (OR logic)
• In this the latch value of P2 is read, is modified and is then written
back to P2 latch.
4.1 8051 IO Ports

• "read-modify-write" instructions. Examples are-
4.1 8051 IO Ports

• Reading a port: (with port Pin as input) is performed as
- Read a port pin (input value,
- Perform other activities with it without affecting the port pin value.
4.1 8051 IO Ports
3. 8051 I/O PORTS & SFR

BIT AND BYTE ADDRESS LOCATIONS
Ports are SFRs
• Port 0: Address 80H
• Port 2: Address 0A0H
• Port 3: Address 0B0H
4.1 8051 IO Ports

Ports are SFRs
• Port 2: Address 0A0H
• Port 3: Address 0B0H
4.1 8051 IO Ports

PORT 0 BITS P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0
BIT ADDRESS 87H 86H 85H 84H 83H 82H 81H 80H
BIT ADDRESS 97H 96H 95H 94H 93H 92H 91H 90H
BIT ADDRESS A7H A6H A5H A4H A3H A2H A1H A0H
BIT ADDRESS B7H B6H B5H B4H B3H B2H B1H B0H
4.1 8051 IO Ports
IO Program: 01
4.1 8051 IO Ports
IO Program: 02
• The following code will continuously send out to port 1 the
alternating value 55H and AAH.
4.1 8051 IO Ports
IO Program: 02 : Another way

4.1 8051 IO Ports
IO Program: 03
4.1 8051 IO Ports
IO Program: 04
4.1 8051 IO Ports
IO Program: 05
4.1 8051 IO Ports
IO Program: 06
4.1 8051 IO Ports
IO Program: 07
4.2 8051 Timers and Counters

1. Timers
• The 8051 has two timers/counters, they can be used either as
• Timers to generate a time delay
• To generate a waveform with specific frequency
• To generate baud rate signal for serial communication
• Event counters to count events happening outside the
microcontroller
• Both Timer 0 and Timer 1 are 16 bits wide
• Since 8051 has an 8-bit architecture,
each 16-bits timer is accessed as two separate registers of low
byte and high byte
1. Timers
• Register related to work with 8051 timers are:
• TH & TL Timer/counter register– To hold the value for generating
time delay
• TMOD Register - to define mode of timer operation
• TCON Register – To control the timer operation
1.1 Timer Registers

• Accessed as low byte and high byte
• The low byte register is called TL0/TL1 and
• The high byte register is called TH0/TH1
1.2 Steps to generate time delay

Steps to calculate values to be loaded into the TL and TH registers for
finding the TH, TL registers’ values
1. Divide the desired time delay by 1.085us (if operating frequency
is 11.0592 MHz) n=T/1.085us where T is required time delay.
2. Perform 65536 – n, where n is the decimal value we got in Step1
3. Convert the result of Step 2 to hex value, where yyxx is the initial
hex value to be loaded into the timer’s register
4. Set TL = xx and TH = yy To generate a time delay
1.2 Steps to generate time delay

• Example: 500us time delay
Step1: 500us/1.085us = 461pulses
Step2: P=65536-461=65075
Step3: 65075 converted by hexa decimal =FE33
Step4: TH1=0xFE; TL1=0x33;
1.3 TMOD Register (to select mode)

• Timer registers are Accessed like any other register
MOV TL0,#4FH
MOV R5,TH0
• To set the various timer operation modes : Both timers 0 and 1 use
the same register, called TMOD (timer mode),
• TMOD is a 8-bit register
• The lower 4 bits are for Timer 0
• The upper 4 bits are for Timer 1



• Timers of 8051 do starting and stopping by either software or
hardware control
• In using software to start and stop the timer where GATE=0
• The start and stop of the timer are controlled by way of software by
the TR(timer start) bits TR0 and TR1
• The SETB instruction starts it, and it is stopped by the CLR
instruction
• The hardware way of starting and stopping the timer by an external
source is achieved by making GATE=1 in the TMOD register

1.4 TCON Register (to control)

1.5 To generate Time delay

1. Load the TMOD value register indicating which timer (timer 0 or
timer 1) is to be used and which timer mode (0 or 1) is selected
2. Load registers TL and TH with initial count value
3. Start the timer (TR1 or TR0 as 1)
4. Keep monitoring the timer flag (TF) with the JNB TFx
(if Timer flag is zero or not), target instruction to see if it is raised and
Get out of the loop when TF becomes high
5. Stop the timer (TR1 or TR0 as 0)
6. Clear the TF flag for the next round
7. Go back to Step 2 to load TH and TL again
2.1 Timer 0 – Mode 0 (13- bit timer)

• This is one of the rarities being kept only for the purpose of
compatibility with the previous versions of microcontrollers.
• This mode configures timer 0 as a 13-bit timer which consists of
all 8-bits of TH0 and the lower 5-bits of TL0.
• How does it operate?
Each coming pulse causes the lower register bits to change their
states. After receiving 32 pulses,
this register is loaded and automatically cleared,
while the higher byte (TH0) is incremented by 1.
• This process is repeated until registers count up 8192 pulses. After
that, both registers are cleared and counting starts from 0
2.1 Timer 0 – Mode 0 (13- bit timer)

2.2 Timer 0 Mode 1 (16-bit timer)

• It is a 16-bit timer; therefore it allows values from 0000 to FFFFH to
be loaded into the timer’s registers TL and TH.
• After TH and TL are loaded with a 16-bit initial value,
the timer must be started.
• After the timer is started. It starts count up until it reaches its limit of
FFFFH.
• When it rolls over from FFFF to 0000H, it sets high a flag bit
called TF (timer flag). This is one of the most commonly used
modes.


Steps to program Timer 0 Mode 1 (16-bit timer)
1. Choose mode 1 timer 0
MOV TMOD,#01H
2. Set the original value to TH0 and TL0.
MOV TH0,#FFH
MOV TL0,#FCH
3. You had better to clear the flag to monitor: TF0=0.
CLR TF0
4. Start the timer.
SETB TR0
5. The 8051 starts to count up by incrementing the TH0-TL0.
TH0-TL0= FFFCH,FFFDH,FFFEH,FFFFH,0000H

Steps to program Timer 0 Mode 1 (16-bit timer)
6. When TH0-TL0 rolls over from FFFFH to 0000, the 8051 set
TF0=1.
TH0-TL0= FFFEH, FFFFH, 0000H (Now TF0=1)
7. Keep monitoring the timer flag (TF) to see if it is raised.
AGAIN: JNB TF0, AGAIN (TF not raised, then AGAIN)
8. Clear TR0 to stop the process.
CLR TR0
9. Clear the TF flag for the next round.

Example program:
Assuming XTAL = 11.0592 MHz, write a program to generate a
square wave of 50 Hz frequency on pin P2.3.
Solution:
The period of the square wave = 1 / 50 Hz = 20 ms.
The high or low portion of the square wave = 10 ms.
10 ms / 1.085 us = 9216
65536 – 9216 = 56320 in decimal = DC00H in hex.
TL1 = 00H and TH1 = DCH.

MOV TMOD,#10H ;timer 1, mode 1
AGAIN: MOV TL1,#00 ;Timer value = DC00H
MOV TH1,#0DCH
SETB TR1 ;start
BACK: JNB TF1,BACK
CLR TR1 ;stop
CLR TF1 ;clear timer flag 1
CPL P2.3
SJMP AGAIN ;reload timer since mode 1 is not auto-reload
2.3 Timer 0 Mode 2 (8 bit timer-8 bit reload value)

(Auto-reload Timer)
• When a timer is in mode 2, THx holds the "reload value" and TLx is
the timer itself.
• Thus, TLx starts counting up. When TLx reaches 255 and is
subsequently incremented, instead of resetting to 0 (as in the case
of modes 0 and 1), it will be reset to the value stored in THx.
• For example, let’s say TH0 holds the value FDh and TL0 holds the
value FEh. After every two cycles TL0 reset to the value stored
in TH0.
• The auto-reload mode is very commonly used for establishing a
baud rate.

(Auto-reload Timer)
• In fact, only the TL0 register operates as a timer, while another
TH0 register stores the value from which the counting starts.
• When the TL0 register is loaded, instead of being cleared the
contents of TH0 will be reloaded to it.
• Suppose it is necessary to constantly count up 55 pulses generated
by the clock.
• In order to register each 55th pulse, the best solution is to write the
number 200 to the TH0 register and configure the timer to operate in
mode 2.

(Auto-reload Timer)

(Auto-reload Timer)

(Auto-reload Timer)
2.4 Timer 0 Mode 3 (split timer)

• Mode 3 configures timer 0 so that registers TL0 and TH0 operate as
separate 8-bit timers.
• In other words, the 16-bit timer consisting of two registers TH0 and
TL0 is split into two independent 8-bit timers.
• This mode is provided for applications requiring an additional 8-bit
timer or counter.
• The TL0 timer turns into timer 0, while the
TH0 timer turns into timer 1.

• In addition, all the control bits of 16-bit Timer 1 (consisting of the
TH1 and TL1 register), now control the 8-bit Timer 1.
• Even though the 16-bit Timer 1 can still be configured to operate in
any of modes, it is no longer possible to disable it as there is no
control bit to do it.
• Thus, its operation is restricted when timer 0 is in mode 3.

• While Timer 0 is in split mode,
you may not start or stop the real timer 1 since the bits that do that
are now linked to TH0.
• The only real use by using split timer mode is
if you need to have two separate timers and, additionally, a baud
rate generator.
• In such case you can use the real Timer 1 as a baud rate
generator and use TH0/TL0 as two separate 8-bit timers.

Problems: EXAMPLE-1:
In the following program, we create a square wave of 50% duty
cycle (with equal portions high and low) on the P1.5bit. Timer 0
is used to generate the time delay. Analyze the program.
Assume XTAL = 11.0592 MHz
MOV TMOD,#01 ;Timer 0, mode 1(16-bit mode)

HERE: MOV TL0,#0F2H ;TL0=F2H, the low byte (13+1)
MOV TH0,#0FFH ;TH0=FFH, the high byte
CPL P1.5 ;toggle P1.5
ACALL DELAY
SJMP HERE
DELAY: SETB TR0 ;start the timer 0
AGAIN: JNB TF0,AGAIN ;monitor timer flag 0
CLR TR0 ;stop timer 0
CLR TF0 ;clear timer 0 flag
RET
• The number of counts for the roll over is FFFFH – FFF2H = 0DH (13
decimal).
• However, we add one to 13 because of the extra clock needed when it
rolls over from FFFF to 0 and raise the TF flag. This gives 14 ×1.085us =
15.19us for half the pulse.
• For the entire period it is T = 2 ×15.19us = 30.38us as the time delay
generated by the timer.
Assume that XTAL = 11.0592 MHz. What value do we need to load the
timer’s register if we want to have a time delay of 5 ms
(milliseconds)? Show the program for timer 0 to create a pulse width
of 5 ms on P2.7
Since XTAL = 11.0592 MHz, the counter counts up every 1.085 us.
This means that out of many 1.085 us intervals we must make a 5 ms
pulse.
To get that, we divide one by the other. We need 5 ms / 1.085 us = 4608
clocks.
To Achieve that we need to load into TL and TH the value 65536 – 4608 =
EE00H.
Therefore, we have TH = EE and TL = 00.
Problems: EXAMPLE-2: Program

CLR P2.7 ;Clear P2.3
MOV TMOD,#01 ;Timer 0, 16-bitmode
HERE: MOV TL0,#0 ;TL0=0, the low byte
MOV TH0,#0EEH ;TH0=EE, the high byte
CPL P2.7 ;SET high P2.7
SETB TR0 ;Start timer 0
AGAIN: JNB TF0,AGAIN ;Monitor timer flag 0
CLR TR0 ;Stop the timer 0
CLR TF0 ;Clear timer 0 flag
SJMP HERE
Problems: EXAMPLE-3
Calculate TL and TH to get the largest time delay possible. Find
the delay in ms. In your calculation, exclude the overhead due to
the instructions in the loop
Solution:
• To get the largest delay we make TL and TH both 0. This will count
up from 0000 to FFFFH and then roll over to zero
• Making TH and TL both zero means that the timer will count from
0000 to FFFF, and then roll over to raise the TF flag.
• As a result, it goes through a total Of 65536 states. Therefore, we
have delay =(65536 - 0) ×1.085 us = 71.1065ms.
Problems: EXAMPLE-4
Assume that XTAL = 11.0592 MHz, write a program to generate a
square wave of 2 kHz frequency on pin P1.7
Solution:
T = 1 / f = 1 / 2 kHz = 500 us the period of square wave.
(b) 1 / 2 of it for the high and low portion of the pulse is 250 us.
(c) 250 us / 1.085 us = 230 and 65536 – 230 = 65306 which in hex
FF1AH.
(d) TL = 1A and TH = FF, all in hex. The program is as follows:

MOV TMOD,#10H ;Timer 1, 16-bitmode
AGAIN: MOV TL1,#1AH ;TL1=1A, low byte of timer
MOV TH1,#0FFH ;TH1=FF, the high byte
CPL P1.7 ;Complement P1.5
SETB TR1 ;Start timer 1
BACK: JNB TF1,BACK ;until timer rolls over
CLR TR1 ;Stop the timer 1
CLR TF1 ;Clear timer 1 flag
SJMP AGAIN ;Reload timer
Problems: EXAMPLE-5
Generate a square wave with TON of 3ms and T0FF of 10ms on all
pins of port 0. Assume an XTAL of 22MHz.
For 22MHz , one timer cycle time is

22MHz / 12 = 1.83MHz
T = 1/1.83M = 0.546 us
For OFF time calculation:
10ms/0.546 us = 18315 cycles
65536-18315 =47221 = B875H
For ON time calculation:
3ms/0.546us = 5494 cycles
65536 – 5494 = 60042=EA8AH
Problems: EXAMPLE-5
MOV TMOD, #01H
BACK: MOV TL0, #75H ORG 300H
MOV TH0, #0B8H DELAY: SETB TR0
MOV P0, #00H AGAIN: JNB TF0, AGAIN
ACALL DELAY CLR TR0
MOV TL0, #8AH CLR TF0
MOV TH0, #0EAH RET
MOV P0, #0FFH END
ACALL DELAY
SJMP BACK

Assuming XTAL = 22MHz write a program to generate a square
pulse of 2 seconds period on pin P2.4. Use timer 1 mode.
Note: 12*(1/22MHz)=0.546us
Solution:
Since square wave TON and TOFF values are equal. So 2s/2 = 1
second.
For TON (1 SECOND) time calculation:
WHEN TL and TH takes value of 0 and the maximum delay is 65536
x 0.546us = 35782 us = 35.78ms.
If maximum delay is repeated for 28 times we get 28x35.78 ms =
1001 ms = 1 second

MOV TMOD, #10H
REPEAT: MOV R0, #28
CPL P2.4
BACK: MOV TL1, #00H
MOV TH1, #00H
SETB TR1
AGAIN: JNB TF1, AGAIN
CLR TR1
CLR TF1
DJNZ R0, BACK
SJMP REPEAT
Problems: EXAMPLE-7
Assuming XTAL = 22MHz write a program to generate a square
pulse of frequency 100kHz on port pin P1.2.
For 100kHz square wave,

(a). T=1/f = 0.01ms = 10uS
(b). TON = TOFF = 10uS/2 = 5uS
(c). 5us/ 0.546 us = 9 cycles
(d). 256 – 9 = 247 = 47H
3.1 Counters
• Timers can also be used as counters counting events happening
outside the 8051
• When it is used as a counter, it is a pulse outside of the 8051 that
increments the TH, TL registers
• TMOD and TH, TL registers are the same as for the timer
discussed previously
• Programming the timer in the last section also applies to
programming it as a counter
• Except the source of the frequency
3.1 Counters
• The C/T bit in the TMOD registers decides the source of the clock
for the timer
• When C/T = 1, the timer is used as a counter and gets its pulses
from outside the 8051
• The counter counts up as pulses are fed from pins 14 and 15, these
pins are called T0 (timer 0 input) and T1 (timer 1 input)
3.1 Counters
• Mode 1:
• Mode 2: Auto Reload

EXAPMLE-1: Assuming that clock pulses are fed into pin T1, write a
program for counter 1 in mode 2 to count the pulses and display the
state of the TL1 count on P2, which connects to 8 LEDs.
EXAPMLE-2: Write an 8051 assembly language program to implement
a counter for counting pulses of an input signals. Assume the crystal
frequency as 22 MHz. Configure TIMER 1 to generate a clock pulse for
every one seconds at P3.5 and TIMER 0 as a counter which receives input
pulses at P3.4 from P3.5 Display final count values in port P1 (TL0) &
P2(TH0).
EXAPMLE-2:4.2Write an 8051 assembly language program to implement a counter
8051 Timers and Counters
for counting pulses of an input signals. Assume the crystal frequency as 22 MHz.
Configure TIMER 1 to generate a clock pulse for every one seconds at P3.5 and TIMER
0 as a counter which receives input pulses at P3.4 from P3.5 Display final count values
in port P1 (TL0) & P2(TH0).
ORG 000H BACK: JNB TF1, BACK
REPEAT: MOV TMOD, #15H CLR TF1
SETB P3.4 CLR TR1
MOV TL0, #00 DJNZ R0, AGAIN
MOV TH0, #00
SETB TR0 MOV A, TL0
MOV P1,A
MOV R0,#28 MOV A, TH0
AGAIN: MOV TL1,#00 MOV P2,A
MOV TH1, #00 SJMP REPEAT
SETB TR1 END
4.3 8051 Serial Communication and Interrupts

1. Serial Communication
• Computers transfer data in two ways:
• Serial
To transfer to a device located many
meters away, the serial method is used,
The data is sent one bit at a time
• Parallel
Often 8 or more lines (wire conductors)
are used to transfer data to a device
that is only a few feet away
Types of Data transmission
Serial data communication uses two methods
• Synchronous method transfers a block of data at a time
• Asynchronous method transfers a single byte at a time
• There are special IC chips made by many manufacturers for serial

communications
• UART (universal asynchronous Receiver-transmitter)
• USART (universal synchronous-asynchronous Receiver-transmitter)
• Protocol is a set of rules agreed by both the sender and receiver on
• How the data is packed
• How many bits constitute a character
• When the data begins and end
• Asynchronous serial data communication is widely used for
character-oriented transmissions - Each character is placed in b/w
start and stop bits, is called framing
• Block-oriented data transfers use the synchronous method
• The start bit is always one bit,
but the stop bit can be one or two bits
• The start bit is always a 0 (low) &
the stop bit(s) is 1 (high)
• Due to the extended ASCII characters, 8-bit ASCII data is common
• In older systems, ASCII characters were 7-bit
• In modern PCs the use of one stop bit is standard
• The rate of data transfer in serial data communication is stated in
bps(bits per second)
• Another widely used terminology for bps is baud rate
• It is modem terminology and
is defined as the number of signal changes per second
• The baud rate and bps are the same, and we use the terms inter
changeably
• The data transfer rate of given computer system depends on
communication ports incorporated into that system
• An interfacing standard RS232 was set by the Electronics Industries
Association (EIA) in 1960
• In RS232, a 1 is represented by -3 ~ -25 V, while a 0 bit is +3 ~ +25
V, making -3 to +3 undefined
• The standard was set long before the advent of the TTL logic family,
its input and output voltage levels are not TTL compatible
• Current terminology classifies data communication equipment as
• DTE (data terminal equipment) refers to terminal and computers

that send and receive data
• DCE (data communication equipment) refers to communication

equipment, such as modems
1.0 Serial Communication: RS232 DB-25



 DTR (data terminal ready)
 When terminal is turned on, it sends out signal DTR to indicate
that it is ready for communication
 DSR (data set ready)
 When DCE is turned on and has gone through the self-test, it
assert DSR to indicate that it is ready to communicate
 RTS (request to send)
 When the DTE device has byte to transmit, it assert RTS to
signal the modem that it has a byte of data to transmit

 CTS (clear to send)
 When the modem has room for storing the data it is to receive, it
sends out signal CTS to DTE to indicate that it can receive the
data now
 DCD (data carrier detect)
 The modem asserts signal DCD to inform the DTE that a valid
carrier has been detected and that contact between it and the
other modem is established
 RI (ring indicator)
 An output from the modem and an input to a PC indicates that the
telephone is ringing
 It goes on and off in synchronous with the ringing sound
• The simplest connection between a PC and microcontroller requires
a minimum of three pins, TxD, RxD, and ground
 In data transmission, serial communication is the process of
sending data one bit at a time, sequentially, over
a communication channel or computer bus.
 To reduce the number of pins in a package, many ICs use a
serial bus to transfer data when speed is not important.
 Some examples of such low-cost serial buses
include SPI, I²C, DC-BUS, UNI/O, and 1-Wire.
 8051 has two pins that are used specifically for transferring and
receiving data serially
 These two pins are called TxD and RxD and are part of the
port 3 group (P3.0 and P3.1)
 These pins are TTL compatible; therefore, they require a line
driver to make them RS232 compatible
 We need a line driver (voltage converter) to convert the R232’s
signals to TTL voltage levels that will be acceptable to 8051’s
TxD and RxD pins
• A line driver such as the MAX232 chip is required to convert RS232
voltage levels to TTL levels, and vice versa
1.2 Baud rate (bps)

• To allow data transfer between the PC and an 8051 system without
any error, we must make sure that the baud rate of 8051 system
matches the baud rate of the PC’s COM port
1.2 Baud rate (bps)

1.2 Baud rate (bps)

1.3 SBUF register

 SBUF is an 8-bit register used solely for serial communication
 For a byte data to be transferred via the TxD line, it must be
placed in the SBUF register
 SBUF holds the byte of data when it is received by 8051 RxD
line
1.4 SCON register

 SCON is an 8-bit the special function register (bit-addressable).
 This register contain not only the mode selection bits but also the
9th data bit for transmit and receive (TB8 and RB8) and the serial
port interrupt bits (TI and RI).
1.4 SCON register

1.4 SCON register

• REN (receive enable):
When it is high, it allows 8051 to receive data on RxD pin, If
low, the receiver is disable
• TI (transmit interrupt):
When 8051 finishes the transfer of 8-bit character It raises TI
flag to indicate that it is ready to transfer another byte
• RI (receive interrupt):
When 8051 receives data serially via RxD, it raises the RI flag
bit to indicate that a byte has been received and should be picked up
before it is lost
2.0 Serial Communiction: Mode 0

 In mode 0, serial data are
transmitted and received
through the RXD pin, while
the TXD pin output clocks. The
baud rate is fixed at 1/12 the
oscillator frequency. On
transmit, the least significant bit
(LSB bit) is sent/received first.
2.1 Serial Communication: Mode 1

 In mode 1, 10 bits are
transmitted through the TXD
pin or received through the
RXD pin in the following
manner: a START bit (always
0), 8 data bits (LSB first) and
a STOP bit (always 1). The
START bit is only used to
initiate data receive, while the
STOP bit is automatically
written to the RB8 bit of the
SCON register.
2.2 Serial Communication: Modes 2, 3

 In mode 2, 11 bits are transmitted through the TXD pin or received
through the RXD pin: a START bit (always 0), 8 data bits (LSB
first), a programmable 9th data bit and a STOP bit (1).
 On transmit, the 9th data bit is actually the TB8 bit of the SCON
register. This bit usually has a function of parity bit. On receive,
the 9th data bit goes into the RB8 bit of the same register
(SCON).
 The baud rate is either 1/32 or 1/64 of the oscillator frequency.
 Mode 3 is the same as Mode 2 in all respects except the baud

rate. The baud rate in Mode 3 is variable.
3.1 Step to program 8051 to transfer

character bytes serially
1. TMOD register is loaded with the value 20H, indicating the use of
timer 1 in mode 2 (8-bit auto-reload) to set baud rate
2. The TH1 is loaded with one of the values to set baud rate for serial
data transfer
3. The SCON register is loaded with the value 50H, indicating serial
mode 1, where an 8-bit data is framed with start and stop bits
4. TR1 is set to 1 to start timer 1
5. The character byte to be transferred serially is written into SBUF
register
6. The TI flag bit is monitored with the use of instruction JNB TI, xx
to see if the character has been transferred completely
7. TI is cleared by CLR TI instruction
8. To transfer the next byte, go to step 5
Assume a switch is connected to pin P1.7. Write a program to monitor its

status and send two messages to serial port continuously as follows:
SW=0 send “NO”
SW=1 send “YES”
Assume XTAL = 11.0592 MHz, 9600 baud, 8-bit data, and 1 stop bit.
4. Interrupt
 A single microcontroller can serve several devices by two ways: (i)
Interrupt (ii). Polling
 Interrupts: Whenever any device needs its service, the device
notifies the microcontroller by sending it an interrupt signal
 Upon receiving an interrupt signal, the microcontroller
interrupts whatever it is doing and serves the device
 The program which is associated with the interrupt is called
the interrupt service routine (ISR) or interrupt handler
4. Interrupt
 Polling can monitor the status of several devices and serve each
of them as certain conditions are met
 The polling method is not efficient, since it wastes much of
the microcontroller’s time by polling devices that do not need
service
 ex. JNB TF,target
• The advantage of interrupts is that the microcontroller can serve
many devices (not all at the same time)
4.1 Interrupt Vector Table,

Interrupt service routine
 For every interrupt, there must be an interrupt service routine
(ISR), or interrupt handler
 When an interrupt is invoked, the micro-controller runs the
interrupt service routine
 For every interrupt, there is a fixed location in memory that
holds the address of its ISR
 The group of memory locations set aside to hold the
addresses of ISRs is called interrupt vector table

 Upon activation of an interrupt, the microcontroller goes through
the following steps:
1. It finishes the instruction it is executing and saves the address of
the next instruction (PC) on the stack
2. It also saves the current status of all the interrupts internally
(i.e: not on the stack)
3. It jumps to a fixed location in memory, called the interrupt
vector table, that holds the address of the ISR

4. The microcontroller gets the address of the ISR from the
interrupt vector table and jumps to it
 It starts to execute the interrupt service subroutine until it reaches
the last instruction of the subroutine which is RETI (return from
interrupt)
5. Upon executing the RETI instruction, the microcontroller returns to
the place where it was interrupted
 First, it gets the program counter (PC) address from the stack by
popping the top two bytes of the stack into the PC
 Then it starts to execute from that address

• Default interrupt
memory locations
in
Interrupt vector table
• To skip IVT,
LJMP MAIN
may be used as in
example
4.2 Interrupt Enable Register

The interrupts must be enabled by software in order for the
microcontroller to respond to them,
 There is a register called IE (interrupt enable) that is responsible
for enabling (unmasking) and disabling (masking) the interrupts
To enable an interrupt, we take the following steps:
1. Bit D7 of the IE register (EA) must be set to high to allow the rest of
register to take effect
2. If EA = 1, interrupts are enabled and will be responded to if their
corresponding bits in IE are high
3. If EA = 0, no interrupt will be responded to, even if the
associated bit in the IE register is high
4.2 Interrupt enable register

 The timer flag (TF) is raised when the timer rolls over
 In polling TF, we have to wait until the TF is raised
The problem with this method is that the microcontroller is
tied down while waiting for TF to be raised, it can’t do
anything else
 Using interrupts solves this problem and, avoids tying
down the controller
If the timer interrupt in the IE register
4.3 External Harware Interrupts

 The 8051 has two external hardware interrupts
 Pin 12 (P3.2) and pin 13 (P3.3) of the 8051, designated as
INT0 and INT1, are used as external hardware interrupts
 The interrupt vector table locations 0003H and 0013H are
set aside for INT0 and INT1
 There are two activation levels for the external hardware
interrupts
 Level trigged
 Edge trigged
4.3 External
Harware
Interrupts
4.3 External Harware Interrupts:

a. Level triggered mode:
 In the level-triggered mode, INT0 and INT1 pins are normally high
 If a low-level signal is applied to them, it triggers the interrupt
 Then the microcontroller stops whatever it is doing and jumps to
the interrupt vector table to service that interrupt
 The low-level signal at the INT pin must be removed before
the execution of the last instruction of the ISR, RETI; otherwise,
another interrupt will be generated
 This is called a level-triggered or level-activated interrupt and is the
default mode upon reset of the 8051

a. Level triggered mode:
• Assume that the INT1 pin is connected to a switch that is normally
high. Whenever it goes low, it should turn on an LED. The LED is
connected to P1.3 and is normally off. As long as the switch is
pressed low, the LED should stay on. Simultaneously perform a
toggle operation in P1.5 with the delay of 500ms.
ORG 0000H ORG 30H

LJMP main main: MOV IE,#10000100B
//ISR for INT1 Here: SETB P1.5
ORG 0013H ACALL DELAY
SETB P1.3 CLR P1.5
MOV R3,#255 ACALL DELAY
Back: DJNZ R3, Back SJMP Here
CLR P1.3
RETI // Delay program in next slide
//Delay of 500ms
DELAY: MOV R2,#04H ;LOAD R2 WITH 07 HEX
HERE3: MOV R1,#0FFH ;LOAD R1 WITH 0FF HEX
HERE2: MOV R0,#0FFH ;LOAD R2 WITH 0FF HEX
HERE1: DJNZ R0,HERE1 ;DECREMENT R0
DJNZ R1,HERE2 ;DECREMENT R1
DJNZ R2,HERE3 ;DECREMENT R2
RET ;RETURN
END
Explanation for the Interrupt program:

 Pins P3.2 and P3.3 are used for normal I/O unless the INT0 and
INT1 bits in the IE register are enabled
 After the hardware interrupts in the IE register are enabled,
the controller keeps sampling the INTn pin for a low-level
signal once each machine cycle
 To make INT0 and INT1 edge-triggered interrupts, we must

program the bits of the TCON register
Recap of TCON
Recap of TCON

b. Edge triggered mode:
 In edge-triggered interrupts
 The external source must be held high for at least one
machine cycle, and then held low for at least one machine
cycle
 The falling edge of pins INT0 and INT1 are latched by the
8051 and are held by the TCON.1 and TCON.3 bits of TCON
register
4.3 External
Harware
Interrupts:
b. Edge
triggered
mode:
Interrupt flag bits

 When the 8051 is powered up, the priorities are assigned

according to the following
 In reality, the priority scheme is nothing but an internal
polling sequence in which the 8051 polls the interrupts in the
sequence listed and responds accordingly
Problem
 Discuss what happens if interrupts INT0, TF0, and INT1 are
activated at the same time. Assume priority levels were set by
the power-up reset and the external hardware interrupts are
edge-triggered.
• Solution:
 If these three interrupts are activated at the same time, they
are latched and kept internally.
 Then the 8051 checks all five interrupts according to the
sequence listed above Table.
 If any is activated, it services it in sequence.
 Therefore, when the above three interrupts are activated, IE0
(external interrupt 0) is serviced first, then timer 0 (TF0), and
finally IE1 (external interrupt 1)
Interrupt priority register (IP)

 We can alter the sequence of interrupt priority by assigning a
higher priority to any one of the interrupts by programming a
register called IP (interrupt priority)
 To give a higher priority to any of the interrupts, we make the
corresponding bit in the IP register high
Interrupt priority register (IP)

• When two or more interrupt bits in the IP register are set to high they
are serviced according to the sequence of Table
a) Program the IP register to assign the highest priority to

INT1(external interrupt 1), then
(b) discuss what happens if INT0, INT1, and TF0 are activated at the
same time. Assume the interrupts are both edge-triggered
 a) MOV IP,#00000100B ;IP.2=1 assign INT1 higher priority.
(OR)
SETB IP.2 ;IP.2=1 assign INT1 higher priority.
 When INT0, INT1, and TF0 interrupts are activated at the same
time, the 8051 services INT1 first, then it services INT0, then
TF0.
5.1 8051 Input/Output interfacing – LCD and LED
5.1 8051 Input/Output interfacing –

LCD and LED
Note: LED is already discussed (on/off a port bit)
Module:5 I/O interfacing with Microcontroller 8051
Module:5 I/O interfacing with

Microcontroller 8051
• LCD, LED, Keypad, Analog-to-Digital Convertors, Digital-to-Analog

Convertors, Sensor with Signal Conditioning Interface
1. Why an LCD is needed?

 Display units are the most important output devices in embedded
projects and electronics products.
 LCD is finding widespread use replacing LEDs
 The declining prices of LCD
 The ability to display numbers, characters and graphics
 Incorporation of a refreshing controller into the LCD, thereby
relieving the CPU of the task of refreshing LCD
 Ease of programming for characters and graphics
2. 16x2 LCD : Most commonly used display unit

 16x2 LCD is one of the most used display unit.
 As per the name the 2x16 has 2 lines with 16 characters on each
line.
 It supports all the ASCII chars and is basically used for
displaying the alpha numeric characters.
 Here each character is displayed in a matrix of 5x7 pixels.
 Apart from alpha numeric chars it also provides the provision to
display the custom characters by creating the pattern.
2.1 16x2 LCD : Registers

 The 16X2 LCD has two built in registers namely data register and
command register.
 Command Register - stores the command instructions
given to the LCD.
A command is an instruction given to LCD to do a
predefined task like initializing, clearing the screen, setting the
cursor position, controlling display etc.
 Data Register - stores the data to be displayed on the LCD.

The data is the ASCII value of the character to be
displayed on the LCD.
Note: Identify which port is connected to Command/data lines

and which port pins to RS, R/W, E
3.1 Commands for an LCD display

Two rows of LCD are accessed using the cursor position to the
respective location given as 8 bits.
Row 0 starts from 80 and goes until 8F
Row 1 starts from C0 and goes until CF.
3.2 Programming an LCD display

STEP1: Initialization of LCD.
STEP2: Sending command to LCD.
STEP3: Writing the data to LCD.


Step1: LCD initialization (common for almost all applications)
1. Send 38H to the 8 bit data line for initialization
2. Send 0FH for making LCD ON, cursor ON and cursor blinking ON.
3. Send 06H for incrementing cursor position.
4. Send 01H for clearing the display and return the cursor.

Step2: Sending command to LCD
Send the command data to command register
Make R/W low.
Make RS=0 if data byte is a command
Pulse E from high to low with some delay.
Repeat above steps for sending another data.

Step3: Writing the data to LCD
Place data byte on the data register.
Make R/W low.
make RS=1 if the data byte is a data to be displayed.
Pulse E from high to low with some delay.
Repeat above steps for sending another data.
Problem 1: Write an 8051 assembly language program to

display the message “N” and “O” on LCD display.
; IN this problem, the LCD’s 8 bit command/data lines are
connected to P1’s 8 lines. P2 is used for RS, R/W, E pins.
;call a time delay before sending next data/command
;P1.0-P1.7 are connected to LCD data pins D0-D7
;P2.0 is connected to RS pin of LCD
;P2.1 is connected to R/W pin of LCD
;P2.2 is connected to E pin of LCD
Problem 1: Write an 8051 assembly language program to display
the message “N” and “O” on LCD display.
ORG 0000H
MOV A, #38H ; INITIALIZE 2x16 LCD
ACALL COMNWRT ; call command subroutine
ACALL DELAY ; give LCD some time
MOV A, #0EH ; display on, cursor on
MOV A, #01 ; clear LCD
MOV A, #06H ; shift cursor right
MOV A, #84H ; cursor at line 1, pos. 4

MOV A, #’N’ ; display letter N
ACALL DATAWRT ; call display subroutine
MOV A, #’O’ ; display letter O
ACALL DATAWRT ; call display subroutine
AGAIN: SJMP AGAIN ; stay here
COMNWRT: ; send command to LCD

MOV P1, A ; copy reg A to port 1
CLR P2.0 ; RS=0 for command
CLR P2.1 ; R/W=0 for write
SETB P2.2 ; E=1 for high pulse
CLR P2.2 ; E=0 for H-to-L pulse
RET
DATAWRT: ; write data to LCD

MOV P1, A ; copy reg A to port 1
SETB P2.0 ; RS=1 for data
RET
DELAY: MOV R3, #50 ; 50 or higher for fast CPUs

HERE2: MOV R4, #255 ; R4 = 255
HERE: DJNZ R4, HERE ; stay until R4 becomes 0
DJNZ R3, HERE2 ; stay until R3 becomes 0
RET
END
Problem 2: Write an 8051 assembly language program to

display the message “HELLO” on LCD display using DPTR. ;
P1.0-P1.7=D0-D7, P2.0=RS, P2.1=R/W, P2.2=E
ORG 0000H
MOV DPTR, #MYCOM ; Address of Initializing comm : #MYCOM
C1: CLR A
MOVC A,@A+DPTR ; Load command(byte) to A
ACALL COMNWRT ; Write command to LCD
ACALL DELAY ; Provide some delay
INC DPTR ; Increment to next command’s address
JZ SEND_DAT ; End of command is a zero; Check that
SJMP C1 ; If not the end of command, next command
Problem 2: Write an 8051 assembly language program to display the
message “HELLO” on LCD display using DPTR. ; P1.0-P1.7=D0-D7,
P2.0=RS, P2.1=R/W, P2.2=E
SEND_DAT: ; End of Commands, send data
MOV DPTR, #MYDATA; Address of First byte of Message
D1: CLR A ; Clear A
MOVC A,@A+DPTR ; Move the letter(byte) to A
ACALL DATAWRT ; Write byte(letter) to LCD
ACALL DELAY ; Delay after DATAWRT
INC DPTR ; Increment to next address
JZ AGAIN ; End of Data is 0
SJMP D1 ; If not End of Data, next character
AGAIN: SJMP AGAIN ; If end of Data, then Just wait
P2.0=RS, P2.1=R/W, P2.2=E
COMNWRT: ; send command to LCD
MOV P1, A ; copy reg A to P1
CLR P2.0 ; RS=0 for command
RET
P2.0=RS, P2.1=R/W, P2.2=E
DATAWRT: ; send DATA to LCD
MOV P1, A ; copy reg A to P1
SETB P2.0 ; RS=1 for Data
RET
P2.0=RS, P2.1=R/W, P2.2=E
DELAY: MOV R3, #250 ; 50 or higher for fast CPUs
HERE2: MOV R4, #255 ; R4 = 255
HERE: DJNZ R4, HERE ; stay until R4 becomes 0
DJNZ R3, HERE2
RET
ORG 300H
MYCOM: DB 38H, 0EH, 01, 06, 84H, 0 ; commands and null
MYDATA: DB “HELLO”, 0 ; Data is stored
END

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3.

1 8051 : Architecture, Memory organization and Machine cycle

3.1 8051 Microcontroller Architecture, Memory

Module:3 Microcontroller Architecture: Intel 8051

Module:3 Microcontroller Architecture:

• Microcontroller 8051 - Organization and Architecture, RAM-

1.1 8085 Introduction

1.2a 8051 Features

1.2b Features: 8051 Family series

1.2b Features: 8051 Family series

1.2b Features: Major manufacturers

1.2c Features: ATMEL Series

2.1 8051 Pin diagram and pin details

2.1 8051 Pin diagram and

2.1 8051 Pin diagram and pin details

2.1 8051 Pin diagram and pin details

2.1 8051 Pin diagram and pin details

2.1 8051 Pin diagram and pin details

2.1 8051 Pin diagram and pin details

2.1 8051 Pin diagram and pin details

2.2 8051 Architecture: detailed:

2.2 8051 Architecture: detailed:

3. 8051 Architecture (simplified)

3. 8051 Architecture: 1. CPU

3. 8051 Architecture: 2. Interrupt control

When subroutine is completed then the execution of main program

3. 8051 Architecture: 3. RAM & ROM

3. 8051 Architecture: 4. BUS Control

3. 8051 Architecture: 5. Crystal Oscillator

3. 8051 Architecture: 6. IO ports

3. 8051 Architecture: 7. Timers/Counters

3. 8051 Architecture: 8. Serial Port

3. 8051 Architecture: RECAP

4. 8051 Memory Organization

4. 8051 Memory Organization:

4. 8051 Memory Organization:

4. 8051 Memory Organization:

4. 8051 Memory Organization:

4. 8051 Memory Organization:

4. 8051 Memory Organization:

4. 8051 Memory Organization:

4. 8051 Memory Organization:

4. 8051 Memory Organization:

4. 8051 Memory Organization:

4. 8051 Memory Organization:

4. 8051 Memory Organization:

4. 8051 Memory Organization:

4. 8051 Memory Organization:

4. 8051 Memory Organization:

4. 8051 Memory Organization:

4. 8051 Memory Organization:

4. 8051 Memory Organization:

4. 8051 Memory Organization:

4. 8051 Memory Organization:

4. 8051 Memory Organization:

4. 8051 Memory Organization:

4. 8051 Memory Organization:

4. 8051 Memory Organization:

4. 8051 Memory Organization:

4. 8051 Memory Organization:

4. 8051 Memory Organization:

4. 8051 Memory Organization: