Rubrics for CEC-141 DLD Lab

Lab #: 02
Lab Title: To Verify Basic Gates truth tables
Submitted by: Sir Shahzad
Name Registration #
M.Zain Fa20-bce-015

Rubrics name & number Marks

In-Lab Post-Lab

Engineerin R2: Use of Engineering Knowledge and follow Experiment

g Procedures:
Knowledge Ability to follow experimental procedures, control variables, and
record procedural steps on lab report.
Problem R5: Data/Evidence Measurements:
Analysis Ability to record raw data / evidence.

Design R8: Best Coding Standards:

Ability to follow the coding standards and programming practices.

Modern R9: Understand Tools: Ability to describe and explain the

Tools principles behind and applicability of engineering tools.
Usage

Individual R12: Individual Work Contributions: Ability to carry out

and individual responsibilities.
Teamwork

R13: Management of Team Work:

Ability to appreciate, understand and work with multidisciplinary
team members.

Rubrics # R2 R5 R8 R9 R12 R13

In –Lab

Post- Lab
Lab Report # 2
Title: To Verify Basic Gates truth tables

Objectives:
The objective of the lab is to use the basic logic gates on the ePAL trainer and verify
their result with the truth tables, also to memorize the numbers of the ICs for future
references so that it is easier for the student to recognize the IC just by looking at it.

Q #1Simulate the following logic gates in Logic Works, verify truth table and show Timing
Diagram.

AND Gate
Circuit:

Truth Table:
a b x
0 0 0
0 1 0
1 0 0
1 1 1

Timing Diagram
OR Gate
Circuit:

Truth Table:
a b x
0 0 0
0 1 1
1 0 1
1 1 1

Timing Diagram:

NAND Gate
Circuit:

Truth Table:
a b c
0 0 1
0 1 1
1 0 1
1 1 0

Timing Diagram:

XOR Gate
Circuit:

Truth Table:
a b x
0 0 0
0 1 1
1 0 1
1 1 0

Timing Diagram:

XNOR Gate

Circuit:
Truth Table:
a b x
0 0 1
0 1 0
1 0 0
1 1 1

Timing Diagram:

Q#2 Give the following three digits 4-bit strings. Simulate and evaluate the 4-bit result
after the following logical operation.

And Gate

Nand Gate
XOR Gate

Not a Gate
Conclusion:
After the completion of tasks, I can use Logic Works to verify the basic logic gates and
their results with different combinations of inputs, I can implement the same on the
ePAL trainer, and I can now recognize the ICs by their chip numbers and the function of
each pin on all the different ICs.