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  • Ec3251 Mte1-1

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    Harshil Suthar
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    The document is a mid-term examination for a sixth semester VLSI Design course. It contains 4 questions: 1. Write a Verilog code for a one-bit adder/subtractor using conditionals and define a user defined primitive for a given Boolean function. 2. Design a XNOR gate using transmission gates and code it in Verilog. Also evaluate outputs for given input conditions. 3. Design a 2-to-4 decoder in Verilog and use it structurally to design a 4-to-16 decoder, providing a block diagram. 4. Write Verilog code for a given circuit using any style and provide a test bench.

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    EC3251_MTE1-1

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    The document is a mid-term examination for a sixth semester VLSI Design course. It contains 4 questions: 1. Write a Verilog code for a one-bit adder/subtractor using conditionals and define a user defined primitive for a given Boolean function. 2. Design a XNOR gate using transmission gates and code it in Verilog. Also evaluate outputs for given input conditions. 3. Design a 2-to-4 decoder in Verilog and use it structurally to design a 4-to-16 decoder, providing a block diagram. 4. Write Verilog code for a given circuit using any style and provide a test bench.

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    14 views1 page

    Ec3251 Mte1-1

    Uploaded by

    Harshil Suthar
    The document is a mid-term examination for a sixth semester VLSI Design course. It contains 4 questions: 1. Write a Verilog code for a one-bit adder/subtractor using conditionals and define a user defined primitive for a given Boolean function. 2. Design a XNOR gate using transmission gates and code it in Verilog. Also evaluate outputs for given input conditions. 3. Design a 2-to-4 decoder in Verilog and use it structurally to design a 4-to-16 decoder, providing a block diagram. 4. Write Verilog code for a given circuit using any style and provide a test bench.

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    of 1

    Faculty of Engineering

    School of Electrical, Electronics & Communication


    B.Tech. (ECE)
    VI Semester
    Mid-Term-I Examination: 2021-22
    EC3251 VLSI Design with Verilog HDL
    (CLOSED BOOK)

    Duration: 1 Hours Max. Marks: 20

    Instructions:
    • Answer all questions
    • Missing data, if any, may be assumed suitably.

    1. (a) Using Condition operator in Verilog write a code which can work as one bit [3]
    Adder & Subtractor both.

    (b) Write a Verilog code that defines the User Defined Primitive (UDP) which [2]
    performs the following Boolean Function:
    F(a,b,c)=∑(0,2,3,4,7)

    2. (a) Design a XNOR gate using transmission gate and write its switch level [4]
    Verilog code.
    (b) If a = 1’b1, b = 2’b00, c = 2’b10. [1]
    What will be the output for the given conditions?
    Z={4{a},2{b}}
    Y={4{a},3{b}, c}

    3. Design a 2to4 decoder in Verilog using any style. Use this decoder to design [5]
    4to16 decoders using structural. Use Block Diagram.

    4. Write a Verilog code for the given circuit using any style of coding. Also [5]
    Write test bench for it.

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