UNIT - V

AUXILIARY MEMORY
Auxiliary memory (also referred to as secondary storage) is the non-volatile memory lowest-cost,
highest-capacity, and slowest-access storage in a computer system. It is where programs and data
kept for long-term storage or when not in immediate use.
Such memories tend to occur in two types-sequential access (data must access in a linear sequence)
and direct access (data may access in any sequence). The most common sequential storage device is
the hard disk drives, whereas direct-access devices include rotating drums, disks, CD-ROMs, and
DVD-ROMs.It used as permanent storage of data in mainframes and supercomputers.
Auxiliary memory may also refer to as auxiliary storage, secondary storage, secondary memory,
external storage or external memory. Auxiliary memory is not directly accessible by the CPU;
instead, it stores noncritical system data like large data files, documents, programs and other back
up information that supplied to primary memory from auxiliary memory over a high-bandwidth
channel, which will use whenever necessary. Auxiliary memory holds data for future use, and that
retains information even the power fails.
Magnetic Drum

What Does Magnetic Drum Mean?

A magnetic drum is a magnetic storage device used in many early computers as the main working
memory, similar to how modern computers use random access memory (RAM) cards. In some cases,
magnetic drum memory was also used for secondary storage. It is basically a metal cylinder that is
coated with a magnetic iron-oxide material where the changing magnetic polarities are used to store
data on its surface, similar to how modern disk drives use magnetism to store and retrieve data.

Magnetic drums are also known as drum memory.

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Techopedia Explains Magnetic Drum

The magnetic drum was invented by Gustav Tauschek in Austria in 1932, but it was only in the 1950s
to 60s that it gained wide use as the main memory for computers, and to an extent, secondary storage.
The main storage area of the magnetic drum is the metal cylinder coated with a ferromagnetic layer.
Read-write heads were positioned micrometers above the drum's surface, along a predefined track, in
order to produce an electromagnetic pulse that can be stored by changing the orientation of the
magnetic particles which the read-write head is hovering over. So as the drum rotates and the read-
write heads produce electric pulses, a series of binary digits are generated. Reading was done simply
by detecting which magnetic particles were polarized and which were not.

Read-write heads are positioned in rows along the axis of the drum, one head for each track, with
some drums containing up to 200 tracks. The heads were in a fixed position so each one only
monitored a single track, which made latency for read and writes dependent on the speed of the
drum's spin. Faster rotating drums achieve higher data rates, but 3,000 rpm was a common speed for
many manufacturers.

The hard disk drive was invented in 1954, while the magnetic-core memory was invented in 1947.
The emergence and subsequent advancement in both meant the decline of the magnetic drum as the
main and secondary storage for computers. By the 1970s magnetic drums ceased to be manufactured.

Semiconductor Memory
Definition: Semiconductor memory is the main memory element of a microcomputer-based system
and is used to store program and data. The main memory elements are nothing but semiconductor
devices that stores code and information permanently.
The semiconductor memory is directly accessible by the microprocessor. And the access time of the
data present in the primary memory must be compatible with the operating time of the
microprocessor. Thus semiconductor devices are preferred as primary memory.

ROM, PROM, EPROM, EEPROM, SRAM, DRAM are semiconductor (primary) memories. The
fabrication of semiconductor memories is done through CMOS technology.
The semiconductor memory offers high operating speed and has the ability to consume low power.
Also, these are fabricated as IC’s thus requires less space inside the system.

Block Diagram of Semiconductor Memory

As we have already discussed that semiconductor memories are nothing but primary memory formed
of semiconductor devices.

Basically, an IC of a semiconductor memory consists of n number of address lines and m data lines.
Thereby providing the total memory capacity of 2n × m bits. This implies that it holds 2n memory
locations and each location can store data up to m-bit.
The functional block diagram representation of semiconductor memory is given below:

As we can see that the block diagram consists of a row and a column address decoder along with
memory array and I/O buffer. These buffers hold the data for a certain period of time.

The total number of address lines i.e., n is divided into q and r and are separately provided as input to
row and a column decoder. The output from these two decoders forms a matrix array having size 2q ×
2r having 2n crossing points.
These crossing points are referred to as memory cells. And each memory cell holds the ability to
store one-bit of binary data. So, whenever the processor sends an address to the memory IC then the
row and column decoder accordingly select one line, which correspondingly selects a memory cell
from the matrix.
In this way, the memory cells are selected by the address sent by the processor. Further, the data can
be read or written in a particular selected memory cell according to the generated control signal.

Initially, the memory cells of semiconductor memory were fabricated of passive components like
resistor and capacitor. After that diodes were also used. But with the advent of new technologies,
bipolar and MOS transistors took the places of diodes, resistors and capacitors.

And now-a-days the memory cells are made using CMOS and HMOS technology that possesses high
operational speed with low power consumption.

Let us now move further and understand how semiconductor memories are classified?

Types of Semiconductor Memory

Basically, the semiconductor memory is classified as volatile and non-volatile memory.

Volatile memories are those memories that store the data temporarily. More specifically we can say
that data is stored in volatile memory only till the duration power supply to the IC is ON. And once
the supply gets OFF then the stored data gets lost.

As against in non-volatile type of memory, the data retained in the memory even if the power supply
is OFF. Thus we can say that in non-volatile memory the data is stored on a permanent basis.

Let us now move further and understand the further classification of non-volatile and volatile
memory.

Non-Volatile Memory

ROM: It stands for Read-Only Memory. It is a memory array that is permanently programmed by the
manufacturer or programmer only once. Hence its data cannot be changed by the processor once it is
programmed.
Thus the processor can only read the data present in this memory hence called read-only memory or
fixed memory.

The process of loading the data in the ROM is known as programming. The way in which ROM is
programmed further classifies it.
  Custom programmed ROM (ROM): These memories are programmed by the
manufacturer at the time of its fabrication. Hence is stored permanently.
 Programmable ROM (PROM): PROM’s are programmed by the user but these offers
re-programmability after erasing previously loaded contents. There exist two methods by
which the contents of the ROM are erased.
EPROM: It stands Erasable Programmable Read-Only Memory. The EPROM offers re-
programming, by erasing the previously stored data by making use of ultraviolet rays. The memory-
erasing time lies between 10 to 30 minutes.
Basically, the electrons in the isolated gate of MOS transistor of memory cells get removed when
irradiated with ultraviolet rays. Thereby allowing removal of stored data in the memory cell through
the control gate.

Further, in order to reprogram the EPROM, the memory chip is inserted in the PROM programmer
socket. A PC provides interfacing to the PROM programmer and the programmer installs the
information to be loaded in the chip from the personal computer.

EEPROM: It is an abbreviation used for electrically erasable programmable read-only memory.

Initially, the data in E2PROM is erased by applying external voltage at the erase pin of the chip. But
this somewhat increases the complexity of the overall system.
So, the latest versions provide incorporation of supply voltage within the chip.

Volatile Memory

RAM: RAM stands for Random Access Memory. It is a volatile memory that means the data is stored
temporarily until the power supply is ON. This memory is used for short term storage of data. At the
time of read operation, RAM exhibits non-destructive nature.
This means that while reading, the data present in the memory location will not be destroyed. But
writing data in a memory location where some data is already present will destroy the previously
stored data. Or we can say that the newly entered data will replace the previous data.

RAM is majorly classified into two categories:

 SRAM: It is an abbreviation for Static Random Access Memory. SRAM has an array of
flip-flops that are used to store the data. The memory cells consist of flip flops that hold
the data until the power supply is on.
 DRAM: It is an acronym for Dynamic Random Access Memory. It is also a read/write
memory that stores the data in the form of charges in the capacitor and transistor pair
present in the memory cell.
However, the stored charge takes some milliseconds to get dissipated therefore periodic
refreshing of the elements is required, in order to have random access feature.
Memory Hierarchy Design and its Characteristics
In the Computer System Design, Memory Hierarchy is an enhancement to organize the memory such
that it can minimize the access time. The Memory Hierarchy was developed based on a program
behavior known as locality of references.The figure below clearly demonstrates the different levels of
memory hierarchy :
This Memory Hierarchy Design is divided into 2 main types:
1. External Memory or Secondary Memory –
Comprising of Magnetic Disk, Optical Disk, Magnetic Tape i.e. peripheral storage
devices which are accessible by the processor via I/O Module.
2. Internal Memory or Primary Memory –
Comprising of Main Memory, Cache Memory & CPU registers. This is directly
accessible by the processor.
We can infer the following characteristics of Memory Hierarchy Design from above figure:
1. Capacity:
It is the global volume of information the memory can store. As we move from top to
bottom in the Hierarchy, the capacity increases.
2. Access Time:
It is the time interval between the read/write request and the availability of the data. As
we move from top to bottom in the Hierarchy, the access time increases.
3. Performance:
Earlier when the computer system was designed without Memory Hierarchy design, the
speed gap increases between the CPU registers and Main Memory due to large difference
in access time. This results in lower performance of the system and thus, enhancement
was required. This enhancement was made in the form of Memory Hierarchy Design
because of which the performance of the system increases. One of the most significant
ways to increase system performance is minimizing how far down the memory hierarchy
one has to go to manipulate data.
4. Cost per bit:
As we move from bottom to top in the Hierarchy, the cost per bit increases i.e. Internal
Memory is costlier than External Memory.
Associative Memory
Associative memory is also known as content addressable memory (CAM) or associative storage
or associative array. It is a special type of memory that is optimized for performing searches
through data, as opposed to providing a simple direct access to the data based on the address.
it can store the set of patterns as memories when the associative memory is being presented with a
key pattern, it responds by producing one of the stored pattern which closely resembles or relates to
the key pattern.
it can be viewed as data correlation here. input data is correlated with that of stored data in the
CAM.
it forms of two type:
1. auto associative memory network
2. hetero associative memory network
Associative memory of conventional semiconductor memory (usually RAM) with added
comparison circuity that enables a search operation to complete in a single clock cycle. It is a
hardware search engine, a special type of computer memory used in certain very high searching
applications. Applications of Associative memory :-
1. It can be only used in memory allocation format.
2. It is widely used in the database management systems, etc.
Advantages of Associative memory :-
1. It is used where search time needs to be less or short.
2. It is suitable for parallel searches.
3. It is often used to speedup databases.
4. It is used in page tables used by the virtual memory and used in neural networks.
Disadvantages of Associative memory :-
1. It is more expensive than RAM.
2. Each cell must have storage capability and logical circuits for matching its content with
external argument.
Virtual Memory

Virtual Memory (VM) Concept is similar to the Concept of Cache Memory. While Cache solves the
speed up requirements in memory access by CPU, Virtual Memory solves the Main Memory (MM)
Capacity requirements with a mapping association to Secondary Memory i.e Hard Disk. Both Cache
and Virtual Memory are based on the Principle of Locality of Reference. Virtual Memory provides an
illusion of unlimited memory being available to the Processes/ Programmers.

In a VM implementation, a process looks at the resources with a logical view and the CPU looks at it
from a Physical or real view of resources. Every program or process begins with its starting address as
‘0’ ( Logical view). However, there is only one real '0' address in Main Memory. Further, at any
instant, many processes reside in Main Memory (Physical view). A Memory Management Hardware
provides the mapping between logical and physical view.

VM is hardware implementation and assisted by OS’s Memory Management Task. The basic facts of
VM are:

 All memory references by a process are all logical and dynamically translated by hardware into
physical.
 There is no need for the whole program code or data to be present in Physical memory and
neither the data or program need to be present in contiguous locations of Physical Main
Memory. Similarly, every process may also be broken up into pieces and loaded as necessitated.
 The storage in secondary memory need not be contiguous. (Remember your single file may be
stored in different sectors of the disk, which you may observe while doing defrag).
 However, the Logical view is contiguous. Rest of the views are transparent to the user.
 Figure 19.1 Storage views
Virtual Memory Design factors

Any VM design has to address the following factors choosing the options available.

 Type of implementation – Segmentation, Paging, Segmentation with Paging

 Address Translation – Logical to Physical
 Address Translation Type – Static or Dynamic Translation
o Static Translation – Few simpler programs are loaded once and may be executed many
times. During the lifetime of these programs, nothing much changes and hence the
Address Space can be fixed.
o Dynamic Translation – Complex user programs and System programs use a stack,
queue, pointers, etc., which require growing spaces at run time. Space is allotted as the
requirement comes up. In such cases, Dynamic Address Translation is used. In this
chapter, we discuss only Dynamic Address Translation Methods.
 A Page/Segment table to be maintained as to what is available in MM
 Identification of the Information in MM as a Hit or Page / Segment Fault
 Page/Segment Fault handling Mechanism
 Protection of pages/ Segments in Memory and violation identification
 Allocation / Replacement Strategy for Page/Segment in MM –Same as Cache Memory. FIFO,
LIFO, LRU and Random are few examples.

Segmentation

A Segment is a logically related contiguous allocation of words in MM. Segments vary in length. A
segment corresponds to logical entities like a Program, stack, data, etc. A word in a segment is
addressed by specifying the base address of the segment and the offset within the segment as in figure
19.2.
Figure 19.2 Example of allotted Segments in Main Memory
A segment table is required to be maintained with the details of those segments in MM and their
status. Figure 19.3 shows typical entries in a segment table. A segment table resides in the OS area in
MM. The sharable part of a segment, i.e. with other programs/processes are created as a separate
segment and the access rights for the segment is set accordingly. Presence bit indicates that the
segment is available in MM. The Change bit indicates that the content of the segment has been
changed after it was loaded in MM and is not a copy of the Disk version. Please recall in Multilevel
hierarchical memory, the lower level has to be in coherence with the immediately higher level. The
address translation in segmentation implementation is as shown in figure 19.4. The virtual address
generated by the program is required to be converted into a physical address in MM. The segment
table help achieve this translation.
Figure 19.4 Address Translation in Segmentation Mechanism
Generally, a Segment size coincides with the natural size of the program/data. Although this is an
advantage on many occasions, there are two problems to be addressed in this regard.

1. Identifying a contiguous area in MM for the required segment size is a complex process.
2. As we see chunks are identified and allotted as per requirement. There is a possibility that there
may be some gaps of memory in small chunks which are too small to be allotted for a new
segment. At the same time, the sum of such gaps may become huge enough to be considered as
undesirable. These gaps are called external fragmentation. External fragments are cleared by a
special process like Compaction by OS.

Paging

Paging is another implementation of Virtual Memory. The logical storage is marked as Pages of some
size, say 4KB. The MM is viewed and numbered as page frames. Each page frame equals the size of
Pages. The Pages from the logical view are fitted into the empty Page Frames in MM. This is
synonymous to placing a book in a bookshelf. Also, the concept is similar to cache blocks and their
placement. Figure 19.5 explains how two program’s pages are fitted in Page Frames in MM. As you
see, any page can get placed into any available Page Frame. Unallotted Page Frames are shown in
white.
Figure 19.5 Virtual Memory Pages to MM Page Frame Mapping
This mapping is necessary to be maintained in a Page Table. The mapping is used during address
translation. Typically a page table contains virtual page address, corresponding physical frame
number where the page is stored, Presence bit, Change bit and Access rights ( Refer figure19.6). This
Page table is referred to check whether the desired Page is available in the MM. The Page Table
resides in a part of MM. Thus every Memory access requested by CPU will refer memory twice –
once to the page table and second time to get the data from accessed location. This is called the
Address Translation Process and is detailed in figure19.7.

Figure 19.6 Typical Page Table Entry

Virtual Page Address Page Frame Number Presence bit P Change bit C Access Rights
A 0004000 1 0 R, X
B 0645728 0 1 R, W, X
D 0010234 1 1 R, W, X
F 0060216 0 0 R
 Figure 19.7
Virtual Memory Address Translation in Paging Implementation
Page size determination is an important factor to obtain Maximum Page Hits and Minimum
Thrashing. Thrashing is very costly in VM as it means getting data from Disk, which is 1000 times
likely to be slower than MM.

In the Paging Mechanism, Page Frames of fixed size are allotted. There is a possibility that some of
the pages may have contents less than the page size, as we have in our printed books. This causes
unutilized space (fragment) in a page frame. By no means, this unutilized space is usable for any other
purpose. Since these fragments are inside the allotted Page Frame, it is called Internal
Fragmentation.

Additional Activities in Address Translation

During address translation, few more activities happen as listed below but are not shown in figures
( 19.4 and 19.7), for simplicity of understanding.

 In segmentation, the length of the segment mentioned in the segment table is compared with the
offset. If the Offset exceeds it is a Segment Violation and an error is generated to this effect.
 The control bits are meant to be used during Address Translation.
o The presence bit is verified to know that the requested segment/page is available in the
MM.
o The Change bit indicates that the segment/page in main memory is not a true copy of
that in Disk; if this segment/page is a candidate for replacement, it is to be written onto
the disk before replacement. This logic is part of the Address Translation mechanism.
o Segment/Page access rights are checked to verify any access violation. Ex: one with
Read-only attribute cannot be allowed access for WRITE, or so.
 The requested Segment/Page not in the respective Table, it means, it is not available in MM and
a Segment/Page Fault is generated. Subsequently what happens is,
o The OS takes over to READ the segment/page from DISK.
 o A Segment needs to be allotted from the available free space in MM. If Paging, an
empty Page frame need to be identified.
o In case, the free space/Page frame is unavailable, Page Replacement algorithm plays the
role to identify the candidate Segment/Page Frame.
o The Data from Disk is written on to the MM
o The Segment /Page Table is updated with the necessary information that a new block is
available in MM

Translation Look-aside Buffer (TLB)

Every Virtual address Translation requires two memory references,

 once to read the segment/page table and

 once more to read the requested memory word.

TLB is a hardware functionality designed to speedup Page Table lookup by reducing one extra access
to MM. A TLB is a fully associative cache of the Page Table. The entries in TLB correspond to the
recently used translations. TLB is sometimes referred to as address cache. TLB is part of the
Memory Management Unit (MMU) and MMU is present in the CPU block.

TLB entries are similar to that of Page Table. With the inclusion of TLB, every virtual address is
initially checked in TLB for address translation. If it is a TLB Miss, then the page table in MM is
looked into. Thus, a TLB Miss does not cause Page fault. Page fault will be generated only if it is a
miss in the Page Table too but not otherwise. Since TLB is an associative address cache in CPU, TLB
hit provides the fastest possible address translation; Next best is the page hit in Page Table; worst is
the page fault.

Having discussed the various individual Address translation options, it is to be understood that in a
Multilevel Hierarchical Memory all the functional structures coexist. i.e. TLB, Page Tables, Segment
Tables, Cache (Multiple Levels), Main Memory and Disk. Page Tables can be many and many levels
too, in which case, few Page tables may reside in Disk. In this scenario, what is the hierarchy of
verification of tables for address translation and data service to the CPU? Refer figure19.8.

Figure 19.8 Address Translation sequence in a Multilevel Memory with TLB

Address Translation verification sequence starts from the lowest level i.e.

TLB -> Segment / Page Table Level 1 -> Segment / Page Table Level n
Once the address is translated into a physical address, then the data is serviced to CPU. Three
possibilities exist depending on where the data is.

Case 1 - TLB or PT hit and also Cache Hit - Data returned from CPU to Cache

Case 2 - TLB or PT hit and Cache Miss - Data returned from MM to CPU and Cache

Case 3 - Page Fault - Data from disk loaded into a segment / page frame in MM; MM returns data to
CPU and Cache

It is simple, in case of Page hit either Cache or MM provides the Data to CPU readily. The protocol
between Cache and MM exists intact. If it is a Segment/Page fault, then the routine is handled by OS
to load the required data into Main Memory. In this case, data is not in the cache too. Therefore, while
returning data to CPU, the cache is updated treating it as a case of Cache Miss.

Advantages of Virtual Memory

 Generality - ability to run programs that are larger than the size of physical memory.
 Storage management - allocation/deallocation either by Segmentation or Paging mechanisms.
 Protection - regions of the address space in MM can selectively be marked as Read Only,
Execute,..
 Flexibility - portions of a program can be placed anywhere in Main Memory without relocation
 Storage efficiency -retain only the most important portions of the program in memory
 Concurrent I/O -execute other processes while loading/dumping page. This increases the overall
performance
 Expandability - Programs/processes can grow in virtual address space.
 Seamless and better Performance for users.

address space
Address space is the amount of memory allocated for all possible addresses for a
computational entity -- for example, a device, a file, a server or a networked computer. The system
provides each device and process address space that holds a specific portion of the processor's address
space. This can include either physical or virtual addresses accessible to a processor or reserved for a
particular process.
The width of its address bus and registers often restricts the processor's address space.
However, a memory management technique called virtual memory can increase the size of the address
space to be higher than that of the physical memory.
Address space is classified as either flat or segmented. Flat address spaces are represented by
incrementally increasing integers starting at zero. Independent segments augmented by offsets or
values added to create secondary addresses represent segmented addresses.
In some systems, address space can be converted from one format to another through a thunking
process -- low-level, machine-generated code used to deploy details of a software system. Thunking is
often used to delay calculations until the system requires a result.
Some types of address spaces
Here are a few examples of address spaces.
Virtual address space
A binary number in the virtual memory that allows processes to use a location in primary storage is
a virtual address. This accommodates use of the main memory, independent of other processes, and
supports the use of more space than what actually exists. It works by relegating some content to a hard
disk or internal flash drive.
Logical address space
A logical address space is a set of logical addresses a computer generates for a specific program. A
group of physical addresses mapped to corresponding logical addresses is called a physical address
space.

This diagram illustrates process of assigning addresses to virtual and physical memory (RAM).

IPv4 to IPv6

In terms of IP address space, concern emerged that the 32-bit address space of IP version 4 (IPv4)
would be inadequate to support the enormous growth of the internet. So, IPv6 was developed with its
128-bit address space.

Subnetting IPv6 address space

The primary purpose of subnetting IPv6 address space is to improve address allocation efficiency by
subnetting a segment of a network address space. Splitting an extensive network into smaller groups
of interconnected networks reduces traffic, which helps increase network speeds because traffic does
not have to flow through unnecessary routes. The subnet mask shares the network portion of the IP
address and the host address range with the computer. The host address range comprises addresses
assigned to host computers on the network.

Subnetting improves the efficiency of address allocation, splitting a larger network into smaller
groups of interconnected networks.

Address space layout randomization

Address space layout randomization is a memory security mechanism used to prevent potential
exploitation of memory corruption vulnerabilities. Adding randomness into a process's virtual
memory address space makes it challenging to exploit vulnerabilities.

Address space in Microsoft Azure

The address space for a virtual network in Microsoft Azure comprises one or more addresses that do
not overlap. Classless Inter-Domain Routing notations specify these address ranges and define them
as public or private. When creating a virtual network, the custom private IP address space is specified
using both public and private addresses. Azure then assigns resources, including a private IP address,
from the address space you set in a virtual network.
Address space vs. memory space

The addresses programmers use are called virtual addresses. A set of these virtual addresses is
called address space.

The place where the address was saved in the main memory is known as the location. A group of
locations is called memory space.

Address space translation

Address space translation describes the process of concentrating the frame number with the offset part
of a logical address. This approach helps form a physical address.

The page table base register holds the base address for the page table of the current process. This is
essentially a processor register the operating system manages.

Address Mapping using Pages

The table execution of the address mapping is interpreted if the data in the address space and the
memory space are each split into a collection of fixed sizes. The physical memory is broken down
into sets of similar size known as blocks, which can range from 64 to 4096 words each. The term
page defines a set of address spaces of a similar size.
Example − Suppose a page or block consists of 1K words, then address space can be divided into
1024 pages and main memory can be divided into 32 blocks.
Even though both a page and a block are divided into sets of 1K words, a page defines the cluster of
address space, while a block defines the cluster of memory space. The programs are also divided into
pages.
Segments of programs are transferred from auxiliary memory to main memory in records similar to
the size of a page. The term page frame is at times can recognize a block.
Example − Suppose a computer has an address space of 8K and a memory space of 4K. If they are
each divided into sets of 1K words, we receive eight pages and four blocks as displayed in the figure.
At any given time, upto four pages of address space can be accessible in main memory in any one of
the four blocks.
The mapping from address space to memory space is made available if each virtual address is
considered to be defined by two numbers - both a page number address and a line within the page. In
a computer with words per page, p bits can determine a line address and the remaining high-order
bits of the virtual address determine the page number.
The diagram shows a virtual address having 13 bits. As each page includes = 1024 words, the higher-
order three bits of a virtual address will define one of the eight pages and the lower-order 10 bits
define the line address inside the page.
Cache Memory-
 
Before you go through this article, make sure that you have gone through the previous article
on Cache Memory.
 
We have discussed-
 

Cache memory bridges the speed mismatch between the processor and the main memory.

 
When cache hit occurs,
 The required word is present in the cache memory.
 The required word is delivered to the CPU from the cache memory.
 
When cache miss occurs,
 The required word is not present in the cache memory.
 The page containing the required word has to be mapped from the main memory.
  This mapping is performed using cache mapping techniques.
 
In this article, we will discuss different cache mapping techniques.
 
Cache Mapping-
 
 Cache mapping defines how a block from the main memory is mapped to the cache memory
in case of a cache miss.
OR
 Cache mapping is a technique by which the contents of main memory are brought into the
cache memory.
 
The following diagram illustrates the mapping process-
 

 
Now, before proceeding further, it is important to note the following points-
 

NOTES
 
 Main memory is divided into equal size partitions called as blocks or frames.
 Cache memory is divided into partitions having same size as that of blocks called as lines.
 During cache mapping, block of main memory is simply copied to the cache and the block
is not actually brought from the main memory.

 
Cache Mapping Techniques-
 
Cache mapping is performed using following three different techniques-
 

 
1. Direct Mapping
2. Fully Associative Mapping
3. K-way Set Associative Mapping
 
1. Direct Mapping-
 
In direct mapping,
 A particular block of main memory can map only to a particular line of the cache.
 The line number of cache to which a particular block can map is given by-
 

Cache line number

= ( Main Memory Block Address ) Modulo (Number of lines in Cache)

 
Example-
 
 Consider cache memory is divided into ‘n’ number of lines.
 Then, block ‘j’ of main memory can map to line number (j mod n) only of the cache.
 
 
Need of Replacement Algorithm-
 
In direct mapping,
 There is no need of any replacement algorithm.
 This is because a main memory block can map only to a particular line of the cache.
 Thus, the new incoming block will always replace the existing block (if any) in that particular
line.
 
Division of Physical Address-
 
In direct mapping, the physical address is divided as-
 

 
2. Fully Associative Mapping-
 
In fully associative mapping,
 A block of main memory can map to any line of the cache that is freely available at that
moment.
 This makes fully associative mapping more flexible than direct mapping.
 
Example-
 
Consider the following scenario-
 

 
Here,
 All the lines of cache are freely available.
 Thus, any block of main memory can map to any line of the cache.
 Had all the cache lines been occupied, then one of the existing blocks will have to be
replaced.
 
Need of Replacement Algorithm-
 
In fully associative mapping,
 A replacement algorithm is required.
  Replacement algorithm suggests the block to be replaced if all the cache lines are occupied.
 Thus, replacement algorithm like FCFS Algorithm, LRU Algorithm etc is employed.
 
Division of Physical Address-
 
In fully associative mapping, the physical address is divided as-
 

 
3. K-way Set Associative Mapping-
 
In k-way set associative mapping,
 Cache lines are grouped into sets where each set contains k number of lines.
 A particular block of main memory can map to only one particular set of the cache.
 However, within that set, the memory block can map any cache line that is freely available.
 The set of the cache to which a particular block of the main memory can map is given by-
 

Cache set number

= ( Main Memory Block Address ) Modulo (Number of sets in Cache)

 
Also Read- Set Associative Mapping | Implementation and Formulas
 
Example-
 
Consider the following example of 2-way set associative mapping-
 
 
Here,
 k = 2 suggests that each set contains two cache lines.
 Since cache contains 6 lines, so number of sets in the cache = 6 / 2 = 3 sets.
 Block ‘j’ of main memory can map to set number (j mod 3) only of the cache.
 Within that set, block ‘j’ can map to any cache line that is freely available at that moment.
 If all the cache lines are occupied, then one of the existing blocks will have to be replaced.
 
Need of Replacement Algorithm-
 
 Set associative mapping is a combination of direct mapping and fully associative mapping.
 It uses fully associative mapping within each set.
 Thus, set associative mapping requires a replacement algorithm.
 
Division of Physical Address-
 
In set associative mapping, the physical address is divided as-
 
 
Special Cases-
 
 If k = 1, then k-way set associative mapping becomes direct mapping i.e.
 

1-way Set Associative Mapping ≡ Direct Mapping

 
 If k = Total number of lines in the cache, then k-way set associative mapping becomes fully
associative mapping.

Page Replacement
A virtual memory organization is a consolidation of hardware and software systems. It can make
efficient utilization of memory space all the software operations are handled by the memory
management software.
The hardware mapping system and the memory management software together form the structure of
virtual memory.
When the program implementation starts, one or more pages are transferred into the main memory
and the page table is set to denote their location. The program is implemented from the main memory
just before a reference is created for a page that is not in memory. This event is defined as a page
fault.
When a page fault appears, the program that is directly in execution is stopped just before the
required page is transferred into the main memory. Because the act of loading a page from auxiliary
memory to main memory is an I/O operation, the operating framework creates this function for the
I/O processor.
In this interval, control is moved to the next program in the main memory that is waiting to be
prepared in the CPU. Soon after the memory block is assigned and then moved, the suspended
program can resume execution.
If the main memory is full, a new page cannot be moved in. Therefore, it is important to remove a
page from a memory block to hold the new page. The decision of removing specific pages from
memory is determined by the replacement algorithm.
There are two common replacement algorithms used are the first-in, first-out (FIFO) and least
recently used (LRU).
The FIFO algorithm chooses to replace the page that has been in memory for the highest time. Every
time a page is weighted into memory, its identification number is pushed into a FIFO stack.
FIFO will be complete whenever memory has no more null blocks. When a new page should be
loaded, the page least currently transports in is removed. The page to be removed is simply
determined because its identification number is at the high of the FIFO stack.
The FIFO replacement policy has the benefit of being simple to execute. It has the drawback that
under specific circumstances pages are removed and loaded from memory too frequently.
The LRU policy is more complex to execute but has been more interesting on the presumption that
the least recently used page is an excellent applicant for removal than the least recently loaded page
as in FIFO. The LRU algorithm can be executed by relating a counter with each page that is in the
main memory.
When a page is referenced, its associated counter is set to zero. At permanent intervals of time, the
counters related to all pages directly in memory are incremented by 1.

Page Table

Page Table is a data structure used by the virtual memory system to store the mapping between logical
addresses and physical addresses.

Logical addresses are generated by the CPU for the pages of the processes therefore they are generally
used by the processes.

Physical addresses are the actual frame address of the memory. They are generally used by the
hardware or more specifically by RAM subsystems.page offset = log 2 P = p bits

The CPU always accesses the processes through their logical addresses. However, the main memory
recognizes physical address only.

In this situation, a unit named as Memory Management Unit comes into the picture. It converts the
page number of the logical address to the frame number of the physical address. The offset remains
same in both the addresses.

To perform this task, Memory Management unit needs a special kind of mapping which is done by
page table. The page table stores all the Frame numbers corresponding to the page numbers of the
page table.

In other words, the page table maps the page number to its actual location (frame number) in the
memory.

In the image given below shows, how the required word of the frame is accessed with the help of
offset.