ARCHITECTURE OF 8086 The internal architecture of 8086 is divided into two separate units. They are 1. Bus Interface Unit (BIU) 2. Execution Unit (EU) The two units function independently. The BIU is used to fetch instructions, read operands and write results. The EU is used to execute instructions that have already been fetched by the BIU. Block diagram of 8086 is shown in Figure 1.5. Bus Interface Unit (BIU) “ The BIU handles transfer of data and addresses between the processor and memory/1O devices. The bus interface unit is responsible for performing all external bus operations such as It computes and sends out addresses. It fetches instruction codes. . It stores fetched instruction codes in (FIFO) queue. . It reads data from memory and I/O devices. . It writes data to memory and I/O devices. AYA BN It relocates addresses of operands. To implement these functions the BIU contains the segment registers, instruction pointer and 6-byte instruction queue.Microprocessors and Microeo, tay 16 ‘Segment Address Segment Registers and Instruction Pointer 16 6- Byte Offset Instruction Address Queue » 1c Decoding circuitry, veg timing and” | control unit ND 2 MN i AH | AL] AX ! General[ BH | BL_| BX i Purpose!” CH cL_| cx {Registers [DH DL_ | Dx ALU Pointers } & Index SP { Registers BP. i Al i DI OPERANDS _|*———>| i FLAGS i EXECUTION UNIT (EU) Execution Uni Fig. 1.5. Block Diagram of Intel 8086 microprocessor it (EU) ; ie The EU receives opcode of an instruction from the queue and decodes then executes it. + 7 4 ‘ + fel “EU is decoding an instruction or executing an instruction, the BIU f instruction codes from the memory and stores them in the wee.2 8086 Microprocessor 1.17 no a and EU operate in parallel independently. This makes processing faster except in the cases of Jump and CALL instructions. + While EU executes instructions and the BIU fetches instructions. This is known as pipelining process. Execution Unit contains the following elements. 1, General purpose registers. 2. Stack Pointer. 3. Base Pointer, 4. Index Registers. 5. ALU. 6. Flag Register. 7. Instruction decoder. 8. . Timing and control unit. egisters of INTEL 8086 Accumulator AX | AH AL Base BX | BH BL / General Counterox | CH | CL Aas Data DX DH DL Stack Pointer SP Base Pointer BP ieee Source Index si Registers Destination Index ol Code Segment cs Data Segment DS Rae “ Stack Segment ss Extra Segment ES Instruction Pointer IP Status Register FLAGS Fig, 1.6. Register Organization of Intel 80861.18 Microprocessors and Microcontroller The Intel 8086 contains the following registers. 1. General Purpose Registers. 2. Pointer and Index Registers. 3. Segment Registers. 4. Instruction Pointer. 5. Status Flags. General Purpose Registers There are four 16-bit general purpose registers such as AX, BX, CX and DX. Each of these 16-bit registers is further subdivided into two 8-bit registers as shown below. 16-bit Registers sit High ender a = order AX AH a BX BH a cx CH aL Dx DH a “Register AX services as an accumulator and Registers BX, CX and DX are used as general purpose registers. “General purpose registers also serve as special purpose registers. As a special purpose register BX serves as a base register for the computation of memory } address. Register CX is used as a counter in case of multi-iteration instructions. When content of CX becomes zero such instructions terminate the execution. DX register is also used for memory addressing when data are transferred between I/O port and memory using certain /O instructions. In 8086 memory addresses are to be calculated using the contents of the segment register and effective memory address.[re 8086 Microprocessor 1.19 “ The registers in this group are as follows 1, Stack Pointer (SP), | Base Pointer (BP). Source Index (SI), Destination Index (DI). Instruction pointer (IP) yeep 4, Stack Pointer (SP) The stack pointer is used in instructions which use stack ie., PUSH, POP, CALL, RET, etc., It always points to a location in memory known as the stack top. However, the complete address is formed by adding the contents of the stack segment register. Base Pointer (BP) nN “The purpose of this register is to provide indirect access to data in stack register. It may also be used for general data storage. s Source Index (SI) and Destination Index (Dl) “> These registers may be used for general data storage, (The main purpose of these registers is to Store offset in case of indexed, base indexed and relative base indexed addressing n modes. Es struction pointer (IP) This register is also referred as “Program Counter”. It is used for the calculation of actual_memory addresses of instructions. It stores the _ offset for the instruction. * During an instruction fetch, IP contents are added to the code segment register. Segment Registers * Intel introduced the concept of memory segmentation in the 8086 processor. In memory segmentation, memory is divided into a number of parts called segments, “In the 8086, the 1 MB physical memory is divided into four segments such as 1, Code Segment. ._°°2. Data Segment. |1.20 Microprocessors:and Microcontrolle 3. Stack Segment. 4. Extra Segment. + Each segment addressed by a 16-bit segment register is as follows 1. CS-—Code Segment Register 2. DS-—Data Segment Register 3. SS-Stack Segment Register 4. ES —Extra Segment Register 01000 Extra Segment o0oDO0 | ES oop00 Unused lemory Aréa o0coo Stack Segment m oos0 | SS 00900 ‘Unused ; Memory Area 00800 Data Segment o0s0 | DS 00500 Zunused Mémory Area 00400 Code Segment 0010 | cs 00100 i ences, Memory Area Memory Fig. 1.7. Memory Segmentation A segment register points to the starting address of a memory segment currently being used. For example, the code segment registers points to the starting address of the code segment and so on.ghe 8086 Microprocessor 21 “ The maximum capacity of a segment may be upto 64 kilobytes. The starting address of a segment is divided by 16. The 8086 memory address is 20 bits. * All memory addresses of the 8086 are computed by summing the contents of the segment register and an offset address. Advantages of Segment Registers 1, Allow the memory capacity to be 1 megabyte even though the addresses associated with the individual instructions are only 16 bits wide. v Allow the instruction, data or stack portion of a program to be more than 64 K bytes long by using more than one code, data or stack segment. Facilitate the use of separate memory areas for a program, its data and the stack. we 4. Permit a program and/or its data to be put into different areas of memory each time the program is executed. * The Flag Register is also referred as “Program Status Word”. | 15 14 13°12 1 °#«10 9 8 7 6 & 43 2 1 =O The status flags are Carry, Parity, Auxiliary carry, Zero, Sign and Overflow. These status flags reflect conditions produced by the execution of arithmetic or logic instructions. Carry Flag (CF) “Carry is set after an arithmetic operation results in a carry out of MSB or a borrow in subtraction. This flag is also used in some shift and rotate instructions. Parity Flag (PF) “It is set if the result of byte operation or lower byte of the word operation contains an even number of 1’s. Auxiliary Carry Flag (AF) “The flag is set if there is a carry out of the lower nibble to the higher nibble of an 8-bit quantity. It is used for BCD operations. Zero Flag (ZF) ** The zero flag is set whenever the result of the operation is zero. Sign Flag (SF) “The sign flag is set if, after the arithmetic or logic operations, the MSB of the result. It indicates that the result is negative. | Overflow Flag (OF) ** This flag is used to detect magnitude overflow in signed arithmetic. For addition operation, the flag is set when there is a carry into the MSB and no carry out of the MSB or vice versa. “+ For subtraction operation, the flag is set when the MSB needs a borrow and there is no borrow from MSB or vice versa. ‘+ There are three control flags such as Direction Flag, Interrupt Enable Flag and Trap Flag. These can be set or cleared by program to alter processor operations. Lenses aeDirection Flag (DF) ~& Itis used with string operations, when it is set, it causes the string instructions to auto decrement or to process strings from right to left otherwise from left to right. Interrupt Enable Flag (IEF) ‘This flag enables the 8086 to recognize the external interrupt requests. When IF = 0, all maskable interrupts are disabled. It has no effect on either non-maskable interrupts or internally generated interrupts. Trap Flag (TF) Setting the TF bit puts the processor into single step mode for debugging.