Department of Electrical Engineering

Indian Institute of Technology, Kanpur

EE 619A: VLSI System Design 2022-23 Semester II

Instructor: Dr. Rik Dey (email id: rikdey@iitk.ac.in)

Objectives: This course will cover the aspects of analysis, design and synthesis of Very Large Scale Integrated
(VLSI) circuits using Complementary Metal Oxide Semiconductor (CMOS) technology. Complex digital VLSI
systems are designed and built in a hierarchical way using integrated circuits (IC) as building blocks. This course
will provide an insight into basics of digital IC design at logic, layout, schematic, and physical levels. An emphasis
will be given on the synthesis-based approach to digital IC design starting from designing basic building blocks
of combinatorial and sequential circuits to ending with designing bigger digital systems. At the end of the course,
the student should be able to develop an understanding of the digital IC design techniques, the basic design flow
in VLSI system design automation, the trade-offs associated with the design methodologies, and methods to
systematically design complex digital VLSI systems based on the current trend and technology.

Pre-requisite: There is no official pre-requisite for the course.

Special Emphasis: This is a graduate level course on digital IC design. Hence, it is expected that the student must
have sound knowledge on undergraduate level digital circuit design. Also, the student should know the basics of
how to write simple codes.

Course Content: The content for the course has been divided in several modules as follows:

Module Content Outline Tentative Number of Lectures

Introduction, why digital, future prospects 1
CMOS transistors, models, scaling 2
CMOS fabrication and layout 1
Interconnects (wires) in CMOS technology 1
Basic CMOS logic gate characteristics 2
Circuit optimization, Method of Logical Effort 2
Combinational circuit design: CMOS logic style 1
Combinational circuit design: Pass transistor logic 1
Combinational circuit design: Logic optimization, Technology Mapping 1
Nanoscale Design, Low Power Design 1
Mid-Semester Examination
Sequential elements, Dynamic CMOS Logic 1
Design of latches and flip-flops 2
Timing analysis 1
Memory, Programmable Logic 2
Physical design: Floor planning, Routing 2
Design and Testability 1
Review, Future directions 1
End-Semester Examination
Reserved for covering other topics, Verliog, Layout, etc. 2
Schedule and Venue:
Class Timing: Tuesday and Friday from 3:30 pm – 04:45 pm. Venue: L03 in LHC (Lecture Hall Complex).
The materials related to the course will be uploaded in Mookit (Hello IITK portal) from time to time.
All the classes will be in offline mode. No video/audio recording of materials will be available.

Office Hours: Monday/Wednesday/Thursday from 3:30 pm – 5:00 pm in WL121 (Western Lab).

Please send me an email if you need any help. Extra office hours will be scheduled upon your requests.

Evaluation Components and Policies:

Attendance in class (total): 5%

Homework/Assignment (total): 15%
Two Quizzes (total): 10% (5% each)
Two Projects (total): 20% (10% each)
Mid-Semester Examination: 20%
End-Semester Examination: 30%

Policies:

• All the evaluations will be in offline mode.

• Bio-metric attendance will be taken in class and will contribute towards the total marks as mentioned above.
Only sanctioned leave from the appropriate authority will be considered if absent.
• Marks will be deducted for late submission of homework/assignment and projects. The exact scheme for
deduction of marks on late submission will be announced with each homework/assignment and project.
• One of the quizzes will be before the mid-semester examination, and one of them will be between the mid-
semester examination and the end-semester examination. The date of conducting each quiz will be announced
only a week before.
• Only the projects (not homework/assignments) should be submitted in groups of no more than 5 students, and
the details regarding the project and group formation will be announced in due time.
• There will be no make-up for any of the quizzes.
• Final grading will be relative based on the overall statistics of the class.

Course Policies: Involvement in copying and/or cheating and/or use of unfair means and/or encouraging such
behaviours will be strictly penalized and reported to the appropriate authority. If someone is found guilty in such
cases, that person may either be de-registered from the course or be awarded an F grade.

Books and References:

1. CMOS VLSI Design by Neil H.E. Weste and David Harris, 4th edition, Addison-Wesley/Pearson. Or
CMOS VLSI Design by Neil H.E. Weste, David Harris and Ayan Banerjee, 3rd Edition, Pearson Education.
2. Digital Integrated Circuits by Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic, 2nd Edition,
Prentice Hall India.