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Fitipower-Integrated-Tech-FR9889SPCTR C516194 4
Fitipower-Integrated-Tech-FR9889SPCTR C516194 4
Description Features
The FR9889 is a synchronous step-down DC/DC Low RDS(ON) Integrated Power MOSFET
converter that provides wide 4.5V to 23V input (120mΩ /100mΩ)
voltage range and 3A continuous load current Internal Compensation Function
capability. At light load condition, the FR9889 can Internal Power Good Function
operate at power saving mode to support high Wide Input Voltage Range: 4.5V to 23V
efficiency and reduce power lose. Adjustable Output Voltage Down to 0.925V
3A Output Current
The FR9889 fault protection includes cycle-by-cycle 340kHz Switching Frequency
current limit, UVLO, output overvoltage protection External Programmable Soft-Start or Internal
and thermal shutdown. The soft-start function 600µs Soft-Start
prevents inrush current at turn-on. This device Cycle-by-Cycle Current Limit
uses current mode control scheme which provides Over-Temperature Protection with Auto Recovery
fast transient response. Internal compensation OVP, UVLO
function reduces external compensation Hiccup Short Circuit Protection
components and simplifies the design process. In SOP-8 Exposed Pad Package
shutdown mode, the supply current is about 1µA.
C: Green
Package Type
SP: SOP-8 (Exposed Pad)
FR9889-1.1-MAY-2016 1
FR9889
Typical Application Circuit
FR9889-1.1-MAY-2016 2
FR9889
Functional Pin Description
Pin Name Pin No. Pin Function
High Side Gate Drive Boost Pin. A capacitor rating between 10nF~100nF must be connected from
BST 1
this pin to LX. It can boost the gate drive to fully turn on the internal high side NMOS.
Power Supply Input Pin. Placed input capacitors as close as possible from VIN to GND to avoid
VIN 2
noise influence.
Voltage Feedback Input Pin. Connect FB and VOUT with a resistive voltage divider. This IC
FB 5
senses feedback voltage via FB and regulates it at 0.925V.
Enable Input Pin. Pull high to turn on IC, and pull low to turn off IC. Connect VIN with a 100kΩ
SHDN 7
resistor for self-startup.
Soft-start Pin. This pin controls the soft-start period. Connect a capacitor from SS to GND to set the
SS 8
soft-start period. If disconnect capacitor from SS to GND, the internal soft-start time will be 600µs.
Ground Pin. The exposed pad must be soldered to a large PCB area and connected to GND for
Exposed Pad 9
maximum power dissipation.
Block Diagram
FR9889-1.1-MAY-2016 3
FR9889
Absolute Maximum Ratings (Note 1)
● Supply Voltage VIN ----------------------------------------------------------------------------------------- -0.3V to +25V
● Enable Voltage VSHDN ----------------------------------------------------------------------------------- -0.3V to +25V
● LX Voltage VLX ---------------------------------------------------------------------------------------------- -1V to VIN+0.3V
● BST Pin Voltage VBST ------------------------------------------------------------------------------------- VLX-0.3V to VLX+6.5V
● All Other Pins Voltage ------------------------------------------------------------------------------------ -0.3V to +6V
● Maximum Junction Temperature (TJ) ----------------------------------------------------------------- +150°C
● Storage Temperature (TS) ------------------------------------------------------------------------------- -65°C to +150°C
● Lead Temperature (Soldering, 10sec.) --------------------------------------------------------------- +260°C
● Power Dissipation @TA=25°C, (PD) (Note 2)
SOP-8 (Exposed Pad) ------------------------------------------------------------------------ 2.08W
● Package Thermal Resistance, (θJA)
SOP-8 (Exposed Pad) ------------------------------------------------------------------------ 60°C/W
● Package Thermal Resistance, (θJC)
SOP-8 (Exposed Pad) ------------------------------------------------------------------------ 15°C/W
Note 1:Stresses beyond this listed under “Absolute Maximum Ratings" may cause permanent damage to the device.
2
Note 2:PCB heat sink copper area = 10mm .
FR9889-1.1-MAY-2016 4
FR9889
Electrical Characteristics
(VIN=12V, TA=25°C, unless otherwise specified.)
Parameter Symbol Conditions Min Typ Max Unit
(Note 3)
Thermal Shutdown Threshold TSD 165 °C
FR9889-1.1-MAY-2016 5
FR9889
Typical Performance Curves (Continued)
VIN=12V, VOUT=3.3V, C1=10µF×2, C2=22µF×2, L1=10µH, TA=+25°C, unless otherwise noted.
IOUT=0A IOUT=3A
VIN 20mV/div.
IL 1A/div.
VLX 5V/div.
VLX 5V/div.
4ms/div. 4µs/div.
Figure 5. Steady State Waveform Figure 6. Steady State Waveform
IOUT=0A IOUT=3A
4ms/div. 4ms/div.
Figure 7. Power On through VIN Waveform Figure 8. Power On through VIN Waveform
IOUT=0A IOUT=3A
IL 1A/div.
VLX 5V/div.
VLX 5V/div.
100ms/div. 100ms/div.
Figure 9. Power Off through VIN Waveform Figure 10. Power Off through VIN Waveform
FR9889-1.1-MAY-2016 6
FR9889
Typical Performance Curves (Continued)
VIN=12V, VOUT=3.3V, C1=10µF×2, C2=22µF×2, L1=10µH, TA=+25°C, unless otherwise noted.
IOUT=0A IOUT=3A
4ms/div. 4ms/div.
Figure 11. Power On through SHDN Waveform Figure 12. Power On through SHDN Waveform
IOUT=0A IOUT=3A
IL 1A/div. IL 1A/div.
VLX 5V/div.
VLX 5V/div.
4ms/div. 80µs/div.
Figure 13. Power Off through SHDN Waveform Figure 14. Power Off through SHDN Waveform
IOUT=0.1A to 3A
VOUT 200mV/div.
VOUT 1V/div.
IL 1A/div.
IL 2A/div.
400us/div. 10ms/div.
Figure 15. Load Transient Waveform Figure 16. Short Circuit Test
FR9889-1.1-MAY-2016 7
FR9889
Typical Performance Curves
VIN=12V, VOUT=3.3V, C1=10µF×2, C2=22µF×2, L1=10µH, TA=+25°C, unless otherwise noted.
100 100
90 90
80 80
70 70
Efficiency(%)
Efficiency(%)
60 60
50 50
40 40
30 30
20 20
5V to 1.2V 5V to 3.3V
10 10 12V to 3.3V
12V to 1.2V 19V to 3.3V
0 0
0.01 0.1 1 10 0.01 0.1 1 10
Load Current(A) Load Current(A)
Figure 17. Efficiency vs. Load Current Figure 18. Efficiency vs. Load Current
100 0.95
90 0.945 IOUT=400mA
80 0.94
Feedback Voltage (V)
70 0.935
Efficiency(%)
60 0.93
50 0.925
40 0.92
30 0.915
20 0.91
12V to 5V
10 0.905
19V to 5V
0 0.9
0.01 0.1 1 10 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
Load Current(A) Ambient Temperature (℃)
Figure 19. Efficiency vs. Load Current Figure 20. Feedback Voltage vs. Temperature
400
IOUT=400mA
Switching Frequency (kHz)
380
360
340
320
300
280
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
Ambient Temperature (℃)
FR9889-1.1-MAY-2016 8
FR9889
Function Description
The FR9889 is a high efficiency, internal Input Under Voltage Lockout
compensation and constant frequency current mode When the FR9889 is power on, the internal circuits
step-down synchronous DC/DC converter. It has will be held inactive until VIN voltage exceeds the
integrated high-side (120mΩ, typ) and low-side input UVLO threshold voltage. And the regulator
(100mΩ, typ) power switches, and provides 3A will be disabled when VIN is below the input UVLO
continuous load current. It regulates input voltage threshold voltage. The hysteretic of the UVLO
from 4.5V to 23V, and down to an output voltage as comparator is 400mV (typ).
low as 0.925V.
Over Current Protection
Control Loop
The FR9889 over current protection function is
Under normal operation, the output voltage is implemented by using cycle-by-cycle current limit
sensed by FB pin through a resistive voltage divider architecture. The inductor current is monitored by
and amplified through the error amplifier. The measuring the high-side MOSFET series sense
voltage of error amplifier output is compared to the resistor voltage. When the load current increases,
switch current to control the RS latch. At the the inductor current will also increase. When the
beginning of each clock cycle, the high-side NMOS peak inductor current reaches the current limit
will turn on when the oscillator sets the RS latch, and threshold, the output voltage will start to drop.
turn off when current comparator resets the RS When the over current condition is removed, the
latch. Then the low-side NMOS will turn on until output voltage will return to the regulated value.
the clock period ends.
Short Circuit Protection
Enable
The FR9889 provides short circuit protection
The FR9889 SHDN pin provides digital control to function to prevent the device damage from short
turn on/turn off the regulator. When the voltage of condition. When the short condition occurs and the
SHDN exceeds the threshold voltage, the regulator feedback voltage drops lower than 0.4V, the
will start the soft start function. If the SHDN pin oscillator frequency will be reduced to 110kHz and
voltage is below the shutdown threshold voltage, the hiccup mode will be triggered to prevent the inductor
regulator will turn into the shutdown mode and the current increasing beyond the current limit. Once
shutdown current will be smaller than 1µA. For the short condition is removed, the frequency will
return to normal.
auto start-up operation, connect SHDN to VIN
through a 100kΩ resistor. Over Temperature Protection
Soft Start The FR9889 incorporates an over temperature
protection circuit to protect itself from overheating.
The FR9889 employs internal and programmable
When the junction temperature exceeds the thermal
external soft start functions to reduce input inrush
shutdown threshold temperature, the regulator will
current during start up. When SS pin doesn’t
be shutdown. And the hysteretic of the over
connect to CSS capacitor, the internal soft start time
temperature protection is 50°C (typ).
will be 600µs. When SS pin connects to CSS
capacitor, the CSS capacitor will be charged by a 6µA Internal Compensation Function
current. The equation for the soft start time is
shown as below: The stability of the feedback circuit is controlled
through internal compensation circuits. This
CSS nF ×VFB internal compensation function is optimized for most
TSS ms = applications, and this function can reduce external
ISS µA
R, C components.
The VFB voltage is 0.925V and the ISS current is 6µA.
If a 0.1µF capacitor is connected from SS pin to PG Signal Output
GND, the soft start time will be 15ms. PG pin is an open-drain output and requires a pull
up resistor. When the sensed output voltage is
Output Over Voltage Protection below 82% of nominal point, PG is actively held low
When the FB pin voltage exceeds 1.25V, the output in soft-start, standby and shutdown. It is released
over voltage protection function will be triggered and when the output voltage rises above 92% of nominal
turn off the high-side/low-side MOSFET. regulation point.
FR9889-1.1-MAY-2016 9
FR9889
Application Information
Output Voltage Setting A low ESR capacitor is required to keep the noise
The output voltage VOUT is set by using a resistive minimum. Ceramic capacitors are better, but
divider from the output to FB. The FB pin regulated tantalum or low ESR electrolytic capacitors may also
voltage is 0.925V. Thus the output voltage is: suffice. When using tantalum or electrolytic
capacitors, a 0.1µFµF ceramic capacitor should be
1
R1 placed as closee to the IC as possible.
VOUT =0.925V× 1+
2
R2
Output Capacitor Selection
Table 2 lists recommended values of R1 and R2 for The output capacitor is used to keep the DC output
most used output voltage. voltage and supply the load transient current.
Table 2 Recommended Resistance Values When operating in constant current mode, the
output ripple is determined by four components:
VOUT R1 R2
5V 44.2kΩ 10kΩ VRIPPLE t =VRIPPLE(C) t +VRIPPLE(ESR)
RIPPLE (t)
3.3V 26.1kΩ 10kΩ +VRIPPLE(ESL) (t)+V
VNOISE (t)
2.5V 16.9kΩ 10kΩ
The following figures show the form of the ripple
1.8V 9.53kΩ 10kΩ contributions.
1.2V 3kΩ 10kΩ
VRIPPLE(ESR)(t)
Place resistors R1 and R2 close to FB pin to prevent
stray pickup.
1.25
2A
1
0.75
0.5
1A
(t)
0.25
0
10 20 30 40 50 60 70 80 90
D (%)
FR9889-1.1-MAY-2016 10
FR9889
Application Information (Continued)
VOUT VOUT That will lower ripple current and result in lower
VRIPPLE(ESR, p-p) = × 1- ×ESR output ripple voltage. The ∆IL is inductor
FOSC ×L VIN
peak-to-peak ripple current:
ESL
VRIPPLE(ESL, p-p) = ×V VOUT VOUT
L+ESL IN ∆IL= × 1-
FOSC ×L VIN
VOUT VOUT
VRIPPLE(C, p-p) = × 1- The following diagram is an example to graphical
8×FOSC2 ×L×COUT VIN
represent ∆IL equation.
Where FOSC is the switching frequency, L is the
2
inductance value, VIN is the input voltage, ESR is the
1.8 L=4.7µH
equivalent series resistance value of the output
1.6
capacitor, ESL is the equivalent series inductance
1.4
value of the output capacitor and the COUT is the L=6.8µH
∆IL (A)
output capacitor. 1.2
1
Low ESR capacitors are preferred to use. L=10µH
0.8
Ceramic, tantalum or low ESR electrolytic capacitors 0.6
can be used depending on the output ripple 0.4
requirements. When using the ceramic capacitors, 0.2
the ESL component is usually negligible. 5 8 11 14 17 20 23
VIN (V)
It is important to use the proper method to eliminate
high frequency noise when measuring the output VOUT=3.3V, FOSC=340kHz
ripple. The figure shows how to locate the probe
across the capacitor when measuring output ripple. A good compromise value between size and
Remove the scope probe plastic jacket in order to efficiency is to set the peak-to-peak inductor ripple
expose the ground at the tip of the probe. It gives a current ∆IL equal to 30% of the maximum load
very short connection from the probe ground to the current. But setting the peak-to-peak inductor
capacitor and eliminating noise. ripple current ∆IL between 20%~50% of the
maximum load current is also acceptable. Then
the inductance can be calculated with the following
Probe Ground equation:
∆IL=0.3×IOUT(MAX)
FR9889-1.1-MAY-2016 11
FR9889
Application Information (Continued)
Feedforward Capacitor Selection PCB Layout Recommendation
Internal compensation function allows users saving The device’s performance and stability are
time in design and saving cost by reducing the dramatically affected by PCB layout. It is
number of external components. The use of a recommended to follow these general guidelines
feedforward capacitor C6 in the feedback network is shown as below:
recommended to improve the transient response or 1. Place the input capacitors and output capacitors
higher phase margin. as close to the device as possible. The traces
which connect to these capacitors should be as
short and wide as possible to minimize parasitic
inductance and resistance.
2. Place feedback resistors close to the FB pin.
3. Keep the sensitive signal (FB) away from the
switching signal (LX).
4. The exposed pad of the package should be
For optimizing the feedforward capacitor, knowing soldered to an equivalent area of metal on the
the cross frequency is the first thing. The cross PCB. This area should connect to the GND
frequency (or the converter bandwidth) can be plane and have multiple via connections to the
determined by using a network analyzer. When back of the PCB as well as connections to
getting the cross frequency with no feedforward intermediate PCB layers. The GND plane area
capacitor identified, the value of feedforward connecting to the exposed pad should be
capacitor C6 can be calculated with the following maximized to improve thermal performance.
equation: 5. Multi-layer PCB design is recommended.
1 1 1 1
C6= × × +
2π×FCROSS R1 R1 R2
FR9889-1.1-MAY-2016 12
FR9889
Outline Information
SOP-8 (Exposed Pad) Package (Unit: mm)
Carrier Dimensions