permesue: At the conclusion of this chapter you should be able to: 1. Understand overview of computer organization and its various units. Note the generations of computers with respect to their hardware and software. Know the advances in computer architecture. 4. Realize the advances in electronic integrated circuit technology. Appreciate evolution of microprocessors due to ‘Moore's law. We live in a computing and computer oriented society, and ‘we constantly come across multitude terms relating to com puter organization, architecture, and circuits. Before getting started with main flow of the book, we will understand these basics and how they are interlinked to microprocessors. Computing is intimately tied to the representation of decimal numbers. Advances in decimal number systems and mathemat- ical notations eventually lead to the formulation of mathema cal operations such as addition, subtraction, multiplication, division, square root, etc. Earlier, these mathematical opera- tions were done using human fingers, thereafter by using pen cil and paper or chalk and slate, The concept of programmable computers was developed by an English mechanical engineer Charles Babbage in around 1820. Programmable computer implies a machine which can do mathematical operations by some components called hardware, and the mathematical operations and the sequence in which they are worked out is controlled by a ‘program’ referred as software. The hardware consists of aetive and passive interconnected components and the software consists of commands which dictate the hard- ‘were t= do mathematical operations on the data in a desired omputers an sequence. Passive components will consume energy and are incapable of producing energy such as resistors, capacitors and inductors, while active components produce energy or power gain. With the advances in electronics, the fist active ‘component was developed in the year 1906 which was called triode, a three-electrode vacuum tube. Higher versions of this * ‘vacuum tube were invented later. Using this active compo- nent and other passive components, the first digital compu- ‘ter was built in 1946. Even though most people are familiar ‘with the decimal number system, an electronic device with ‘an active component cannot be reliably built with 10 distin- guishable states. Therefore, computers use the binary number system which has only two states, 0 and 1. An active device can be made fully conducting (representing a state) and can ‘be made not to conduct at all, representing the other state of a binary system. These two states can be reliably built with an active device. After vacuum tubes, the transistor—a semicon- ductor device—was invented and computers were built with. transistors. Further improvements in semiconductor tech- nology resulted in placing many transistors on a silicon die. ‘These developments resulted in active devices in small-scale integration, medium-scale integration, very large sacle inte- gration, and so on. Computers were built with these devices resulting in generations of computers. A computer will have a CPU or central processing unit, a main memory unit to store information, and input and output devices to feed in informa- tion and printing out information. Table 1.1 shows the gen- erations of computers, what devices were used and what the hardware was made of to do computations under the control of various levels of software. Like advancements in active devices, there are also advances in memory devices, input and output devices and software. Main memory devices started with relays, moved to magnetic core memories and now there: are highly advanced, high volume and very fast dual-data-rate dynamic memories in VLSI technology. Input and output devices started with paper tapes, card punch to the present keyboards and then moved on to'monitors, hard disks and high-speed printers, scanners, ete.’ Secondary memories are initially magnetic drums, magnetic tapes and a magnetic disks, optical disks, and so on, Software tooters Remar and Applications oe Generations of Cont pcnirecture| 8 tanguage Cie Tablet cna teenage and Assen BAC Tae : eo ae inple-user basic IBM 701, ea Sine med ad interupt mode a Petey Rely ety Pca accumulate - Pi i Fedo ate LL used with compilers Br, Discrete transistors Batch processing 604, Mansy, Core memories eroaiering Floating point: Libraries ‘Asithmetic VO : Processors a memory a02es8 - ane it a Multiprogramn ning Integated circus 2 Time sharing OS Micron SB osiisas Multi-user applications Mer cog ‘Lookahead processing © * | Microprocessor technology ‘Multiprocessors ‘Vector super-computing, Maulticomputer (1991-present) * VSLU/VHSIC processors Scalable architecture with machine language, assembly language and moved on to higher tevel languages such as FORTRAN, COBOL, C, CH}, JAVA, etc., which run under an operating system. The operat- ing system, also known as an OS, is a software that commu- nicates with computer hardware at the most elementary level. Without an operating system, no software programs can run. The OS is what allocates memory, processes tasks, accesses disks and peripherials, and serves as the user interface. 2 Ina computer, information is represented in a binary form fo reliability. The information could either be machine instruc. tions or data. Machine instructions and data representation discussed in the following sections. The input which is ethos t Assembly ot Higher Level Language (HLL) is convered standard 7 or 8 binary characers, called ASCI-7 and ASC (American Standard Code for Information Interharsg EBCDIC (Extended Binary Coded Decimal Interchan, ec and sent to the CPU. The CPU sends this informaties oo?) ‘memory. The input can also be sen directly to the memery og a device called Direct Memory Access (DMA), DMA anne discussed in later chapters. The information sent from an ye device could be either machine instructions or data ‘The coded information sent by the input device willbe convert pure binary form before the processor stats processing LSiVLST and semiconductor memory Multiprocessor OS ;, Languages Compilers Massively parallel processing Grand challenge applications CPU fetches the machine instructions from the mam ory and executes them on the data from the min men thereby altering the data as dictated by machine istston Instruction Formats and Addressing Modes Machine instruction consists of an opcode computer what function it has to perform 00! (data) specified in another field of the machine} The opcode could be of. fixed length or of YAR. iis Data could be specitied in the machine instruction oe address in main memory could be given. Thet® tions with one, two or three opezand address. address machine instruction, datais fetched fo? and the function specified by the opcode is PeTr el data and data in another register in the CPU, 294 so wlohe the register, This registers wal CE eB julator.. at i is i In two-address machines, data is FE be sil ei the oerREGISTER ADDRESSIN ‘The address speci address of one o} IG MODE ified is not the main me i -mory address but th the internal registers ofthe CPU, ° DIRECT ADDRESSING MODE The operand address s; main memory, INDIRECT ADDRESSING MODE ‘The address specified is not the operand address. This address Points to the memory location where the address ofthe oper. and is available, BASE ADDRESSING ‘The address part in the instruction will be added to the ‘contents of a register in CPU called base register and this becomes the effective address of the operand. INDEX ADDRESSING ‘The contents of the address part specified in the instruction Will be added to a register in the CPU called the index register and this becomes the effective address of the operand. IMMEDIATE ADDRESSING * ‘The operand itself is in the instruction, IMPLIED ADDRESSING ‘No operand address is given in the instruction. The opcode itself specifies the register in the CPU where the operand is available. RELATIVE ADDRESSING The address part in the instruction is added to the contents of the Program Counter (PC). This becomes the effective address of the operand. Data Formats Ina computer, the data is represented in fixed-point, floating- point and decimal formats. ecified points to the operand in the ‘An Overview of Computers and Microprocessors, SEA! FIXED POINT The data is represented in binary form and the binary point is assumed to be on the right side of the last bit which is called the Least Significant Bit (LSB). Numbers could bbe signed or unsigned, In an unsigned binary number, the bit at the leftmost position is called the Most Significant Bit (MSB). In a signed number, the most significant bit is the sign bit. ‘0° is used for positive numbers, and ‘1’ is used to represent negative numbers. Signed numbers can 'be represented either in signed magnitude, or signed one’s complement, or signed two's complement form. In signed ‘magnitude form, the magnitude of the number is in pure bbinary form for both positive and negative numbers. In signed 1's complement form, for positive numbers, the magnitude is in pure binary form and for negative numbers, the magnitude is not in pure binary form but is in 1's com- plement form. In 2's complement representation, positive ‘numbers have the magnitude in pure binary form but for negative numbers, the magnitude is in 2's complement form. Computers were builtin all the three representations ‘but most computers and computers of today use 2's com: plement representation for fixed-point numbers. In fixed. point, all numbers are in integer form. sven To handle a wide range of numbers, we can! resort to floating-point number representation. Fixed-point arithmetic is exact whereas floating-point arithmetic is not exact and will not give accurate result: This. isto be bome in mind. a ‘You may have to differentiate between two terms:'accu- racy and precision. ACCURACY vs. PRECISION : Accuracy The quality of freedom from mistake or error, of conformity to truth orto a rule. Precision ‘The degree of exactness or discrimination with which a quantity is stated. Accuracy is-distinguished from precision in the follow= ing example: A six-place table is more precise than a four place table: However, if there are errors in a six-place table, it ‘may be more or less accurate than the four-place table (IEEE. Standard Distionary). +¢SNKB_ Microprocessors and Interfacing Fig:12° Overiows in floating-point representation. NOTE: Numbers in regions 2, 4, 6 are representable. FLOATING-POINT REPRESENTATION In scientific computing, we need: 1, To be able to represent and perform arithmetic ‘operation on a wide range of numbers ; 2, Even if the number is representable, sometimes it should be very convenient to express a number, eg. 1000000 as 1.0.x 10°, 3. Sign of mantissa 4. Mantissa 5. Sign of exponent 6. Exponent A 32-bit number is called single-precision floating point representation and a 64 bit floating point number is called double-precision representation, ‘The mantissa is in fractional form and the binary point is to leR of the most significant bit in most machines, The exponent is an integer, The maximum number that could be writen: + (1-29) x 27 198 Minimum number = 2 x 2-#* ‘The other representation of floating-point format is shown in Fig. 1.2: The exponent will nt havea sign bit and tis called an expo- ‘nent with bias. For an 8-bit exponent, the bias is 128 or 127, There are two types of floating points: * Normalized floating point + Unnormalized floating point ign of the ‘82Bit (Single precision floating moa) point number) Fig. 13° Biased exponent representation of floating-point number, In normalized floating point, the first bit (MSB) has to be: “I'. Most systems, even IEEE format, have normalized floating-point numbers because it maintains higher preci- sion than unnormalized floating point. In the normalized’ floating-point representation, since the first bit has to be non-zero, to increase. the precision of floating-point arith- ‘metic, floating-point numbers in the memory will be writ. {en with implicit 1st bit. In other words, the first bit of the mantissa after the binary point will be given a weightage of 2°. This will obviously increase:the:lengthiof the mantissa: by one more bit: When the implicit first bit floating-point umbers come to the floating-point arithmetic unit, the Plicit first bit is made explicit. So in the floating-point arithmetic unit, the registers that hold the numbers rave Table 12 _ Floating-point Representations used in Various Machines [Computer Radix of | * Exponent(Base) Bits in Exponent Number System “Number Sysiém. a Member ‘for Exponent in for Manisa” NormativeThe base is 2 in case of most ma: processors, and 16 in case of IBM machi be in signed magnitude form or signed but most machines use signed-magnitude ‘mantissa. Table 1.2 shows the used in some selected machines, nes including Intel ines. Mantissa can complement form representation for floating-point representation How to represent a Floating-point Zero In fixed-point representation, Zero is represented by all zeros in the number, If the sign bit is “1” and all magnitude bits are zero, itis nega. tive zero but in this case the sign bit is complemented and the Tepresentation is fixed-point zero. In a floating-point number, once the mantissa is “0’, the ‘exponent can be anything. If the entire mantissa is ‘0’ and the exponent has any value other than maximum negative exponent, the result is ‘0° but it is called dirty zero. A clean ‘zero’ is one where you have all ‘zeros’ in the mantissa and the maximum negative exponent. 4 DECIMAL REPRESENTATION Representation of Detimal Digits in ASCIVEBCDIC Formats Each design will Have an 8-bit representation. The first four bits represent the ‘zone’ 1111-EBCDIC and 0101 for ASCII-8, the next four bits represent the decimal number ‘in one of the BCD codes but mostly in 8-4-2-1 code. ‘There are two types of representation: zoned and packed formats. When the decimal information goes through the input and output devices, the format will be zoned and within the computer, it is in packed format. Zoned and packed formats are shown in Fig. 1.4. Packed Decimal When a digit is sent through the input unit, it stays in ASCII 8 or EBCDIC format. BYTE/BYTES (Memory access width) ‘An Overview of Computers and Microprocessors GER Fig. 144 Packed format. Zoned Format ‘A simple computer has a Central Processing Unit (CPU), Main Memory (MM), secondary memory (magnetic disc), and inpot/ ‘output interfaces and devices, all intercomected as shown in Fig. 1.6. The input; is either in assembly or higher level lan- ‘guage (HLL), is converted into standard 7 or 8 binary coded characters, called ASCIL-7. and ASCIL-8 (American Standard Code for Information Interchange) or EBCDIC (Extended Binary Coded Decimal Interchange Code) and sent to CPU. ‘Then the CPU sends this information to the memory. The imput can also be sent to the memory directly using a device called. Direct Memory Access (DMA) which is not shown in Fig. 1.6.WARBAAE Microprocessors and Interfacing Fig. 1.7 Bus-organized computer system configuration. DMAis discussed in later chapters. In some devices, the Device Controller (DC) can control more than one device such asa disk and in others, the device controller and device will be integrated together such as printers. The binary coded information (pro- gram) which is sent through the input device to the main mem- ory is converted into binary form before the CPU processes it. ‘The CPU fetches the machine instructions from the main ‘memory and executes them on the data from the main memory, thereby altering the data as dictated by machine instructions. Connecting various units as shown in Fig. 1.6 consumes lots of wires and itis not very convenient either to add additional units or debug the system in case of any failure. Hence, the con- cept of bus was introduced. A bus is a conducting wire carrying a signal from a transmitting source and delivering the signal to ‘one or more receivers. There are two types of buses: + Unidirectional + Bidirectional ‘The frequencies at which the signals are transmitted on the bbus make it important thatthe bus be treated as a transmission line that needs to be terminated at both ends for a bidirectional bbus with impedances which equals the characteristic imped- ance of the wire. A unidirectional bus can be terminated with the characteristic impedance either at the end of the bus or in series with the transmitter. This termination avoids reflections ‘on the bus and assures signal integrity. Most of the computers today are bus organized as shown in Fig. 1.7. ‘There are two computer architectures: * von Neumann * Harvard von Neumann Architecture In the von Neumann architecture, there is onl xe ory in. which both instructions and ata’sre stored ~. a Sata are store DC: Device controller D_: Device (Peripheral) Operation asynchronous ‘Address data controller together, the process being known as stored pros ca cept Tiiformation is fetched from the main memory “Jocation address through a register calle mit counter, that information | If the iafomitog is fetched with 6 then that information is data) This ‘stored-program Coney was developed by designers of ENIAC, a vacuum-tube-based machine built for the US Army between 1943 and 1946. The concept was first expounded by von Neumann (1945), and incorporated into the IAS compitter (at the Princeton Institue for Advanced Studies) which was completed in 1952. All + general-purpose computers are now based on the key cot- cepts of the von Neumann ‘Though the von Neumann Purpose computing, it suffer ‘suffers ‘mation (instructions and data) must! the processor and memory through channel, and this channel has _—_—_y Fig.1.8 The von Neumann architecture,used, the processor can go no faster. This. formance-limit feator Seledvar Naas ees Pecfomance liming Harvard Architecture -<~ The other architecture, kn shown in Fig. 1.9, hag tions and the other for ‘Mark 1, an electrom the stored-program c architecture in this fo lown as Harvard architecture, (v0) memories—one for instruc. data. The name comes from Harvard ‘chanical computer which pre-dates ‘oncept of von Neumann, as does the rm. Theladvantage)of this architecture Instruction memory ‘An Overview of Computers and Microprocessors. HAN is{increased bandwidthfavailable due to separate buses for Anstructions and data, The disadvantage is that the storage is allocated to instructions and data in a fixed ratio, in current—day ‘von Neumann architecture is Used in principle but within the CPU, there are two memories called instruction cache and data cache. The main memory will have both instructions and data together. The cache (hid- den) memory isa very fast memory of limited size within the CPU. More details about the cache ‘memory is discussed later. The modified Harvard architecture is shown in Fig. 1.10. Instruction 7 Instruction 2 Ins. 3 (branch) Ins. address: Tastruction 4 processing Central unit ee) Fig. 19 The Harvard architecture. ‘System bus (instructions and data) Kins acon Feseu Microprocessors ‘and Interfacing a ‘PROCE Seale sien asynchronously/synchronously send silt Fe CPU to inform their occurrence for CPU totale aPPropte ‘eon These signals are called inerrups, Whenever an IA fopt comes and if itis tobe serviced, CPU saves the OPT rogram itis executing and goes to another program 10 Ser the equied operation coresponding tothe accepted inter Interrupts are discussed in detail in the chapter on input, output and interfacing GNPUT/OUTPUT Input and output in a computer can be done either in pro- ‘grammed 1/0 mode by the CPU or interrupt mode by the CPU afer it receives an interrupt signal from VO deviees, direct memory access (DMA) or by an 1/0 processor. VO can be done either in /]0 mapped I/O mode or memory~ ‘mapped 1/0 mode. In 110 mapped 1/0 mode, devices will be given addresses, and the CPU executes /0 machine instruc tions by specifying the I/O address. In the memory-mapped W/O, VO device registers are treated as if they are main memory locations, and the CPU performs /O by execut- ing memory reference instructions by specifying the main memory address assigned to that device, So in the memory- ‘mapped 1/0, some small part ofthe main memory address is allotted to /O/. VO operation involves three steps: i intia- i) data transfer, and ii) termination. In initiation, the CPU selects the device and prepares it for 1/0 by issuing non-data commands. In the data transfer step, data would be transferred between the VO device and CPU to memory or directly from the device to the memory. In termination, the CPU examines the status and sees whether the 1/0 is performed without any error, In programmed 1/O, all three steps will be performed by CPU. In interrupt mode, step (a) is performed by CPU first and step (b) will be performed by the CPU only when it gets an interrupt from the device for data transfer. Step (c) will be performed by the CPU. In DMA, the step (a) will be done by the CPU, step (b) will be done by DMA without CPU intervention and step (c) will be performed by the CPU when the DMA informs CPU the end of data transfer through an interrupt. All these modes are discussed in detail in Chapter 9. neh ‘ADVANCES IN COMPU ITEC! : a i There have been major advances in computer systems as could be seen in the computer-generation table. The sim- ple CPU had only fixed-point Arithmetic and Logic Unit (ALU), accumulator, program counter, and some registers , seter, base register, and central contolunit, such as index FOB ements, the simple CPU has now ical develo} i = te CPU which consists of the following become 85 units: terface Unit (BIU) 3) usta struction ques Decoding unit(s) 5 Instruction Cache (I CACHE) ¢) Data Cache (D CACHE) {) Branch Target Cache (BTC) Control w A Memory management unit {) Integer operation units {) Floating-point operation units k) Special functional units Let us briefly study the functions of each block of the super- scalar processor. PRE-FETCH UNIT AND INSTRUCTION CACHE When an instruction is fetched, decoded and sent to the ALU for execution, this unit will fetch other instructions in the main memory which are in sequence, decode the instruction, and keep them ready to be passed on to the execution units which are free, thereby reducing the time for fetching the next instructions and making the CPU run faster. DECODING UNIT ‘This unit decodes the instructions and decides the actions be taken, BUS INTERFACE UNIT This unitmakes the processor communicate with the external units such as memory, and input and output devices through the buses. It makes the CPU internal signals compatible both in voltage and current levels with the external world and also. communicates with the bus protocol. CACHE ‘The main memory of the computer system is eit Static RAM (SRAM) or monty Dynan ic RAM (GRAD. Nowadays, DDRAMs (Dual Data Rate DRAMS) are being used. These memory devices are comparatively aac Providing the information to the processor which runs many times faster. Processor registers: provide the fastest access to information held in them, ‘So the need was felt to pro- Vide a relatively small amount of very fast ‘memory between the processor and the main ‘Memory. This fast memory in the CPU is called a cache. It holds copies of repeatedly sed instructions and data. stored in the main memory. ‘The effectiveness of the cache mechanism is based on the Property of computer programs called locality of reference. Program analysis shows, that: most of their execution timesis spent on routines where many instructi nested loop or a few procedures that repeatedly call ch other. Locality of reference manifests itself in two ways: temporal and spatial. Temporal means that a recently exe. cuted instruction is likely to be executed again very soon. Spatial aspect means that instructions in close proximity to a recently executed instruction are likely to be executed soon. The concept here is to keep the active segments of the rogram in the fast cache so that total execution time can be reduced significantly as CPU accesses the cache for infor- mation and gets it faster. When the information required by the CPU is available in the cache, it is called a hit; otherwise it is referred to as amiss. When a miss happens, there are various algorithms discussed in later chapters that decide which block of information needs to be removed from the cache and a new a block of information is to be brought to the cache from the main memory. Importantly, the cache speeds up the processors. In superscalar CPUs, there are two caches—one for instructions and the other for data. MMU (MEMORY MANAGEMENT UNIT) The main memory cost is high and hence it has a limit on its size in a computer system. Large programs that need more main memory space than available, cannot run on this. Hence, the virtual-memory concept has been devel- oped to solve this problem. ‘The user need not know what the main memory size is and can assume very large mem- ory size and write programs. The virtual-memory concept keeps the executable part of large program in the main memory and the remaining part in the secondary memory such as a magnetic disk. Whenever that part ofthe pro- that is to be executed is not in the main memory, the System will swap that part of the program from the disk and the not-required part of the program that is in the main memory goes to the disk. The information addresses gen- trated for large programs are called virtual addresses and available main memory locations are physical addresses. ‘AMemory Management Unit (MIMU), is responsible for handling accesses to memory requested by the CPU. Its functions include translation of virtual addresses to physi- cal addresses. BRANCH TARGET CACHE Since a pre-fetch unit brings instructions in advance, if a branch instruction comes, the branch pre- diction foretells the outcome of the conditional branch instructions. The outcome of a branch instruction me} result in flushing out of all pre-fetched instructions and Betting a new set of instrictions. Proper branch predictio#® *“leveie frequent flushing of pre-fetched instructions an) $2Ves processor speed, BTC consists of a table with brant ‘ktsses, corresponding varget addresses, and prediction formate to be executed ‘An Overview of Computers and Micropracessors S74" CONTROL UNIT This is the central control unit controlling the functions of the computer system. There are two types of control units. One is conventional or hardwired control and the other one is microprogrammed control. The hardwired control uri faster while the microprogrammed control unit gives greater flexibility in design that allows adding new instructions very easily. Current-day processors use both types of controls for executing the machine instructions. INTEGER UNITS This unit handles fixed-point binary arithmetic and logic operations. For binary arithmetic, 2's complement represen- tation is used. All numbers are treated as integers. FLOATING-POINT UNITS This unit handles all floating-point arithmetic using IEEE standard single (32 bit), double (64 bit) and quad (128) preci- sion floating-point binary numbers. ‘Both normalized and un-normalized floating-point arith- metic could be performed. SPECIAL FUNCTIONAL UNITS (SFU) Here, depending on the requirement of the special func- tional units such as fast Fourier transforms, Digital Signal Processing (DSP) can be incorporated. ‘Apart from these advances in the CPU, there are other advances such as pipelining, computer networking, and fast serial (gigabit) transmission in modern-day computers. ‘There are (w0) classes of computers .called Complex Instruction Set Computer (CISC) and Reduced Instruction Set Computer (RISC). The differences between these two are Biven below: 1 Control unit is hardwired Conte al and microprogrammed : Complex multiclock instructionsRMHRIRIER Microprocessors and intracing C fea Most computers are designed with both RISC and CISC Tt tures. Hence they are nither RISC or CISC computers coined the word CRISC (Complex Reduced Instr Computers) for such computers. Enly computers wee designed and fabricated using discrete active components such as vacuum tubes, transistors, small- scale integrated circuits, medium-scale integrated circuits and passive components such as resistors, inductors, capaci- tors, ete. As integrated technology developed as per Moore's law, which states that numbers of transistors on a single die doubles every two years (18 months), it resulted in VLST circuits that has changed the scenario of computer fabrica- tion. The sections below show the developments in integrated technology from SSI to VLSI Small-Scale Integration (SSI) — 1960-64 + Collection of one or more gates fabricated by only a single silicon chip. Small-scale integration contains an equivalent Of 1 to 20 gates. They contain a handful of gates or flip-flops. Examples are logic gates such as NAND, NOR, Exclusive-OR, J_K flip-flops, D flip- flops, etc., (54/7400 series). SSI was introduced in the year 1960. In the 1960s, it was broadly based on bipolar transistors. * Technology: 50-100 micrometer Medium-Scale Integration (MSI}—1965-70 + Contains the equivalent of about 20-200 gates. An MSI typically contains function-building blocks such as a decoder, registers, or counters. This was introduced around 1965. Examples include ALU, Shift registers, counters, etc. + Till recently, or even today, SSIs and MSIs are used in the ‘glue’ logic to interface together larger scale elements in complex systems. + Technology: 10-50 micrometers. Large-Scale Integration (LSI) —1970-76 * Contains the equivalent of 200 to 2000 gates or more. + LsIpart includes small memories, low-end micro- processors, programmable logic devices, etc. + This was introduced in around 1970. + In 1975, digital MOS ICs have prevateg, 4, ent, even intrinsic speed advantage gf? transistors is being challenged by Mospeye’ + Programmable logic devices were introdurty " . fied Programmable Gate Arrays (FPGA, introduced in 1990. Because of the advantages in device mi ization, low power dissipation and high yield. is expected that digital MOS ICs will dominay the IC market and capture a major market share ofall semiconductor devices. « Bipolar transistor technology has shown more capacity for improvement than expected and jy still an important factor. + Another trend is the gradual introduction of GaAs (Gallium Arsenide) digital integrated tech. nology for selected applications. + Technology: 5-10 micrometers. S) Were niatur, Very Large-Scale Integration (VLSI}—1976 + The dividing line between LSI and VLSI (Very Large-Scale Integrated Circuits) is not clear and tends to be stated in terms of transistor count rather than gate count. + An IC with over 1, 000, 000 transistors is defi- nitely VLSI and includes most microprocessors and memories of today. * This VLSI started in the year 1975. * Technology: < 2 micrometers. Ultra Large Scale Integration (ULSI) * When the transistor count increases to a mil- lion transistors, the technology is referredito'as ULSI—Ultra Large-Scale Integrated Circuits» Technology: <1 micrometer. ~ aes Hence, the integrated technology started with 50-100 micrometers in 1960 and now itis’ 28 nanometers with billions of transistors on asin. sle chip. This tremendous technological devel- opment has given rise to superscalar processors and muticore processors on a single chip. Because of the. dramatic developmts in semiconduc- tor technology, computers that were fabricated with dis- Grete components have started using silicon chips. These VLSI circuits gave way for the development of fixed instruction. set microprocessors, bit-slice processors andicrocontrollers on a single silicon die, ssor is a CPU on a single chip. Bit sic egister-ALU (RALU) on a chi sequencer on another chip. These two ta be used to build a computer of required word lenge build a computer using a microprocessor, one shoul selac memories, a memory controller, a peripheral interface sad other components and interconnectthemusingasystembus A microcontroller is a computer with the CPU, limited Program and data memory and I/O interfaces, timers et “ona single chip. CPUs started with 4-bit ally grown into 8: The microproc- "¢ processors are ip and micro-instruction Processor chips and have gradu- it, 16-bit, 32-bit and 64-bit Processors (CPU) with all required support ‘components in LSUVLSI technology such as memories and peripheral interfaces to build high-end computer systems. Microprocessors are manufactured by many companies initially but Intel domi nated this field and continues to manufacture superscalar and ‘multicore microprocessors. Other companies have gradually entered into this field. It is interesting fo sce the evolution of Intel Microprocessors as shown below. 1971 Intel introduced its 4-bit bus, 4004 chip—the first microproc- essor. Speed was 60, 000 operations per second. It used 2300 ‘transistors, based on 10-micron technology and addressed 640 bytes. The die for the chip measures 3 x 4 mm. It oper- ated at 750 kHz. 1972 Intel introduced its 8008 chip, the first 8-bit microprocessor. It accessed 16 KB of memory, used 3500 transistors, based on 10-micron technology. Its speed was 60,000 instructions per second. 1974 Intel released its 2 MHz 8080 chip, an 8-bit microprocessor. It could access 64 KB of memory used 6000 transistors, based on 6-micron technology with a speed of 0.64 MIPS. This processor used two power supplies. Intel introduced the sin- gle power supply 8-bit processor 8085 in 1976 which is still widely used. 1978 Intel introduced the 4.77 MHz 8086 microprocessor. It used 16-bit registers, a 16-bit data bus, and 29,000 tran- sistors, using 3-micron technology dae na emory. Its speed was 0.33 . Later included ® MHz (0.66 MIPS) and 10 MHz (0.75 MIPS). This 8086 has a co-math processor 8087 introduced in 1980 to do floating-point arithmetic. Other mathematical operation advances in computer architecture started from his processor. ‘An Overview of Computers and Microprocessors GHG 1979 Intel introduced the 4.77 MHz 8088 microprocessor which was created as a stepping stone to the 8086, as it operates on 16 bits internally, but supports an 8-bit data bus, to use exist- ing 8-bit device-controlling chips. It contained 29, 000 tran- sistors, using 3-micron technology, and could address 1 MB of ‘memory. Its speed was 0.33 MIPS. A later version operates at 8 Miz, for a speed of 0.75 MIPS. 1985 Intel introduced the 6 MHz 80286 microprocessor and used a 16-bit data bus, 134, 000 transistors using 1.5 micron technology and offers protected mode operation. It could access 16 MB of memory or 1 GB of virtual memory. Its speed was 0.9 MIPS. Later ‘versions operate at 10 MHz 1.5 MIPS, and 12 MHz.2.66 MIPS. 1985 Intel introduced the 16 MHz 80386DX microprocessor. It ‘used 32-bit registers and a 32-bit data bus, and incorporated 275, 000 transistors (1.5 microns). It could access 4 gigabytes of physical memory. 1989 Intel announced the 25 MHz microprocessor at Spring Comdex in Chicago, Illinois. It integrated the 386, 387 math coprocessor, and added an 8 KB primary cache. It used. 1.2 million transistors, employing 1-micron technology at a speed of 20 MIPS. 1991 Intel introduced the 50 MHz 486 microprocessor. Speed was 41 MIPS. This new 486 employs 0.8-micron technology. 1992 Intel introduced the 486SL processor, designed for notebook computers. Speeds include 20 MHz (15.4 MIPS), 25 MHz. (19 MIPS) and 33 MHz (25 MIPS). The processors can address 64 MB of physical memory. They used 1.4 million transistors, employing 0.8-micron technology. 1993 Intel introduced the Pentium processor and used 32-bit reg isters, with a 64-bit data bus, giving it an address space of 4GB. Itincorporated3.1 million transistors, using 0.8-micron, BICMOS technology. Speeds are 60 MHz (100 MIPS) and 66 MHz (112 MIPS). 3 1994 Intel introduced the 75 MHz Pentium processor. Speed was 126, 5 MIPS. It uses 3.2 million transistors, employing 0.6-micron, ‘BiCMOS technology. ~~RRVERRIARRE Microprocessors and Interfacing 1995 Intel released the Pentium Pro which contained 5.5 million transistors. 1995 Intel announced the immediate a of the 133 MHz Pentium Processor. It used 3.2 million transis employing 0:35 micron BICMOS technology. Speed was 218.9 NIPS. 1996 In the 133 MHz Pentium Processor for notebook comput- ers, the processor used 0.35 micron logy, and operated on 3.3 volts of power externally, w intemal core only required 2.9 volts, 1996 Intel released the 150 MHz mobile Pentium processor, designed for use in portable computers. The processor used 0.35-micron technology, and operated on 3.3 volts of power externally, while its intemal core only requires 3.1 volts, 1997 Intel released the 7.7 million transistor Pentium II processor. This processor uses 0.25 micron technology. 1999 Intel released the 450 MHz Pentium III Processor. This proc- essor uses 0.18 micron technology and operates from 450 to 1.13 GHz frequency. Intel released Pentium IV operating at 2 GHz and there is a Pentium 4 family of processors. 2005 In 2005, Intel released its fit t frst (two independent Processor cot gy Pentium D. The ni : Pentium D, it supports Ayper pai” Oh overclocking. adi Present Status All of the currently available and ance desktop processors use Pen ‘Tejas’ project which was intended UPCOMing | iy ium 4 tage "0 produce 5° was discontinued and abandoned ears lately Intel has also abandoned plans i gn Pentium 4 processor, Figure 1.11 show how. ‘Moore’s law was; Ppl processors. 6800—Widely used 8-bit processors in 1974 (68000—Widely used internally 32-bit but with 16% ‘nal bus in 1979, 68010—An enhanced version of the 68000 released }020—32-bit processor in 1984 ; 630 An enlanced version of 68020 released in 18 68040—A successor to the 68030 released in 1989 ae {rocossor, 386 val 08 4004 19751980 1985 1970 1990idely used 8-bit processor released in 1976 rocessor released in 1979 In this chapter, evolutions of generations of computers, developments in electronics and microprocessors and advances next chapter discusses in detail about an 8-bit Microprocessor 8085 and a 16-bit processor 8086 architectures. in This Chapter Generations of computers Von Neumann and Harvard architectures Hardware, software, operating system, computer languages Batch processing, multiprogramming, timesharing Instruction formats, addressing modes Fixed-point, floating-point data formats Interrupts ISR, interrupt response time ASCII, EBCDIC Bus DMA Cache MMU RISC, CISC Moore's law SSI, MSI, LSI, VLSI Microprocessor evolution Checklist of Important Terms and Concepts Review Questions and Problems . 1, Why can a binary state device be built reliably using’an active component and not a device with ten distinguishable states? 913, What is virtual memory and what funct ‘An Ovorviow of Computers and Microprocessors cA *2, What are the advantages of 2's complement rep- resentation of binary signed numbers over other representations? 3, In an 8-bit register, the following signed binary numbers in 2's complement representation are stored. Give their decimal equivalents: 1) 11010110 i) 01101111 4!) 10000000 iv) 01000001 **4, In von Neuman architecture, how does the CPU recognize the information It received from primary memory as an instruction or data? ‘5, From input unit to CPU or memory and CPU or memory to output unit, in what format is informa tion Is transferred? 8 *6. Represent the decimal number A = -167 in fixed point (a) Signed magnitude form (b) Signed 1's complement form (©) Signed 2's complement form Represent the decimal number A = 187.52 in single precision binary biased exponent floating- point representation. #8, Represent A = 187 in ASCII zoned format using 8-4-2-1 BCD. 1. Name some i ’ a wut only, output only and input and terrupt comes, why does not the CPU immediately start the interrupt service routine, instead of completing the execution of ongo- ing instruction and start servicing the interrupt service routine? #*11. How do you compute the interrupt response time ofa computer? «12, In programmed interrupt and DMA 1/0 modes, which device with maximum speed of data trans- fer can be handled and what could be the speed of, that device? performed by the memory management #14. How many guard bits would be necessas normalized floating point unit to maintall mum precision of floating-point why? #15, What do you think are the ers and manufacturers may billions of transistors on asi REDMI NOTE}Objectives @ At the conclusion of this chapter, you should be able to: 1. Understand the organization of 8-bit microprocessor 8085. Should be able to build a microcomputer based on 8085, Describe how a microprocessor fetches and executes, ws f unit and bus interface unit. Describe functions of the 8086 queue. Demonstrate how the 8086 calculates memory addresses. NO This chapter will help us get an overview of the two basic Microprocessor families - viz. 8085 Microprocessor and ‘8080 which used two power supplies but was not well received in the market. Then the 8-bit 8085 processor, fully compatible ‘with the 8080 and with a single power supply was released, and this processor was well received and is widely used. Even today, one can see the use of the 8085 processor in some applications. It is a basic CPU with a fixed-point ALU for binary and decimal arithmetic, hardwired control unit, and some registers. It does not have even the binary MULTIPLY and DIVIDE machine instructions. We will now see the main features of this widely used 8-bit processor, that is, 8085. Main Features of the 8-bit Microprocessor 8085 + 8-bit parallel processing le +5 volt supply + Basic clock speed is 3 MHz for 8085A, 5 MHz for 8085A-2 + 12 addressable 8-bit registers, four of them can function only as two 16-bit register pairs + Six others can be used interchangeably as 8-bit registers or as 16-bit register pairs lexed address databus, ADO-AD7 sctional address bus, AB-A15 rect Memory addressing (DMA) cap: + Single bit serial-in and parallel-out faci Conta! bus (excidng 10M) fee Fig. 2.1. Block diagram of Inte! 8085.FABRE Microprocessors and Interfacing * Provides machine cycle status * 80 machine instructions Interrupt Signals Avail 5 . a in 8085 Microprocessy.°* 0 Ripped VO or memory mapped UO, It sends out one bit seri. ally and accepts one bit erally inthis line. Read and cate are part of the control bus, RST6, 5 34 The detailed pin diagram of the 8085 is given in Fig. 2.2, 2c xo 401 Vee | <8 ie 391 HOLD JINTR Vector has to be Reset our] 385 HLOA tained from sopc] s7cuxoun . ¢ iterupt controller in i sioc| [Reser response to INTA ¢ TRAP] [Reap oT : RST7.5C) RST6.SC] rstssC] INTRC] NAC] 00] AD, AD, Ads] AD, CI a5] AD, AD, vss} 2 101) ps, The machine status as given by SI, SO are as follows: [Ro Dwr ale PS DAs NSUseReeee UUuU PP? PRE eR uu 22 |. The Hold signal will be used to inform the CPU te release the address, data and control buses to be UU 2? used by the external requesti ic The Hold acknowledgement ' Fip22) Beneupmesee nal device thatthe CPU has relinquished i i 8085 id bus lines have gone into tri-state and request Functions of Various Pins of the ing ‘unit such as the DMA can use the address, da and control buses. ; ‘The Ready pin allows slower memories to be inte Microprocessor ideas ve aeeseed, « Xi, X2 are used to connect a crystal for provid faced tothe 8085, When menery acest ing clock to the CPU. used by external transaction would be completed only whet ready signal is active In case slower memete ides clock-out to be 8085 provi interfaced, itis the responsibllity of thar they 2 _ peripherals. sed for-single bit serial-in .ssert the signal to indicat seve. + SID and SOD f° RIM and SIM instructions. to ey fr data tansacions Some de and serial-out throug address bits. would be wasted by the a har ‘ons, These wast . -A8 are higher iress bits when the ALE data transactions, a a tower order a D7-DO bidirectional rasa refered as WAT states . ive and . signal is active Om gis inactive. data bus when8085 and 8066 Microprocessor Architectures RBASEzS8H% 3. The 8085 supports both modes of 1/0, To distin- guish whe memory mapped 1/0 or 1/0 mapped 1/0, called 10/M/. : Active high ofthis signal indicates 1/0 mode access, AC Cumulator and active low indicates memory mode access. ‘The accumulator is an 8-bit register used for arithmetic, logic, 4. WR/ and RD/ are write and read signals, VO, and loadistore operations. 5. RESET IN/ is given externally to reset the 8085 microprocessor. Fi 6, RESET OUT is the signal which 8085 generates in. "189 response to RESET IN? to reset the ther support The agian Sit reser containing five : es a cennected to BUSS) 1, Sign—Setifthe most significantbitof the resultis set. ‘The internal details ofthe 8085 processorare shown inFig.2.3. 2. Zero— Seti the resuezero. a WA AsTes TRAP “n | rst 55 | rer 75 eeeawans Aonorert sorta eh ei internal data bus Flag. select Power. bill supply ano es is é eee Ue x —feen 2 : | 1 pit artar| AD WR ALE 8» 8; 10% Hupa_| RESET OUT READY HOLD RESETIN Fig.23 _Intemal details of 8086. meMicroprocessors and Interfacing ‘out from 3, Auxillary carry — Setifthere was carry Out’: the bit 3 to the bit 4 of the result and this is used in BCD arithmetic. 4, Parity — Set ifthe parity the result) is even. ; 5, Carry —Set ifthere was a carry during addition, or borrow during subtraction/comparison. General Registers 1. B-bit B and 8-bit C registers can be used as one 16-bit BC register pair. When used as a pair, the C register contains a low-order byte. Some instruc- tions may use the BC register as a data pointer. 2. B-bit D and 8-bit E registers can be used as one 16-bit DE register pair. When used as a pair, the E register contains a low-order byte. Some instruc- tions may use the DE register as a data pointer. . B-bit H and 8-bit L registers can be used as one 16-bit HL register pair. When used as a pair, the L register contains a low-order byte. The HL regis- ter usually contains a data pointer that is used to reference memory addresses. STACK POINTER It is a 16-bit register. This register is always incremented or decremented by 2 PROGRAM COUNTER Itis a 16-bit register. (the number of set bits in The addressing modes a1 + Direct + Register « Register indirect + Implied + Immediate Opcode fetch, memory/peripheral READ ang, diagrams are shown in Figs. 2.4,2.5 and 26. "ey, 8085 machine instruction could be one byte in ih bytes or three bytes depending on the addressing no! opcode will indicate how many bytes ae to be fg form a machine instruction. The opcode is of fixed is one byte long. \ The instruction set of the Intel 8085 microproceser, sists of the following instructions: able in 8085 ar. + Data moving instructions + Arithmetic — Add, subtract, increment , decrement Logic — AND, OR, XOR and rotate Control transfer — Conditional, uncon call subroutine, return from subroutine ; restarts Input/Output instructions Others — Setting/clearing flag bits, ena disabling interrupts, stack operations, etc. M, (07) Ms, Signal Th T Ts Ts Ts Ts Th a oR 81,80 WO =0, S1=1,S0=1 xX Aen Ass PCH x Unspecified | our IN Dp ADy PCL 0x0; (06x) ---|---+---<—] Ae w a Fig.24 Opcode fetch machine cycle.‘My (OF) ~ t th Toot Ts 7, 7 [7 ox of CpCemasaas | Pe Ais CCH our w Apa [TX Pau p- Dp=b, OX >- F} — - 7-- — = AE 5 Ready Fig.25 Memory read machine cycle MW OR 1OW Ta oRION jin Signal 7 % Ts Ti a ox 10M | > oz onmp OR fom s1=0 50<}< To =omROR 1,80 Anas [1X a Dy=Dy | OUT X= Do-Oy AD)--ADy [foxyInterrupt Processing in 8085 TRAP is a non-maskable interrupt, tha ed by ani inition, In order forthe 8085 to service This signal on the TRAP pin must have a sustai a leading edge. If this condition occurs, the 8085 completed execution of the current instruction Gees the program counter onto the stack, and branches to the loca- tion 0024,, interrupt address vector for the TRAP). Note that the TRAP interrupt is disabled by the falling edge of the sig- nal on the pin. RST7.5 RST75 is a maskable interrupt. This means that it can be ‘enabled or disabled using the SIM instruction, 8085 responds to the RST7.5 interrupt when the signal on RST7.S pin has a leading edge. In order to service the RST7.5, 8085 completes execution of the current instruction, pushes the program counter onto the stack, and branches to 003C16. The 8085 remembers RST7.5 interrupt by setting an internal D flip-flop by the leading edge. RST6.5 RSTO. is a maskable interrupt. It can be enabled or disa- bled using the SIM instruction and is HIGH level sensitive. 1n order to service this interrupt, 8085 completes executing Current instruction, saves the program counter onto the stack and branches to the location 0034, RST5.5 The RSTS.S is a maskable interrupt. Itcan be enabled or disa- bled by the SIM instruction and is HIGH . order to service this interrupt, 8085 completes execution of the current instruction, saves the program counter onto the stack and branches to 0020,, Table22 Restart Instructions Interrupt Vectors ‘Mnemonics | : RSTS: RSTS BST is a mask is also cat Inomups INTR is HIGH level seating Wert, interrupts are active and the signal onthe INTR mite 8085 completes execution of the current instru, on, and erates an interrupt acknowledge, INTA, Low Pulse ag control bus, 8085 then expects either a -byte CALL ast through RST) ora 3-byte CALL. This instruction provided by external hardware, In other words, the int can be used te enable a tri-state buffer. The output of & buffer can be connected to 8085 data lines. The butter be designed to provide the appropriate opcode onda Note that the occurrence of INTA, tums off the 8085 rupt system in order to avoid multiple interups froma soy device, Also note that there are eight software interupgy executing RST instructions (RSTO through RST7), Eag these RST instructions has a defined vector address. They tor addresses are given in Table 2.2. ; When external interrupts enter, extemal hardw. required to provide the interrupt vector for each interrup receiving one or more external interrupts, the external har ware generates the INTR signal. INTR is given least prot If no other interrupts are present and only INTR is prese sives out a signal called Interrupt acknowledg INTA. The external hardware is the Inerrupt Conroller 825 8259 can accept eight external interrupts and will be int ized by CPU to 1. Know whether the interrupt signal is level tri gered or edge triggered 2. Call address 3. Interrupts that are to be masked 4. Priority of interrupts Once the 8259 is programmed, it external interrupts. When it receives an interrupt sign on any one of the interrupt input lines IRO-IRY, it fir checks for priority and also checks whether this interry is now ready to acceto the first, second and third INTA/ signals, 8259 sup CALL opcode, low byte of call address and high byte of call address respectively. When the 8085 receives the CALL opcode and 16-bit address, it saves the program counter ‘contents (PC) in stacks, and loads the CALL address into PC. Consequently, 8085 starts executing the corresponding. interrupt service routine. This is how external interrupts are handled, 8259 can be cascaded to accept a maximum of 64 interrupts and can also be used with the 8086 mi sor. Figure 2.7 shows the 8259 diagram with all the input and output signals. ‘The 8085 processor configuration with bus, 8-bit data bus and control bus is shown Memories, general-purpose serial (Intel 8251) and parallel (8255) peripheral interfaces, DMA controller (8237) can be - connected with peripherals to form a desired computer sys- tem. Interfacing details are discussed later. Interfacing of memories to the system bus is discussed in Chapter 8. Peripheral interfacing to the system bus is explained in Chapter 9. Having seen briefly the architecture of 8085 microprocessor, ‘we shall now study the architecture ofthe 16-bit processor 8086. ters work with 16-bit binary words. . 8086 has a 16-bit data bus. It can read or write data to a memory/port, either 16 bits or 8 bits ata time. . 8086 has a 20-bit address bus which means it can address up to 220=1MB memory location =” . Frequency range of the 8086 is 6-10 MHz. x * aa {8085 and 8086 Microprocessor Architectures . Like 8085, 8086 too can do only fixed-point arithmetic as the Integrated circult technology of that time did not permit to put additional clr~ cuitry on 8086 to do floating-point operations. Intel had designed the coprocessor 8087 that can int arithmetic and other complex mathematical operations. The 8086 can work In conjunction with 8087 to do both fixed-point, floating-point and other complex mathematical functions. ‘The 8086 is designed to operate in two modes, minimum and maximum. In the minimum mode, the 8086 processor works in a single processor environment and generates control bus signals shown in parentheses next to pins 24 through 311 in the 8086 pin diagram of Fig. 2.9. The maxt- mum mode is designed to be used to work with the coprocessor 8087 and generates signals listed next to pins 24 through 31. ‘The 8086 works in a multiprocessor environment. Control signals for memory and 1/0 are generated byan external BUS contr It can pre-fetch up to six instruction bytes from memory and queues them in order to speed up instruction execution. 9. Itrequires +5 V power supply. 10. It uses a 40-pin dual in line package. 11. 8086 has two blocks— BIUand EU. - The BIU performs all bus operations such as instruction fetching ing and writing operands for memory and calculating addresses of the memory operands, prefetch of up to six bytes of instruction code. The instruction bytes rruction queue. The EU executes ‘ADI5ADO (ADDRESS DATA BUS) ‘These lines constitute the time multiplexed memory/lO. address and data bus. ‘ALE (ADDRESS LATCH ENABLE) A HIGH on this line causes the lower order 16-bit. cs bus to be latched, which stores the addresses ard then, *- lower order 16 bits of the address bus can be used as data bu. READY READY is'the acknowledgement from the addressed mon ory or /O device that it will complete the data trans x.a ‘Microprocessors and Interfacing PIPES EplgMax {ru} mode modo. FLanis Dates Patzisa atess ators [BHE/S7 Ea mwOR [FO Fs ROWGTO [ ROIGTO CoC pee psi ps Foso Hos! Test Fa READY U < 8 (HOLD) (HuDA) 40 39 38 37 36 35 34 3 32 31 30 29 28 (ave) (NTA) .9 The 8086 pin assignments. TR (INTERRUPT REQUEST) is a level-triggered input INTA Interrupt Acknowledge from the MP. NMI NON-MASKABLE INTERRUPT ‘An edge-triggered input that causes an interrupt request to the MP. A subroutine is vectored using an interrupt vector look-up table located in the system memory. The NMI is not ‘maskable internally by software. RESET This causes the processor to immediately terminate its resent activity, The signal must be active HIGH for at least four clock cycles. It then restarts execution, ccioctures HE (005 ond 8000 Microproce: The Intel 8086 to be used as the CI ports address bu: 576, memory locations. smory addresses of the 8086 rep- resents a byle-wi jon, Sixteen-bit words will be stored in two consecutive memory locations, If the first byte of ‘word is at an even address, the 8086 can read the entire word in one operation. If the first byte of the word is at an odd address, the 8086 jon and the and the ¢ instruction set as the 8086. The 8088 also has ‘a 20-bit address bus, so it can address any one of 1,048,576 bytes in memory. The 8088, however, has an 8-bit data bus, 50 ittcan only read data from or write data to memory and ports, it read of write either ive memory locations, the 8088 will always have to do two read operations, Since the 8086 and the 8088 are almost any reference we make to the 8086 in the rest of the book will also pertain to the 8088 unless we specifically indi- cate otherwise. This is done to make reading easier. The Intel 8088, incidentally, is used as the CPU in the original IBM Personal Computer, the IBM PC/XT, and several compatible is an improved version of the 8086, and an improved version of the 8088. In addition the 80188 to a 16-bit CPU, the 80186 and 80188 each have program- mable peripheral devices integrated in the same package. In a Tater chapter we will discuss these integrated peripherals. The instruction set of the 80186 and 80188 is a superset of additional instructions. In other words, a program. an 8086 or an 8088 is upward-compatible to an 80188, but a program written for an 80186 or an 80188 may not execute correctly on an 8086 or an'808 tion set descriptions in Chapter 6, we which instructions work only with the 8018 The Intel 80286 is a 16 bit, advan which was specifically designed for tiuser or multitasking microcomputer.ESESSGIAMHIER Microprocessors and Interfacing i i additional capabilities such as mul | it 2, the 80286 functions mostly as a fast’ different h aS mules 086.1 ‘owt progr writen for an 8086 can be rin on an. SSE, SSE2, ete), system power saving modes, type 5, we will discuss the go; ing in it ing ii technology 80286 operating in its real address mode. When operating in its virtual address mode, an 80286 has features which make In Chapt it easy to keep users’ programs separate from one another processors, 286, 386, 7 in Chapter 17, we shall take tp 41% 4, ra * Up " and to protect the system program from destruction by users’ _ versions of the Pentium processors for dscussins °™* May Programs. In Chapter 15, we discuss the operation and use of the 80286. The 80286 is the CPU used in the IBM PC/AT BOSCINTERWA Before we can talk about how to write program: we need to discuss it forthe, ALU, flags, regist. specific intemal features, se , instruction byte queue, and registers. bon ecommodatng all the software designed for___As shown by the block diagram in Fig. 210, hg 2 rocessors, 8086 OBS, £0186, $0188 and CPUs divided into two independent functional pre interac nit or IU, and the execution uni or EU Be the work between these two uit speeds up proce The BIU sends out addresses, fetches instut semory, reads data fom ports and memory and wis Ports and memory. In other words, the BIU handlesa fers of data and addresses on the buses forth executors, 80286. It contains more sophisticated features for use in mul- tiuser and multitasking environments. Intel 80486 is the next member of the IA-32 architecture. This processor has the floating point processor (80387) inte~ grated into the CPU chi These processors are then fol- lowed by different versions of the Pentium Processors, with Fig. 2.10 8086 internal block diagram. (Intel Corp.)it ofthe 8086 tells the BIU where to fetch from, decodes instructions, and executes 's take a look at some of the parts of the exe- cation unit. The Execution Unit CONTROL CIRCUITRY, INSTRUCTION DECODER, AND ALU ites some condition produced controls certain opera- EU, thus effectively runs up a “flag” to tell you that a carry was produced. ‘The six conditional flags in this group are the carry flag (CF), the parity flag (PF), the auxiliary carry flag (AF), the zero flag (ZF), the sign flag (SF), and the overflow flag (OF). The names of these flags should give you hints as to what conditions affect them, Certain 8086 instructions check these flags to determine which of two alternative actions should be done in executing the instruction. 8085 and 8086 Microprocessor Architectures #EaASAI7 conditional flags are set or is of the results of some arithmetic with string instructions. the operation and use of the nine flags. GENERAL-PURPOSE REGISTERS Observe in Fig. 2.10 that the EU has eight general- purpose used together to store 16-bit data words. The acceptable reg- ister pairs are AH and AL, BH and BL, CH and CL, and DH and DL. The AH-AL pair is referred to as the AX register; the BH-BL pair is referred to as the BX register, the CH-CL pair is referred to as the CX register, and the DH-DL pair is referred to as the DX register. |-purpose register set is very similar to sors. It was designed this way so that the many programs run on the 8086 or the 8088. The advantage of using inter- nal registers for the temporary storage of data is that, since fy in the EU, it can be accessed much more ly than it could be accessed in external memory. Now look at the features of the BIU. Fig.2n1 8086 fag register ‘oat (ntl Corp. ) sons conpaneLerLAcs Or is 4 13 12 4 10 9 8/7 6 5 4 3 2 1 0 [Te] a Tor[or [rr se]e] ofr] e reer] OS UNDEFINED CARRY FLAG - SET BY CARRY OUT OF MSB Ee PARITY FLAG — SET IF RESULT HAS EVEN PARITY _|m address, this prefetch vm seeds up processing. Fetching ‘then reloaded starting current instruction executes iS and-queue scheme greally 5 the next instruction while the called pipelining. SEGMENT REGISTERS ‘The 8086 BIU sends out 20-bit addresses, so it can ad¢ any of 2® or 1,048,576 bytes in memory. However any given time the 8086 work (64-Kbyte) segments within 18,576-byte (1-Mbyte) range. Four segment registers in the BIU are used to hold the ‘upper 16 bits of the starting addresses of four memory seg- ments that the 8086 is working with at a particular time. The four segment registers are the code segment (CS) register, the stack segment (SS) register, the exira segment (ES) register, and the data segment (DS) register. Figure 2.12 shows how these four segments might be positioned in memory ata given time. The four segments can be separated as shown, or, for small programs which do not ce all 64 Koes in each segment, they can overlap, fo répeat, then, a segment rej Sc nat ts used to hold the The code segment rej bits of the starting of hich the BIU is currently fetching instruction code always inserts zeros for the low Boe but the segment wil the lowest 4 bits. segments so that 16-bit numbers when working with the stating address of « segment. The part of a segment starting address stored in a segment register is often called the segment base. ways stat at an address with zeros ig constraint was put on the location of nly necessary to store and manipulate + HIGHEST ADDREg <— TOP OF EXTRA se; <— ExTRAsecm ES= 7oo0n NT BASE <— TOP OF STACK Segue <— STACK SEGMENT Base ‘SS = 5000H ‘TOP OF CODE SEGMENT Bn Eeeerr | Fig.2.12 One way four 64-Kbyte segments might be posta! within the 1-Mbyte address space of an 8086. A stack is a section of memory set aside to store add and data while a subprogram executes. The stack #99 register is used to hold the upper 16 bits ofthe stating = for the program stack. We will discuss the use and 7=™ ofa stack in detail later. The extra segment register and the data segment are used to hold the upper 16 bits ofthe staring 5S ‘wo memory segments that are used for data. INSTRUCTION POINTER The next feature to . i . Took at in the BIU is e Pointer (IP) register. As discussed previously, Be ote wnt register holds the upper 16 bits of the ss int the ins2085 and 6086 Microprocessor Architectures RIRBREIGES ‘The actual physical address sent to memory is produced by it jined in the IP register to the segment ‘upper 16 bits in the CS register. Any time the 8086 accesses memory, the BIU produces the required 20-bit physical address by adding an offset to a seg ment base value represented by the contents of one of the seg- ‘ment registers. As another example of ths, let's look at how the ‘8086 uses the contents of the stack segment register and the con- tents of the stack pointer register to produce a physical address. ple of this, the address constructed in the preceding paragraph, 38AB4H, can also be represented as 348A:4214. ‘To summarize, then, the CS register contains the upper 16 bits of the starting address ofthe code segmentin the I-Mbyte produced by adding the contents of the stack pointer register address range of the 8086. The instruction pointer register resented by the upper 16 bits contains 2 16-bit offset which tells, where in that 64-Kbyte of the base address in SS. Fig. 2.14 shows an example. The ‘code segment the next instruction byte is to be fetched from. 5O00H in SS represents a segment base address of 50000H. 2 + TF e 213 Addition of ta CS to produce the physical address of |" Fig.214 _Ackition of SS and SP to produce the physical ‘code byte, (a) Diagram, (b) Computation. * of the top of the stack. (a) Diagram, (b) Computation. @00 REDMI/NOTE 101] TAMA{QESIRAART Microprocessors and Interfacing 1¢ SP ix added the stack will be rasa single number, FFEOH in thi ‘address forthe top © .ddress can be represented POINTER AND INDEX REGISTERS IN THE EXECUTION UNIT In addition to the stack inter (BP) re ter (SP), the EU contains register. These three registers age of data just as the gener above. However, their main use is to ‘of a data word in one of the segments. be used to hold the offset of a data word in the data segment. in memory will be general address represented by the ‘Afier we give you an overy ‘guages used to program a some examples of how we Programming Languages ‘Now that you have an overview of the 8086 CPU, start thinking about how it is programmed. To run. a microcomputer must have the program store form in successive memory locations, as shown ‘There are three language le that can be used to program for a microcomputer. MACHINE LANGUAGE You can write programs as simply a sequence of the binary codes for the instructions you want the microcomputer to execute, This binary form of the program is referred to as 2 Fig. 215 ‘Assembly language program statement format, ra CPU such as the 8086, Also, it is very easy for ‘error to occur when working with long series of I's and gs ‘xadecimal representation for the binary codes mig! 1 there are sil thousands of instruction cag ASSEMBLY LANGUAGE To make programming casier, many programmers programs in assembly language. They then translate assembly language program to machine language so .ded into memory and run, Assembly languag smonics 10 Tepresen is just a device to hel in an assembly or a shortened form fec-, or four-letter m ‘guage mnemonic are usual English word(s) for \e opers ¢ mnemonic for subtract is first field in an asser ‘A label is a symbol or group of symbols used. to represent ‘an address which is not specifically known at the time the Labels are usually followed by a colon they are just inserted later many uses of where they are needed. We wi labels. ‘The opcode field of the instruction contains the mnestion: for the instruction to be performed. Instruction mnemonics are sometimes called operation codes, ot opcodes. The ADD mnemonic in the example statement in Fig. 2.15 indicates that we want the instruction to do an addition. “The operand field of the statement contains the data, the memory address, the port address, or the name of the regis ter on which the instruction is to be performed. Operand is just another name for the data item(s) acted on by an instruc- tion. In the example instruction in Fig. 2.15, there are two operands, AL and 07H, specified in the operand field. AL represents the AL register, and 07H represents the number 07H. This assembly language statement thus says, “Add the number 07H ‘the AL register." By Intel con- vention, the result of the addition will be put in the register o¢ the memory location specified before the comma in the ope an the example statement in Fig. 2.15, then, the re be left in the AL register, As another example, the assembly language statement ADD BH, AL, when converted to machine language and run, will add the contents of the AL» ‘er to the contents of the BH register, The results will be left in the BH register, an assembly language statems 5 is the commentfield, sich saay occur to you at this point i \guage, how do I get ito machine language which can be loaded into yomputer and executed?” There are two answers question. The first method of doing the translation © work out the binary code for each instruction, a bit at a time using the templates given in the manufacturer's data books. We will show you how to do this in the next chapter, but it is a tedious and error-prone task. The sec- ‘ond method of doing the translation is with an assembler. ‘An assembler is a program which can be run on a personal ‘computer or microcomputer development system. It reads the file of assembly language instructions you write and generates the correct binary code for each. For developing all but the simplest assembly language programs, a bler and other program development tools are essen will introduce you to these program developm the next chapter and describe their use throughout the rest of this book. HIGH-LEVEL LANGUAGES Another way of writing a program for a microcomputer is with a high-level language, such as BASIC, Pascal, or C; guages use program statements which are even like than those of assembly language. Each statement may represent many machine code s. An interpreter program or a compiler program is used to translate higher- level language statements to machine codes which can be loaded into memory and ex« ‘cuted. Programs can usually be written faster in Janguages than in assembly language because a hig cas 8085 and 8086 Microprocessor Architectures rams that involve a lot of hardware co systems, or programs that ye usually best written in data processing programs ive amounts of data, such as insurance rds, are usually best written in a high-level language. The decision conceming which language to use has recently been made more difficult by the fact that cur- rent assemblers allow the use of many high-level language features, and the fact that some current high-level languages provide assembly language features. OUR CHOICE For most ofthis book we work very closely with hardware, 50 assembly language is the best choice. In later chapters, how- ever, we do show you how to write programs which contain we go on to that, however, we will use a few si instructions to show you more about accessing data in regis- ters and memory locations. How the 8086 Accesses Immediate and Register Data Ina previous discussion of the 8086 BIU, we described how the 8086 accesses code bytes using the contents of the CS and. IP registers, We also described how the 8086 accesses the stack using the contents of the SS and SP registers. Before we can” teach you assembly language programming techniques, we: need to discuss some of the different ways in which an'8086 ‘can access the data that it operates on. The different ways in ‘which a processor can access data are referred to as its address- jing modes. In assembly language statements, the addressing ‘mode is indicated in the instruction. We will use the ‘8086 MOV instruction to illustrate some of the 8086 addressing modes. ‘The MOV instruction has the format Ver this instruction copies a word or a MOV Destination, Source specified register or a memory location speci 24 different ways. The source and the destination be memory locations in an instruction.PHYSICAL ‘ADDRESS: MOV CX, AL because operand (AL) into a the low byte of CX, you can use Accessing Data in Memory OVERVIEW OF MEMORY ADDRE BIU 2 FFF: n operand in memoi 24378» seni FA=437AH zoo00n " PHYSICAL ADDRESS 2.164 sho ‘ the data segment bas Y. Fig. 2.166 shows h ctive address, the data segment bay, s of 20000H to produce the physical addnee Sent out ory. The 20-bit physical address sent out (© memory | then be 2437AH. The physical addres cay be represented cither as a single number 2437, ‘Segment base:offsot form as 2000:437AH, 7 END OF DATA SEGMENT 8X REGISTER % MOV BX, 437 Ang + START OF DATA SEGMENT Ds = 2000H os [z cA data segment register and effective Physical address of the data byte, | (b) Computation, s ulates the effective address for an n YOU specify in a number in the \e contents of a Contain 20008, The prt AH oF in the the instruction. instruction as the Specified register asDIRECT ADDRESSING MODE copy “the contents of the memory loca from the data segment base of 437A\ shown by the rightmost arrow in Fi the 20-bit physical memory address by adding the the data segment base, as shown ter we will show you how Another example of the idressing mode is the truction MOV BX, [437AH]. When executed, this copies a 16-bit word from memory into the BX register, ie 8086 will automatically determine the number of bytes tit must access in memory. ‘An important point here is that an 8086 always stores the low byte of a word in the lower of the two addresses and res the high byte of a word in the higher address, To stick is in your mind, remember: byte—Low address, High byte—High address previous two examples showed how the direct address- mode can be used to specify the source of an operand. t addressing can also be used to specify the destination of Contents of BH will be copied to the memory location at a lacement of 437BH. This operation is represented by sim- reversing the direction of the arrows in Fig. 2.16a. NOTE: When you are hand-coding programs using the instruction MOV BX, 437AH. ‘ond instruction will load the immediate number 437AH. 8085 and 8086 Microprocessor Architectures ARAELIG into BX, rather than loading a word from memory at a the next chapter, when you are using ‘an assembler, you usually use a name to represent the direct address rather than the actual numerical value. A FEW WORDS ABOUT SEGMENTATION this point you may be wondering why Intel designed. 8086 far in terface with 8- and 16-bit-wide th the 16-bit registers in the 8086, \n for segmentation has to do with the type’ ly CPUis likely tobe Used. A previous section of this chapter described briefly the ‘operation of a timesharing microcomputer system. In a time- sharing system, several users share a CPU. The CPU works on ‘one user's program for perhaps 20 ms, then works on the next user's program for 20 ms. After working 20 ms for each of the other users, the CPU comes back to the first user’s program again, Each time the CPU switches from one user’s program to the next, it must access a new section of code and new sec- tions of data, Segmentation makes this switching quite easy. | Each user's program can be assigned a separate set of logi- cal segments for its code and data. The user’s program will contain offsets or displacements from these segment bases. To change from one user's program to a second user’s program, at the CPU has to do is to reload the four segment reg the segment base addresses assigned w the second »gram. In other words, segmentation makes it easy to keep users’ programs and data separate from one another, and. segmentation makes it easy to switch from one user’s program to another user's program. In Chapter 16 we tell you much ‘more about the use of segmentation in multiuser systems. Introduction In previous chapters we worked with what i Programmer s model of the 8086. This model Such as internal registers, number of address linSRE2I8S Microprocessors and Interfacing of data lines, and port addresses, which you need to wie programs. Now we will look at the bus signals, timing, BO circuit connections of an 8086 and an 8088. Ina laet Crapo wwe will show the hardware connections for the 80386 microprocessors. System Overview i dias of a simple 8086-based Figure 2.170 shen apm ira cose Took at the general- ized microcomputer in Fig 2.10. Firs, find the 8086 CPU, the ROM, and the RAM in Fig. 2.17a. Next, look for the ports, represented by the block labeled MCS-80 PERIPHERAL. iAs we discuss in detail later, there is a wide variety of port devices available. Some examples are parallel port devices such as the 8255A, serial port devices, special port devices which interface with CRTs, port devices which interface with Keyboards, and port devices which interface with floppy disks. ‘Next, find the control bus, address bus, and data bus in Fig. 2.17. The basic control bus consists of the sig- nals labeled M/O, RD, and WR at the top of the figure. If the 8086 is doing a read from memory or from a port, the RD signal will be asserted. If the 8086 is doing a write chy zea ctoce| to memory or to a port, the WR signal will be During @ read from memory or a write to memge MAO signal will be high, and during port operations theft signal will be low. As we show you in detail later, the Rs 20 and MAO signals are used to enable addressed devices, ” The address bus and the data bus are shown separate} the right side of Fig 2.174, but where they leave the s08¢ 2 two buses are shown as a single bus labeled ADDRDAn The reason for this is that, in order to save pins, the lower bits of addresses are multiplexed on the data bus. Here's overview of how this works. _ As a first step in any operation where it accesses memo, or a por, the 8086 sends out the lower 16 bits of the adds on the data bus. External latches suchas the 74.5373 devices shown in Fig. 2.17a are used to “grab” this adres and hold it during the rest of the operation. To so latches at the proper time, the 8086 outputs a signal cal Address Latch Enable or ALE. Once the address is stored o the outputs of the latches, the 8086 removes the address fron the address/data bus and uses the bus for reading or writin data. Another section of Fig. 2.174 to look at briefly is the bloci labeled 8286 Transceiver. This block represents bidirection three-state buffers. For a very small system, these buffers ar o T t + + 1 EN RT I _t: t t CSO, CSO, WE Oo} e ce cS wom (2142 RAM (4) ‘2716-2 PROM (2) wceae Perea 2 @ shea sxe | Laxie | anne Fig.2.17 (a) Block diagram of a simple 6086-based microcomputer. See also next page)(8085 and 8086 Microprocessor Architectures regmigs (6+ Nand Te 14+ Nae) Te wel me | om | te | wf m [ow [tm | % ax ue \ J \ =—X xX ADONSTATUS YK ie srs 3783 x ADDRATA em ~~ (i500 omnouto1s00 -(X RD neaoy a WTS W,_/ war war oa \, / \ [+—Mewory access THE —l * (ee o Fig.2.17 (continued) (b) Basic 8086 system timing. (Intel Corporation) not needed, but as more devices are added to a system, they become necessary. Here’s why. Most of the devices—such as ROMs, RAMs, and ports— connected on microprocessor buses have MOS inputs, so on a de basis they don’t require much current. However, each input or output added to the system data bus, for example, acts like a capacitor of a few picofarads connected to ground. In order to change the logic state on these signal lines from low to high, all this added capacitance must be charged. To change the logic state to a low, the capacitance must be discharged. If we connect more than a few devices on the data bus lines, the 8086 outputs cannot supply enough current drive to charge and discharge the circuit capacitance fast enough. Therefore, we add exter- nal high-current drive buffers to do the job. ‘Buffers used on the data bus must be bidirectional because the 8086 sends data out on the data bus and also reads data in on the data bus, The Data Transmit/ Receive signal, DT/R, from the 8086 sets the direction in which data will pass through the buffers, When DT/R is asserted high, the buffers will be set up to transmitdata from the 8086 to ROM, RAM, or ports. When DT/R is asserted low, the buffers will be set up to allow data to come into the 8086 from ROM, RAM, or ports. ‘The buffers used on the data bus must have three-state out- puts so the outputs can be floated when the bus is being used for other operations. For example, you certainly do not want, data bus buffer outputs enabled onto the data bus while the 8086 is putting out the lower 16 bits of an address on these lines. The 8086 asserts the DFN signal to enable the three~ state outputs on data bus buffers at the appropriate time in an, operation. = ‘The final section of Fig. 2.17 to look at is the 8284A clock generator in the upper left comer. This device uses a crystal to produce the stable-frequency clock signal which. steps the 8086 through execution of its instructions in an orderly manner. The 8284A also synchronizes the RESET. signal and the READY signal with the clock so that these signals are applied to the 8086 at the proper times. When theURAL Microprocessors and Interfacing ed, the 8086 goes to address FFFFOH es eae truction of the system its next instruction. The first instr a aes is usually Tocated at this adres, s0 e387 tis signal tart, the system. ing this signal is a way to boot, or start, ‘ discuss the use ofthe READY input inthe next section, com Now that you have an overview ofthe basic system con nections for an 8086 microcomputer, let's take a look atthe signal present on the buses as an 8086 reads data from mem ory or from a port, 8086 Bus Activities During a Read Machine Cycle Figure. 2.178 shows the signal activities on the 8086 micro- computer buses during simple read and write operations. Don’t be overwhelmed by all the lines on this diagram. Their meanings should become clear to you as we work through the diagram. ‘The fit line to lok a in Fig. 2.176 is the clock wave- form, CLK, at the top. This represents the crystal-controlled clock signal sent to the 8086 from an extemal clock genera~ tor device such as the 8284 shown in the top left comer of Fig. 2.17, One cycle of this clock is called a state. For refer- ence purposes, a state is measured from the falling edge of one clock pulse to the falling edge of the next clock pulse. ‘The time interval labeled T, in the figure is an example of a state, Different versions of the 8086 have maximum clock frequencies of between 5 MHz and 10 MHz, so the minimum time for one state will be between 100 and 200 ns, depending ‘on the part used and the crystal used, A basic microprocessor operation such as reading a byte from memory or writing a byte to a port is called a machine oyele. The times labeled Tey in Fig. 2.176 are examples of machine cycles. As you can see in the figure, a machine cycle consists of several states. The time a microprocessor requires to fetch and execute {an entire instruction is referred to as an instruction cycle. An instruction cycle consists of one or more machine cycles, To summarize this, an instruction cycle is made up of machine cycles, and a machine cycle is made up of states, The time fora state is determined by the frequency of the clock sig nal. In this section, we will discuss the activities that occur on the 8086 microcomputer buses during a read machine cycle, ‘The best way to analyze a timing diagram such as the one in Fig. 2.17b is to think of time as a vertical line moving from left to right across the diagram. With this technique, you can easily see the sequence of activities on the signal lines as you move your imaginary time line across the waveforms. During T,, of a read machine cycle the 8086 first asserts the M/IO signal. It will assert this signal high if tis going to do a read from memory during this cycle, and it will assert MAIO low if itis going to do a read from a port during this cycle. The timing diagram in Fig. 2.17b shows two crossed waveforms for the M/IO signal because the signal may be ing low or going high for a read cycle. The pointy Bei orem eross indicates the time at which thet! Becomes valid for this machine cycle. Likewise gyi of th timing diagram, crossed lines are used to rep’ time when information on_a lin or group of ines ica After asserting M/IO, the 8086 sends out a high Address Latch Enable signal (ALE). This signa) nected t0 the enable input (STB) of the 743373 a latches, as shown in Fig. 2.174, 50 these latch ™ bee enabled when ALE is high. As you can also qq Fig. 2.17a, the data inputs of these laches are cone 8086 ADO-ADI5, AI6-A19, and Bus High pri (BHE) lines, After the 8086 asserts ALE high, it sendy out these lines the address of the memory location that it ws to read. Since the latches are enabled by ALE being this address information passes through the latches t outputs. The 8086 then makes the ALE output low, wi disables the latches. The address held on the latch ou travels along the address bus to memory and port device Note in the timing diagram in Fig. 2.17 how the at on the ADDR/DATA lines is represented, The fist poin, which the two waveforms cross represents the time at whi the 8086 has put a valid address on these lines. These t waveforms do not indicate that all 16 lines are going high going low at this point. After ALE goes low, the address information is held ont latches, so the 8086 no longer needs to send out the addresse Therefore, as shown by a dashed line on the ADDR/DAT, line in Fig. 2.178, the 8086 floats the ADO-ADIS lines s that they can be used to input data from memory or from Port, At about the same time, the 8086 also removes the BH and A16-A19 information from the upper lines and sends o some status information on those lines. The 8086 is now ready to read data from the address memory location or port, so near the end of state T, the 808 asserts its RD signal low. If you trace the connection of th RD signal in Fig. 2.174, you should see that this signal i used to enable the addressed :nemory device or port device When enabled, the addressed device will put a byte or word of data on the data bus. In other words, asserting the RD sig- nal low causes the addressed device to put data on the dat bus. This cause-and-effect relationship is shown on the tim ing diagram in Fig. 2.176 by an arrow going from the fallin ‘edge of RD to the “bus reserved for data in” section of the ADDR/DATA waveforms. The bubble on the tail of the arrow is always put on the signal transition or level that causes some action, and the point of the arrow always indicates the action caused. Arrows of this sort are only used to show the effect a signal from one device will have on another device. They are not usually used to indicate signal cause and effect within a device, Now, referring to Fig. 2.176 again, find the section of the ADO-ADIS waveform marked off as memory access time near the bottom of the diagram. This time represents the timeit takes for the memory to output valid data after it receives ‘an address and an RD signal. Ifthe access time for a memory “device is too long, the memory will not have valid data on its outputs soon enough in the machine cycle for the 8086 to Teceive it correctly. The 8086 will then treat whatever gar- ‘age happens to be on the data bus as valid data and go on with the next machine cycle. As Jong as Murphy’s law is still ‘in force, the garbage read in will probably cause the entire ‘Program to crash. A section later in the chapter shows you hhow to calculate whether a particular ROM, RAM, or port device has a short-enough access time to work properly in a given 8086 system, For now, however, we just need you to understand the concept so we can show you one way that an 8086 can accommodate a slow device. _ Torefresh your memory, look again at the block diagram in Fig. 2.17 to find an input on the 8086 CPU labeled READY. _ When this pin is high, the 8086 is “ready” and operates nor- mally. If the READY input is made low at the right time in a ‘machine cycle, the 8086 will insert one or more WAIT states between T, and T, in that machine cycle. The read timing dia- "gram in Fig. 2.176 shows an example of this. An extemal "hardware device is set up to pulse READY low before the rising edge of the clock in T. After the 8086 finishes T, of the machine cycle, it enters a WAIT state. During a WAIT state, the signals on the buses remain the same as they were at the start of the WAIT state. The address of the addressed memory location is held-on the output of the latches, so it does not change, and as you can see from the timing diagram in Fig. 2.176, the control bus signals, M/IO and RD, also do "not change during the WAIT state, Twarr. The memory or port device then has at least one more clock cycle to get its data "output, If the READY input is made high again during T, or "during the WAIT state, as shown in Fig. 2.176, then after one | WAIT state the 8086 will go on with the regular T, of the machine cycle. Ifthe 8086 READY input is still low at the end of a WAIT state, then the 8086 will insert another WAIT state. The 8086 will continue inserting WAIT states until the READY input is made high again. To summarize, inserting the WAIT state(s) freezes the action on the buses. This gives the addressed device one or ‘more extra clock cycles to put out valid data. As an example of how this is used, we can use slower (cheaper) ROM in 2 system by adding a simple circuit which pulses the READY ‘input low each time the ROM is addressed. No WAIT states will be inserted in the read machine cycle for reading data from faster devices such as the RAM in the system. ‘Note in Fig. 2.174 that a READY input signal is usually passed through the 8284A clock generator IC so that the READY signal actually applied to the 8086 is synchronized with the system clock. — Now let us look back at Fig. 2.17b to sce how DEN and -DT/R function during a read machine cycle. During T, of the machine cycle the 8086 asserts DT/R. low to put the data ‘8085 and 8086 Microprocessor Architectures {2221 buffers in the receive mode. Then, after the 8086 finishes using the data bus to send out the lower 16 address bits, it asserts DEN low to enable the data bus buffers. The data put on the data bus by an addressed port or memory will then be able to come in through the buffers to the 8086 on the data bus. The activities on the 8086 buses during a read machine cycle can be summarized as follows. The 8086 asserts M/IO high ifthe read is to be from memory and asserts M/1O low if the read is going to be from a port. ‘At about the same time, the 8086 asserts ALE high to enable the external address latches. Itthen sends out BHE and the desired address on the ADO-A19 lines. When the 8086 pulls the ALE line low, the address information is latched on the outputs of the external latches. After the 8086 is through using the ADO-ADIS lines for an address, it removes the address from these lines and puts the lines in the input mode (floats them). The 8086 then asserts its RD signal low. The RD signal going low tums on the addressed memory or port, which then outputs the desired data on the data bus. To com- plete the cycle, the 8086 brings the RD line high again. This causes the addressed memory or port to float its outputs on the data bus. Ifthe 8086 READY input is made low before or during T, ofa mtachine cycle, the 8086 will insert WAIT states, as long as the READY input is low. When READY is made high, the 8086 will continue with T, of the machine cycle. WAIT states can be used to give slow devices additional time to put out valid data. Ifa system is large enough to need data bus buffers, then the 8086 DT/R signal connected to these buffers will set them for input during a read operation or set them for output during a write operation. The 8086 DNE signal will enable the buffers at the appropriate time in the machine cycle. 8086 Bus Activities During aWrite Bi Machine Cycle tae Now that we have analyzed the 8086 bus activities: for ‘a read machine cycle, let’s take a look at the timing dia- ‘gram for a write machine cycle in the right-hand side of Fig. 2.17. Most of this diagram should look very familiar to {you because itis very similar to that for aread cycle. = __ During T, of a write machine cycle the 8086 asserts MIO low if the write is going to be to a por, and it asserts M/IO high if the write is going to be to memory. At about the same time, the 8086 raises ALE high to enable the address latches."The £8086 then outputs BHE and the adress that it will be witing to ‘on ADO-A1S. Incidentally, when writing to a part; lines A16— ‘A19 will always be low, because the 8086 only sends out 16-bit port addresses. After the address has had time to pass through the latches, the 8086 brings ALE low again to latch the address ‘onthe outputs of the latches. Besides holding the address, these latches also function as buffers for the address lines. After the address information is latched, the 8086 removes the addressMicroprocessors and interfacing information from ADO-AD15 and outputs the desired data on the data bus. Itthen asserts its WR signal low. The WR signal is used to tum on the memory or port that the data is to be written to, After the addressed memory or port has had time to accept the data from the data bus, the 8086 raises the WR signal line high again and floats the data bus. If the memory or port device cannot accept the data word within a normal machine cycle, extemal hardware can be set up to pulse the READY input low each time that memory or a port device is addressed. If the READY input is pulsed low before or during T, of the machine cycle, the 8086 will insert a WAIT state after state T,. Remember that during WAIT states the signals on the data bus, address bus, and control bus are held constant, so the addressed device has one or more extra clock cycles to accept the data from the data bus. If the READY! input is made high before the end of the WAIT state, the 8086 will go on with state T, as soon as it finishes the WAIT state. Ifthe READY input is still low just before the end of the WAIT state, the 8086 will insert another WAIT state. It will continue to insert WAIT states until READY is made high. The point here is that the 8086 can be forced to insert as many WAIT states as are necessary for the addressed device to accept the data. Ifthe system is large enough to need buffers on the data bus, then DT/R will be connected to the direction input on the buf- fers. During a write cycle, the 8086 asserts DT/R high to put the buffers in the transmit mode. When the 8086 asserts DEN. low to enable the buffers, data output from the 8086 will pass through the buffers to the addressed port or memory location. Work your way across the timing diagrams for the read and write machine cycles in Fig. 2.176 until you feel that you understand the sequence of activities that occurs. Checklist of Important Terms and Concepts ee a in This Chapter 8085 microprocessor architecture TRAP, RST, INTR Accumilator, flag register, GPRS Interrupt controller Machines cycles 8086 architecture Minimum mode, maximum mode Segmentation Bus Interface Unit (BIU) Instruction byte queue, pipelining, ES, CS, SS, DS registers, IP register Execution Unit (EU) AX, B, eae ee FU) AX, BX, CK, DX, registers, SP Machine Language, assembly language Mnemonic, opcode, operand, label, ie Memon »perand, label, complier, cross Review Questions @ and Problems — #1, What is the reason for giving either manyay ‘ power-on RESET to a digital system? , What factors should you consider to estimate y interrupt response time in 8085 microprocessy #3, Doyou really feel $O and S! are required to deg, an 8085 based computer system and in what ye can you use them? . Can you give one application where you can y, SID and SOD pins in 8085? +5, To what use are the signals S0/, S!/, S2/ put 8086? #6. Describe the sequence of signals that occurs g the address bus, the control bus, and the da bus when a simple microcomputer fetches a instruction. *7. What determines whether a microprocessor | considered an 8-bit, a 16-bit, or a 32-bit device? 8. (a) How many address lines does an 8086 have? (b) How many memory addresses does this num ber of address lines allow the 8086 to acces directly? (c) At any given time, the 8086 works with fou segments in this address space. How man) bytes are contained in each segment? +9, Whats the main difference between the 8086 an the 80887 (a) Describe the function of the 8086 queue. (b) How does the queue speed up processing? (@) If the code segment for an 8086 progran starts at address 70400H, what number wil be in the CS register? (b) Assuming this same code segment base, wha physical address :vill a code byte be fetched from ifthe instruction pointer contains S39CH? ***12. What physical address is represented by? (a) 4370:561EH (b) 7A32:0028H *°13. Whatis the advantage of using a CPU register fortem Porary data storage over using a memory location? "14, If the stack segment register contains 3000H and the stack pointer register contains 8434H, Whatis the physical address of the tip of the stack? “15. (a) What is the advantage of using assembly lan- guage instead of writing a program directly in machine language? (b) Describe the operation an 8086 will perform when it executes ADD AX, BX. “**16. What type of programs are usually written it assembly language? “2, "10. “11,