International Conference on Sustainable Computing in Science, Technology & Management (SUSCOM-2019)

A High Accuracy Sample and Hold Circuit with Reduced Non- Linearity
Errors for SAR ADC in 45nm CMOS process

Silpa Kesav Velagaletia, Nayanathara K.Sb, Madhavi B.Kc*

a,b
JNTUH, CVR College of Engineering,Hyderabad, India,
c
JNTUH, Sridevi Women’s Engineering College,Hyderabad,India.

ARTICLE INFO ABSTRACT

Article history: This manuscript presents a novel Sample and Hold circuit with reduced charge injection, clock feedthrough
Received 11 January 19 and coupling effects. Designing of a clock booster is an important attribute in the proposed bootstrap circuit.
Received in revised form 29 January 19 The Non-ideal effects of switches are Charge injection, Clock feed through and Coupling effect. These Non-
Accepted 23 February 19 ideal effects have been reduced by using a dummy switch and transmission gate methods. The Coupling
effect has been greatly reduced and improved the accuracy of the Sample and Hold circuit by using full
differential architecture. This Sample and Hold circuit is designed in the 45nm CMOS process which
Keywords:
operates at 1.1V of supply voltage. The experimental outcomes show that the Sample and Hold circuit
Clock feed through, Charge injection,
reaches the Effective Number of Bits (ENOB) greater than 12 bits, Spurious Free Dynamic Range (SFDR)
Coupling effect, Clock booster, Sample
of 62 dB and Signal to Noise Ratio (SNR) of 64.7 dB for a 13KHz input signal frequency through 200KS/s
and Hold.
sampling rate which consumes 7.18μW of power. The total harmonic distortion of the proposed Sample and
Hold circuit is 0.248%.
© 2019SUSCOM. Hosting by Elsevier SSRN. All rights reserved.
Peer review under responsibility of International Conference on Sustainable Computing in Science, Technology and Management.

1. Introduction

The greater part of the Analog to Digital Converters and Switched Capacitor filters assumes a crucial job in accomplishing high linearity, high exactness
and a low power scattering at low supply voltages. Most genuine elements influencing the execution of an exceptionally precise Sample and Hold circuit
are charge injection, clock feed through and coupling effects. A few strategies have been proposed to defeat the previously mentioned issues. A standout
amongst the most broadly utilized is the dummy switch and second strategy is replacing a CMOS transmission gate (TG) across the sampling capacitor. The
Coupling effect emerges when the bootstrapped switch (Luh, Chroma, & Draper, 2000) (Sheu, Shieh, & Patil, 1947) is in the off state. The coupling effect
debases the high frequency performance. Different strategies have limited input bandwidth and Output voltage swing. All the above strategies speak to a
tradeoff concerning ENOB, SINAD, SNR, SFDR and Power consumption. To beat these impediments, a novel bootstrap circuit with clock booster and
dummy switch has been proposed.
The association of this paper is as per the following. Section 1 introduces about operation and impediments of Sample and Hold Circuit. Section 2 depicts
the Nonlinear effects of switches. Section 3 portrays the operation of the clock booster and bootstrap circuit. Section 4 describes about the proposed bootstrap
circuit with clock booster and using dummy switch, transmission gate. Also, this session portrays the Fully differential bootstrap circuit with diminished
coupling effects. Section 5 portrays the Experimental outcomes. Conclusions are given in Section 6. Future scope is given in Secion.7.

2. Non-Ideal Effects of Switches

The essential module of any mixed signal circuit is the switch. A critical characteristic of the CMOS switch (Steensguard, 1999) (Abo, 1999) (Razavi, 2000)
is that below the threshold voltage the MOSFET will be in OFF state and no current flows through the channel. MOS switches offers considerable advantages
with a few degradations. There are three non-ideal effects associated with these switches which reduces the usage of MOSFETS in Sampled data circuits.
These three impacts are charge injection, clock feedthrough and coupling effect. This section explains about the Non- Ideal Effects of Switches.

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2.1. Charge injection

Charge injection (Wegmann, Vittoz, Rahali, 1987) (Jacob Baker, 1997) idea will remain comprehended by utilizing basic NMOS Switch as appeared as
follows. Consider the NMOSFET, this MOSFET will be on when applied positive gate voltage superior than threshold voltage, then the drain to source
voltage 𝑉𝑑𝑠 is small, at that point the charge induced in the channel is 𝑄′𝑐ℎ .When the MOSFET goes off, then half of the charge will be distributed equally
onto the load capacitor 𝐶𝑙𝑜𝑎𝑑 and the remaining half of the charge will be induced into Vin. The injected charge towards Vin has no impact, in view of low
input impedance. The charge injected into the load capacitor does the change in voltage across the switch.
The measure of the charge of an inverted channel is shown in equation (1)
Q′ch = Cox (VGS − VTHN )WL (1)
The change in Voltage across 𝐶𝑙𝑜𝑎𝑑 is shown in equation (2)

Figure.1 Illustration of Charge injection

VGS − VTHN
∆Vload = −Cox. W. L. (2)
2Cload
This equation can be written as shown in equation (3)
VDD − Vin − VTHN
∆Vload = −Cox . W. L. (3)
2Cload
Substitute, the threshold Vth then ∆𝑉𝑙𝑜𝑎𝑑 is shown in the equation (4)

∆Vload = Cox. W. L(VDD − Vin − [VTHN0 + γ(√2∅F + Vin − Vss ) − √2∅F )])/2Cload (4)

From this equation the change in voltage across 𝐶𝑙𝑜𝑎𝑑 is nonlinear.

2.2. Capacitive feedthrough

Capacitive feedthrough is clarified using the clock signal. When the clock ∅ is high then the NMOSFET turns on, at that point the input voltage will be
available at the 𝑉𝑜𝑢𝑡 then the capacitor 𝐶𝑙𝑜𝑎𝑑 will be charged through the MOSFET. The outcome of 𝐶𝑙𝑜𝑎𝑑 is charged to Vin and the MOSFET has no effect
of Capacitive feedthrough. Presently when the clock ∅ is low then the NMOSFET turns off, at that point the charge sharing arises between input capacitance
to load capacitance 𝐶𝑙𝑜𝑎𝑑 .

Figure2. Illustration of Capacitive feedthrough

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The percentage of the clock signal ∅ seems through 𝐶𝑙𝑜𝑎𝑑 as

𝐶𝑜𝑣𝑒𝑟𝑙𝑎𝑝 (𝑉𝐷𝐷 − 𝑉𝑆𝑆 )

∆𝑉𝑙𝑜𝑎𝑑 = (5)
𝐶𝑜𝑣𝑒𝑟𝑙𝑎𝑝 + 𝐶𝑙𝑜𝑎𝑑

Where 𝐶𝑜𝑣𝑒𝑟𝑙𝑎𝑝 is the overlap capacitance value, 𝐶𝑜𝑣𝑒𝑟𝑙𝑎𝑝 = 𝐶𝑜𝑥 . 𝑊. 𝐿. 𝐷. LD is the length of the channel that overlays between the drain and source.
From the above two equations, the change in voltage across 𝐶𝑙𝑜𝑎𝑑 is nonlinear. In this way, in view of these impediments mixed signal circuits face nonlinear
errors.

2.3. Coupling Effect

The bootstrap switch gate terminal should always have connected to supply voltage. Because of this condition the switch will be always on and the “ON”
resistance will be very low, thus improves the switch linearity. Once the bootstrap switch is in the off state then coupling effect (Chun-Cheng, Soon-Jyh,
Guan-Ying, 2010) arises. When the switch is in “OFF” state, the input signals will be connected to output through the sampling and parasitic capacitances.
This type of effect called as the coupling effect. This coupling effects degrades the high frequency of the operation and may cause dynamic offset. To avoid
this coupling effects two capacitors of value 5fF connected from input to output and two capacitors of value 2.5fF connected diagonally from input to output.
These non-linear effects can be avoided by using proposed bootstrap circuits as shown in the next sessions.

3. Low voltage CMOS Switch

The vital attribute of MOSFET is that it acts as a dynamic (Analog or Digital) Switch. The MOS transistors are extensively utilized in Switched capacitor
filters (Chung-Yu, Wei-Shinnwey, Tasi-Chung, 1995) and sampled data converters like A/D and D/A converters, etc. In any sort of MOSFET (NMOS or
PMOS) are going to be having four types of terminals. They are source, drain, gate and bulk/substrate. Out of four terminal’s gate control and substrate are
utilized to regulate the conductivity of MOSFET. At that point when the MOSFET is on, it turns as permanent lined conductance gds.

Figure.3 CMOS switch On-state conductance versus input signal voltage: (a) For the small supply voltage (b) For a tremendously small supply
voltage

The CMOS switch On-state conductance versus the supply voltage is shown in Figure.3. The above Figure.3(a) demonstrates that source power Vdd is
superior than the addition of the threshold voltages Vthn and Vthp . At the massive supply voltage, it’s simple to attain enormous conductance from the peak
to peak Vin. Wherever the supply voltage is equivalent to the addition of the threshold voltages, the considerable reduction in the conductance, when Vin
reaches Vdd ⁄2. No switch conducts when the supply voltage is less than a critical value Vdd,crit as shown in Fig.3(b). The critical value is Vdd,crit = Vth,n +
Vth,p . The switch conductivity hangs on all the terminals. The conductance of the switch isn’t constant. It hangs on the available main source voltage also.
So, to regulate the output swing with less supply voltages, signals beyond the supply voltage scale is desirable. This kind of application can be achieved by
using the clock booster. During this session description of the bootstrap circuit and clock booster is explained.

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3.1. Clock booster operation

The pictorial figure of the bootstrapped switch is shown below. It has mainly three elements. They are the pass transistor, the Control signal generator and
clock booster. The main aim of the clock booster circuit (Palmisano, Palumbo, 1997) is to produce a voltage more than the main voltage. Figure.5 shows
the diagram of the clock booster. Once the input clock signal Q is extreme, Q b is small, and Q d is extreme then MOSFET NM0 will be switched on and the
voltage at the node a is ground voltage and the MOSFET NM1 gate is connected to supply voltage. So NM1 is always on, then ground voltage will appear
at Q2. Now the Q2 node related to gate control of PM2 and PM0 are connected to low voltage.

Figure.4 Block diagram of the Bootstrap switch

So PM0 and PM1 are pre-charged to Vdd . When the clock signal Q is low, then MOSFET PM0 is boosted to Vdd , while the MOSFET PM1 is at Vdd −
Vth,p ,the capacitors C1 and C2 charges to Vdd . The MOSFET PM2 is used to keep the gate to drain voltage of MOSFET PM3 to less value and is imperilled
to a greatest source to gate voltage of 𝑉𝑑𝑑 + 𝑉𝑡ℎ,𝑝 . The output voltage of the clock booster is 1.89V as shown in Figure.6.

Figure.5 Schematic of Clock Booster Circuit Figure.6 Waveform of the Clock booster

3.2. Bootstrap switch operation

The actual bootstrap circuit is shown in Figure.7. Constant conductance is required in any front-end circuit of ADC. To accomplish this requirement bootstrap
circuit (Yuxiao, Zhe, Jianjun, 2013) (Bai-Sun, Dong-Oh, Young-Hyun, 1999) (Eichenberger, Guggenbuhl, 1990) is necessary. The bootstrap circuit is used
to generate output voltage linearly dependent to input signal. Generally, the bootstrap circuit operates on a clock signal. This clock is used to make the
bootstrap switch (NM4) ON and OFF. Once the Clk signal is in low state, Clkb will be in high state, then NM5 is on and NM6 is usually on, because the
gate control of NM6 is always connected to supply voltage and the MOSFET’s NM6 and NM5 are used to release the gate voltage of MOSFET NM4 to the
ground potential. When the Clkb is high, NM1 is on, the availability voltage Vdd is stored with in the Capacitor C by PM1 and NM1. So, the bottom plate
of the capacitor is at Vdd by PM1. During the “on” phase the capacitor C act as the storage capacitor between the gate and source of NM4.
When the capacitor C is charging the MOSFET’s PM2 and NM3 are used to isolate the capacitor C from NM4. When the Clk is in high state then the
MOSFET NM0 is used to pull down the gate voltage of PM2, therefore PM2 will be on at the lower potential. Then the MOSFET PM2 is used to allow the

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stored charge in the capacitor C to flow into the gate of the MOSFET NM4. During this time, the MOSFET NM3 is used to keep the gate voltage of NM4
at Vdd by making the Vgs of NM4 as constant irrespective of input voltage of the bootstrap circuit. During this time when the input voltage of the bootstrap
switch is at supply voltage Vdd then the gate voltage will be at 2Vdd.

Figure7. Schematic of Bootstrap Circuit Figure.8 Waveform of the Bootstrap circuit

In this circuit latch up is repressed because PM2 body is tangled to the source terminal internally. The MOSFET NM6 reduces the Vds and Vgd of
MOSFET NM5 once Clk is low. The punch through voltage can be improved by increasing the channel length of MOSFET NM6. MOSFET NM2 makes
sure that Vgs of PM2 doesn’t exceed Vdd . The bootstrap circuit waveform is shown in Figure.8. To supply more charge on the gate terminal of the MOSFET
NM4, the size of the capacitor has been increased to 5fF. This bootstrap circuit was designed in 45nm CMOS technology; therefore, the capacitor value was
maximum 5fF. Because of this capacitance value in this circuit, the linearity problem might arise and reduce the voltage. These problems can be avoided by
using the proposed bootstrap circuit in the next session.

4. The Proposed bootstrap circuit

There are three main errors arises in the bootstrap circuit and they are i) Charge injection ii) Clock feedthrough iii) Coupling effects. To overcome these
errors, this paper proposes two methods. They are bootstrap circuit using transmission gate and bootstrap circuit with a dummy switch. Figure.9 shows the
proposed bootstrap circuit using the transmission gate. The Figure.10 shows proposed bootstrap circuit using a dummy switch.

4.1. The Proposed bootstrap circuit using transmission gate

In the Proposed bootstrap circuit transmission gate was connected across capacitor C. The gate terminals are connected to Clk and Clkb respectively. The
MOSFET’s NM7 and PM3 sources are connected to the capacitor C and drains are connected to input of the bootstrap switch as shown in Figure.9.
Transmission gate is used to compensate circuit errors. When the Clkb is high NM1 will be in ON state, the capacitor is connected to the junction terminal
of the transmission gate. Some portion of the stored charge will be discharged through NM1 to the ground, the amplitude swing of output was reduced. So,
this is not a precise architecture for Sample and Hold. So, to overcome this disadvantage a bootstrap circuit with a dummy switch is proposed in section 4.2

4.2. Proposed bootstrap circuit with dummy switch

The recommended design with dummy switch at the output of bootstrap switch as presented in Figure.10. Dummy switch was connected between the
bootstrap switch and output to avoid non-linearity errors. The operation using the dummy switch method (Christian, Mohamad, Gordan, 2006) (Waltari,
Halonen, 1999) is explained below. The MOSFET NM7 with the shorted source and drain is placed in a series with MOSFET NM4. The complemented
clock signal has given as input to the dummy switch. When NM4 goes off half of the channel charge is inserted towards the dummy switch NM7. The
MOSFET NM7 source and drain are shorted. Still channel can be established after applying enough voltage at gate control. So, the charge injected by NM4
will be matched by the charge induced by NM7. Now, if NM7 MOSFET is in the off state, then the total charge will be induced in both the directions. Since
NM7 source and drain are shorted and Vin is a low impedance node, the total charge will be injected into NM4 MOSFET to input voltage Vin. Thus, the non-
linearity errors clock feedthrough and charge injection have been reduced. Figure.11 and Figure.12 shows testbench of the proposed bootstrap circuit with
clock booster and waveform. In this waveform, output wave negative cycle was highly linear because of the clock booster outputs are given as the clock to

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the bootstrap circuit. When the bootstrap circuit was in off state coupling effects may arises. So, to avoid coupling effects Full differential structure (Soliman,
Tasnim , 2015) (Gatti , Maloberti , Palmisano, 1992) was proposed as shown in Figure.13. To avoid coupling effect capacitors with 5fF was connected from
input Vip to 𝑉𝑑𝑎𝑐𝑝 and from Vin to Vdacn , and capacitors with 2.5fF was connected diagonally from Vip to Vdacn and Vin to Vdacp . With this architecture the
coupling effects were greatly reduced. Figure.13 shows the waveform of Differential Sample and Hold circuit with reduced Non-Linearity errors. Figure.14
waveform shows the Comparison of the bootstrap circuit with the clock booster and the proposed bootstrap circuit with a dummy switch. Therefore, the
proposed bootstrap design by using dummy switch full differential structure of sample and hold architecture gives the better result than the conventional
bootstrap circuit.

Figure.9. Proposed bootstrap Circuit-1 Figure.10 Proposed bootstrap Circuit -II with dummy switch

Figure.11 Test bench of the clock booster with the proposed bootstrap circuit

Figure.12 Waveform of the proposed bootstrap circuit with the clock booster

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(a) (b)
Figure. 13 (a) Schematic of Full differential proposed S/H with the reduced Coupling Effect (b) Waveform of Full differential proposed S/H with
reduced non-linearity errors

Figure.14 Comparison waveform of bootstrap, bootstrap with clock booster and with proposed bootstrap with reduced nonlinearity errors

(a) (b)
Figure.15 Power and Delay calculation using cadence calculator for proposed Sample and Hold (a) Power consumption (b) Delay value

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Figure.16 Power spectral density of proposed Sample and Hold

5. Experimental Results

The proposed Full Differential S/H circuit was designed in 45nm CMOS Technology with the power consumption of 7.118E-6 with 1.1V supply voltage.
Figure.15 displays the power and delay values of proposed Sample and Hold circuit. Figure.16 shows the output spectrum was generated with the 200KS/s
sampling rate and 13 KHz analog input using a Coherent sampling calculator method. To assess the non-linearity parameters, power spectral density(PSD)
was generated for 1024(210) sample points. The cycles required are 67 and transient time is 5.115ms. The input sine wave was given as 550mV of offset
voltage and 550mV of amplitude at 13 KHz input frequency. The clock booster generates the clock signals which are connected as input to the bootstrap
circuit. Table.1 displays the functioning constraints of different S/H circuits (Soliman, Tasnim , 2015) and the proposed circuit. Table.2 displays the
functioning constraints of the proposed Full differential bootstrap circuit with input Voltage range is 1.1V p-p and the achieved ENOB, SINAD, SNR and
SFDR are 12.63(bits), 51.98(dB), 64.777(dB) and 60.2(dB) respectively.

Table1 – Functioning constraints of various Sample and Hold Circuits

Type of Sample and Hold ENOB(bits) SINAD(dB) SNR(dB) SFDR(dB) Power

consumption(W)
Basic Sample and Hold 9.9 61.63 61.6 70.37 5.02p

Sample and Hold with a 11.49 48.522 50.29 53.85 3.88p

dummy switch

Differential Sample and 11.6 49.42 49.4 56.4 12.4p

Hold
Transmission gate 11.75 50.03 50 56.16 5.25n

Sample and Hold

Proposed Sample and Hold 12.6 51.98 64.77 60.2 7.118u

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Table2 – Functioning constraints of the proposed Sample and Hold

S. No Parameter Value
1 Sampling rate 200KS/s
2 Input frequency 13KHz

3 Resolution 12.6(bits)

4 Input range 1.1Vp-p

5 Supply voltage 1.1V

6 Power consumption 7.118uW

7 Process 45nm CMOS

8 SINAD 51.98(dB)

9 SNR 64.77(dB)

10 SFDR 60.2(dB)
11 THD 0.248%

6. Conclusion

In this manuscript proposes a full differential Sample and Hold Circuit with the dummy switch was designed with 200KS/s clock frequency in 45nm CMOS
technology with a supply voltage of 1.1V. This design similarly works at an 800mV supply voltage. An interesting attribute of the proposed circuit is the
clock booster. The peak to peak input amplitude flexibility allows to redesign any type of data converters such as Successive approximation, pipeline ADC
and time interleaved ADC. Linearity of the proposed circuit has been increased because of the on-resistance property of the clock booster. Using the dummy
switch in bootstrap circuit clock feedthrough and charge injection got removed and further to decrease the coupling effects, cross coupled capacitance i.e.
Full Differential structure has been designed.

7. Future scope

Designing of the Sample and Hold circuit is the crucial part of the front-end of any ADC like Successive Approximation Register (SAR). This proposed
Sample and Hold circuit consumes more power with the usage of clock booster which effects the overall performance of mixed signal circuits. In future, to
reduce power consumption, power reduction techniques can be adopted to lower the overall power of such circuits.

REFERENCES

Luh, L., Chroma, J., & Draper, J. (2000). A high-speed fully differential current switch, IEEE Trans. Circuits Syst.II, Analog Digit. Signal Process., vol.47,
no.4, pp.358-363.
Sheu, B. J., Shieh, J. H., & Patil, M. (1947). Modelling charge injection in MOS analog switches, IEEE Trans. Circuits Syst., vol.34, no.2, pp.214-216.
Steensguard, J. (1999). Bootstrapped low- analog switches, Proc.IEEE-ISCAS Symposium on Circuit and Systems, VLSI, pp.II 29-32.
Abo, A. M. (1999). Design for Reliability of Low-voltage Switched- capacitor Circuits, Ph.D. Thesis, University of California, Berkeley.
Razavi, B. (2000). Design of Analog CMOS Integrated Circuit, McGraw-Hill.
Wegmann, G., Vittoz, E. A., & Rahali, F. (1987). Charge Injection in Analog MOS Switches, IEEE Journal Of Solid State Circuits,Vol.22. pp.1091-1097.
Jacob Baker, R. (1997). CMOS CIRCUIT DESIGN, LAYOUT AND SIMULATION, Wiley.
Chun-Cheng, Liu, Soon-Jyh, Chang, & Guan-Ying, Haung. (2010). A 10-bit 50MS/s SAR ADC with a Monotonic Capacitor Switching Procedure, IEEE Journal of
Solid State Circuits. Vol.45. pp.731-740.
Chung-Yu, Wu, Wei-Shinnwey, & Tasi-Chung, Yu. (1995). A 1.5V CMOS Balanced Differential Switched capacitor Filter with Internal Clock Boosters,
Proceedings of ISCAS'95 - International Symposium on Circuits and Systems, pp.1025-1028.
Palmisano, G., & Palumbo, G. (1997). Clock boosters for 1.2V SC Circuits, 1997 IEEE International Symposium on Circuits and Systems, pp-2012-2015.
Yuxiao, LU, Zhe, Li, & Jianjun, Zhou. (2013). A full-Swing area-efficient high speed CMOS bootstrapped Sampling Switch, IEICE Electronics Express, vol.10
pp.1- 6.
Bai-Sun, Kong, Dong-Oh, Kang & Young-Hyun, Jun. (1999). A Bootstrapped CMOS Circuit Technique for Low-Voltage Application, ICVC 6th International
conference on VLSI and CAD, pp. 289-292.
Eichenberger, C. & Guggenbuhl, W. (1990). Oncharge injection in analog MOS switches and dummy switch compensation techniques, IEEE Trans. Circuits

February 26 - 28, 2019 | Amity University Rajasthan, Jaipur, India Page 797

Electronic copy available at: https://ssrn.com/abstract=3355133

 International Conference on Sustainable Computing in Science, Technology & Management (SUSCOM-2019)

Syst., vol.37, no.2, pp.256-264.

Christian, J., F., B., Mohamad S., & Gordan, R., W. (2006).Low-Voltage Analog Switch in Deep Submicron CMOS: Design Technique
and Experimental Measurements, IEICE TRANS FUNDAMENTALS, Vol, E89-A, No.4, pp.1076-1087.
Waltari & Halonen, K. (1999). A 220-MS/s CMOS sample-and-hold circuit using double sampling,Analog Integrated Circuits and Signal Processing, vol.18,
pp.21-31.
Soliman, M., A. & Tasnim N., B. (2015). Sample and Hold circuits for Low frequency Signals in Analog to digital Converter, 2015 International
conference on Information and Communication Technology Research(ICTRC), pp.36-39.
Gatti, U., Maloberti, F., & Palmisano, G. (1992).An Accurate CMOS Sample-and-Hold Circuit, IEEE Journal of Solid State Circuits, Vol.29, No.1.pp.120-122.

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