Figure 1 Clocking mechanism for the OOB detect circuit:

Figure 2 showing a simple toggle flip flop (shown below) may be used to divide the refclk. .

.
Figure3 showing how Cascading several divide by two circuits (as shown below) produces higher order clock
dividers such as divide by 4 and divide by 8.

Figure 4 Flowchart to determine whether the RX is in Electrical Idle for the Protocols with linerates
lessthan or equal to 1.5G

For linerate ≤ 1.5Gbps

f ≤ linerate/(3*runlength)

IS RXELECIDLE asserted?
NO

Rx is not in
YES electrical Idle

Rx is in
electrical idle
Figure 5 Flowchart to determine whether the RX is in Electrical Idle for SATA 3G or SATA 6G

SATA 3G or 6G

NO

IS RXELECIDLE asserted?

YES

Is incoming data Rx is not in electrical

YES
Valid? Idle

NO

Rx is in electrical
idle
Figure 6 Flowchart to determine whether the RX is in Electrical Idle for the PCIE gen1

PCIE Gen1

Is Scrambler present? NO
NO

YES

IS RXELECIDLE asserted?
NO

IS RXELECIDLE YES
asserted?

YES Is incoming data Valid?

NO YES
Rx is in
electrical idle

Rx is in Rx is not in
electrical idle electrical Idle
Figure 7 Flowchart to determine whether the RX is in Electrical Idle for the PCIE gen2

PCIE Gen2

NO

IS RXELECIDLE asserted?

YES

Is incoming data Valid? YES Rx is not in electrical Idle

NO

Rx is in electrical
idle
Figure 8 Flowchart for the entry electrical idle for RX for PCIE gen2 or Gen3

PCIE Gen3 or Gen2 Entry

No

Is EIOS detected?

YES
NO

IS RXELECIDLE Detected?

YES

RX is in Electrical
IDLE.

Figure 9 Flowchart for the exit from electrical idle for RX for PCIE gen2 or Gen3

PCIE GEN2 or GEN3 Exit

NO

Is RXELECIDLE deasserted?

NO
YES

Valid EIOS?

YES

RX is out of
Electrical Idle.