CIT309 2023_1 TMA1 9_10

____ is an example of architectural attributes

c.
Number of\\nbit representing various data types

Computer memory is organized into a _________

d.
Hierarchy

An alternative to a hardwired control unit is a ___________in which the logic of

the control unit is specified by a micro program

c.
Micro programmed control unit

_______are arranged in clusters of five, with each cluster\\nsupporting eight

processor chips and providing access to the entire main memory space.

c.
L2 Cache

_______ is the number of bits read out of or written into memory at a time.

c.
Unit of transfer

_______ is a hardware-generated signal to the processor.

b.
Interrupt

Instruction fetch is also known as ____________

a.
Read *

A________is an interconnected set of gates whose output at any time is a function

only of the output at that time

b.
Combinational circuit

________ data may be transferred from processor to memory or from memory to

processor

d.
Processor-memory
If a word is altered in one cache, it could conceivably invalidate a word in
another cache. To prevent this other processessor must be altered that an update
has taken place. This problem is known as:

c.
Cache coherence problem

CIT309 2023_1 TMA2 9_10

If a bits error occurs, the code will detect and usually _______the error

c.
Correct

Error correction technique involves adding redundant bits that are a function of
the _______ to form an error correction code

c.
Data bit

In computer, the way in which the components are interrelated is term

d.
Structure

____ specifies a particular I/O device

b.
I/O address register

____ is used for the exchange of data between an I/O module and the CPU

d.
I/O buffer register

______ can be caused by harsh environmental abuse, manufacturing defects, and wear

_______ is a permanent physical defect such that the memory cell or cells affected
cannot reliably store data but become stuck at 0 or 1 or switch erratically between
0 and 1.

d.
hard failure

A _________ arbitrates system communication and has a central role in maintaining

cache coherence

d.
System control element
A set of interrupt will execute in what order of priority?

c.
Instruction fetch *

Loop unrolling can improve performance by the following except _________

a.
Decreasing parallelism instruction

CIT309 2023_1 TMA3 8_10

The disadvantage of the use of micro-programming to implement a control unit is

______

a.
Address Register

b.
Cheaper *

c.
Slower

d.
Less error prone to implement * TWO ANSWERS

Who first introduced Single instruction, single data (SISD) stream computers?

a.
Flynn

The task of optimizing the generated code to minimize code size, reduce instruction
execution count, and enhance pipelining is much more difficult with _______

c.
Complex instruction set

The CPU register that contains the data to be written into the memory and also
receives the data read from memory is called _________

b.
Memory Buffer Register

The following except _________ are the elements of a machine instruction

b.
All instruction reference

______ is the simple pipeline found in traditional Riand CISC machines, with no
multithreading

b.
Single-threaded scalar

Which of the following processors are more responsive to interrupts?

b.
RISC processor

One of the first commercially available RISC chip sets was developed by

d.
MIPS Technology Inc

Pipelining is a unique feature of which of the following?

a.
RISC

The operating system is a program that manages the computers resources, provides
services for programmer and schedule the execution of the other_______

d.
Programs