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Experiment3 PDF
Experiment3 PDF
Experiment3 PDF
Objective:
• To implement the Nth Fibonacci Generator in Verilog and verify the design
Experimental Procedure:
1. Design a digital block to compute the Nth fiboncacci number (where N is the given
input number). Implement the design in Verilog and develop a simple test bench
to verify the design. Take input N to be 3-bits, allocate sufficient number of bits
for the output. Input and output busues will have qualifiers N valid and Fibo valid
respectively.