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IEP RTL to GDSII

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Contents
1 RTL to GDS flow
1.1 Logic Synthesis
1.2 Logic Equivalence Checking
1.3 Physical Design
1.3.1 Initial Setup
1.3.2 Floorplanning
1.3.3 Power Planning
1.3.4 Placement
1.3.5 Clock Tree Synthesis
1.3.6 Routing
1.3.7 Basic Timing Analysis
1.3.8 Further Steps
1.3.9 Basic Physical Verification
1.3.10 Dumping
1.4 Synthesis to post-PnR LEC
1.5 Acronyms
1.6 Basic vim commands

RTL to GDS flow

This section would cover the basic set of commands and the back-end tool flow required to synthesize the RTL
and then take it through PnR to arrive at a GDS.

Logic Synthesis

Synthesis is the process by which a behavioural RTL code is converted to a structural netlist, with the specified
area, power and performance constraints. The inputs to the synthesis flow are the RTL, the constraints (.sdc file)
and the timing libraries (.lib files). We would be using Cadence RTL Compiler (RC) as our synthesis tool.

Firstly, ensure that you're working in c-shell

tcsh

Copy the working directory from the path provided below

cd ~
scp smart@10.32.33.21:synth_pnr.tar.gz .

Untar the directory and cd into it.

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tar -xzvf synth_pnr.tar.gz

cd synth_pnr

All the required files and directories would now be seen in the required directory structure.

Assignment - Vary the clock period and figure out (approximately) what the maximum synthesis
frequency for the design is. Please keep an uncertainty of 2ns in your runs. Your constraints file is called
constraints.tcl, where the clock definitions would be present.

Next, we have to initialize a few variables related to cadence tools. Run the following command.

source ~/cadence.cshrc

Next, invoke RTL Compiler

rc

Source the following files in the terminal (rc - shell)

rc:/> source setup.g

rc:/> source template.tcl (This is your main synthesis script)

Your design should get synthesized after this step if everything was done right.

To check the timing (setup) status of your design, run the following command

rc:/> report_timing -encounter

You'll find that there are a few directories written out in your work directory. One of them, called
reports_<timestamp>, will have your synthesis reports. You can go through the reports to see a few metrics of
your design, eg timing characteristics, area, power, gate count. Alternately, you can enter commands in the rc
shell after synthesis to view detailed information about your design.

Assignment - Find out the following information about the design:

1. The instance count of the design
2. The standard cell area
3. The percentage of the area occupied by the memories

The directory called outputs_<timestamp>, would have the output files after synthesis.
<your_top_module_name.v> is the synthesized netlist. You should have a look at this file. This is the netlist that
would be taken forward for PnR. This directory would also contain the generated sdc file
"top_chip_wrapper.sdc". It would also contain the lec dofiles which would be needed for running Conformal

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Equivalence Checking.

Finally, close rc
rc:> exit

Logic Equivalence Checking

We would now vectorlessly (ie exhaustively) establish the equivalence between the RTL and the synthesized
netlist. This would establish the correctness of the synthesized design, provided, of course, that the RTL is
golden. The required dofiles are already generated as synthesis outputs. We would have to copy them out one
hierarchy to the main synthesis directory.

Please change outputs_<timestamp> below to your output directory name.

cp -rf outputs_<timestamp>/rtl2intermediate.lec.do .
cp -rf outputs_<timestamp>/intermediate2final.lec.do .

Run LEC by running the following commands

lec -xl -Dofile rtl2intermediate.lec.do

lec -xl -Dofile intermediate2final.lec.do

The LEC logs can be found inside the logs_<timestamp> directory. They would be called
rtl2intermediate.lec.log and intermediate2final.lec.log. You can view the lec result in these log files.

Physical Design

The process of converting a netlist into manufacturable geometrical structures having the desired functionality
and satisfying the various timing and design rule constraints can broadly be called as the activity of physical
design.

For the purposes of this lab, we would go through the very basic vanilla flow to convert our netlist to a GDS.

Physical Design can broadly be divided into the following sub-tasks, which are, in order

Partitioning
Floorplanning
Power Planning
Placement
Clock Tree Synthesis (CTS)
Routing
Physical Verification
Parasitic Extraction and Back Annotation
Timing Analysis & Closure
DFM, DFY and Tapeout

We would go through the tool flow of each of these steps without getting into theoretical details. Physical
Verification, extraction and sign-off timing analysis is beyond the scope of this lab, and might be covered in a
later session.

Initial Setup

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Let's move into the PnR work area

cd ~/synth_pnr
cd pnr_new
ls -ltr

It should already be populated with the required files and directories.

Next, we have to copy our synthesized netlist and constraints file from our synthesis output directory.

Please change outputs_<timestamp> below to your output directory name.

cp -rf ../outputs_<timestamp>/top_chip_wrapper.v .
cp -rf ../outputs_<timestamp>/top_chip_wrapper.sdc .

All required files are now present in your working directory. Before proceeding forward, make the following
changes.

Add the following power pads to the end of your synthesized verilog netlist "top_chip_wrapper.v"

pvdi pvdi_VDD_CORE_1 (.VDD(VDD_CORE), .VSS(VSS_CORE), .VDDO(VDDO_CORE), .VSSO(VSSO_CORE));

pv0i pv0i_VSS_CORE_1 (.VDD(VDD_CORE), .VSS(VSS_CORE), .VDDO(VDDO_CORE), .VSSO(VSSO_CORE));

pvdi pvdi_VDD_VCO_1 (.VDD(VDD_VCO), .VSS(VSS_VCO), .VDDO(VDDO_VCO), .VSSO(VSSO_VCO));

pv0i pv0i_VSS_VCO_1 (.VDD(VDD_VCO), .VSS(VSS_VCO), .VDDO(VDDO_VCO), .VSSO(VSSO_VCO));

pvda pvda_CORE (.VDD(VDD_CORE), .VSS(VSS_CORE), .VDDO(VDDO_CORE), .VSSO(VSSO_CORE));

pv0a pv0a_CORE (.VDD(VDD_CORE), .VSS(VSS_CORE), .VDDO(VDDO_CORE), .VSSO(VSSO_CORE));

pvda pvda_VCO (.VDD(VDD_VCO), .VSS(VSS_VCO), .VDDO(VDDO_VCO), .VSSO(VSSO_VCO));

pv0a pv0a_VCO (.VDD(VDD_VCO), .VSS(VSS_VCO), .VDDO(VDDO_VCO), .VSSO(VSSO_VCO));

Add these before the final endmodule

Assignment

1. Add 2 more power pads for VDD_CORE and VSS_CORE. Hint: The format would be the same as the
first two power pads, but with different names. Name them pvdi_VDD_CORE_2 and pv0i_VSS_CORE_2

2. You now need to add these 2 pads to the IO assignment file called final.io. Open the IO assignment file
and go through the file structure. Figure out which two sides of the chip have 16 pads (the other two have
17) and add your pads to these sides, one each, in the same format as the other pads. Note : Few sides may
have cut cells called cut_*. These do not count as IO pads, so be careful while counting.

We need to make a few more changes to the netlist such that the VCO power domains are correctly specified.

Make the following changes to the top_chip_wrapper.v file

Find the line - pc3d00 pc3d00_1(.PAD (CONTRL_pad), .PADR (CONTRL));

and replace with - pc3d00 pc3d00_1(.PAD (CONTRL_pad), .PADR (CONTRL), .VDD(VDD_VCO), .VSS(VSS_VCO), .VDDO(VDDO_VCO), .VSS

Find the line - pc3d00 pc3d00_2(.PAD (VCTRLn_pad), .PADR (VCTRLn));

and replace with - pc3d00 pc3d00_2(.PAD (VCTRLn_pad), .PADR (VCTRLn), .VDD(VDD_VCO), .VSS(VSS_VCO), .VDDO(VDDO_VCO), .VSS

Find the line - pc3d00 pc3d00_3(.PAD (VCTRLp_pad), .PADR (VCTRLp));

and replace with - pc3d00 pc3d00_3(.PAD (VCTRLp_pad), .PADR (VCTRLp), .VDD(VDD_VCO), .VSS(VSS_VCO), .VDDO(VDDO_VCO), .VSS

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Add the pins .VDDI(VDD_VCO), .GNDI(VSS_VCO) to the VCO module "VCO DUT1". Make sure that you do not make any syntax error

Make the following changes to the top_chip_wrapper.sdc file

Browse to the end of the file and change the setup uncertainty to 0.0 and hold uncertainty to 1.0

Save and close all open files.

Now we are ready to launch our PnR tool, Cadence SoC Encounter.

Invoke encounter

encounter

We first need to load the required files

Go to File -> Import Design

Under the "Verilog" tab, under "Files", enter the name of your netlist, top_chip_wrapper.v (or browse and select the file
Change the "Top Cell" to "Auto assign"

Under the "Technology/Physical Libraries" tab, select "LEF Files"

Browse to the lef directory and add all files.
Important - Make sure you add the technology lef file first - tsl180l4.lef.
Important2 - Add the following lef second - tsl18fs120_scl.lef

Add final.io to the IO Assignment file

Under "Power", enter VDD_CORE as the power net and VSS_CORE as the ground net

Under "Analysis Configuration", add the design.view file in the MMMC View Definition File section.

Click OK

Your Design should get initialized now.

Click on the Floorplan View button, next to online help, on the top right corner of the screen.
Press f to fit everything on screen.

You should now see your initial setup ready with the standard cells shaded on the left of the estimated floorplan,
and the macros on the right.

Floorplanning

Click on Floorplan -> Specify floorplan

Click on Dimension
Specify the dimension as Height = 2300, Width = 2300
Change Core to left, core to right, etc.. (all 4) to 50
Click OK

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You should now see the floorplan with the area assigned for power rings on your screen.

Click on Floorplan -> Auomatic Floorplan -> Plan Design

Go to setPlanDesignMode
Change the effort to high
Click OK
You'll see an auto generated floorplan. Move around the macros if you so wish to.

Create placement blockages around all macros

createPlaceBlockage -allMacro -outerRingByEdge {4 4 4 4} -type hard

Power Planning

Core power planning

Click on Power -> Power planning -> add ring

Under nets, browse and select both VDD_CORE and VSS_CORE, click add, and click OK.
Under "Ring Configuration", change Top and Bottom to M3 H; and Left and Right to TOP_M Vertical
Change width and spacing to 10 under each column.
Under "offset", click on "centre in channel"
Click OK

You should now see the power rings around the core area.

Next, we need to add the power stripes.

Click on Power -> power planning -> add stripe

Select both VDD_CORE and VSS_CORE under nets.
Change the layer to TOP_M, and direction to Vertical.
Change width and spacing to 10
Click OK.

You should now see the vertical metal stripes on your screen.

We now need to provide power to the standard cell rails by creating the M1 rails and dropping vias.

Click on Route -> Special route

Select VDD_CORE and VSS_CORE as nets
Deselect everything except follow_pins.
Click OK

The standard cell rails have now been provided with VDD and VSS.

The Power and Ground connection between custom made macros and pads can be done

Define another power ring around the macro with same net name in which it needs to be connected.
Click on Power -> Power planning -> add ring
Under nets, browse and select both VDD_VCO and VSS_VCO, click add, and click OK.
Under "Ring Configuration", change Top and Bottom to M3 H; and Left and Right to TOP_M Vertical
Change width and spacing to 10 under each column.
Under "offset", click on "specify"
Click OK

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Make sure in the top verilog netlist the power connection to pads and VCO(custom made analog blocks ) is
specified as

pvda pvda_VCO (.VDD(VDD_VCO), .VSS(VSS_VCO), .VDDO(VDDO_VCO), .VSSO(VSSO_VCO));

pv0a pv0a_VCO (.VDD(VDD_VCO), .VSS(VSS_VCO), .VDDO(VDDO_VCO), .VSSO(VSSO_VCO));

Similar way do power and Ground connection to VCO DUT also. Click on Route -> Special route

Select VDD_CORE and VSS_CORE as nets

select Pad pins,Block pins,pad rings.
Click OK

Tool will automatically route the Power connection to analog blocks and pads and pad rings also.

Placement

Click on Place -> Place standard cell

Select "In place optimization"
Click OK

After the placement run is complete, click on Physical View button next to "online help" on the top right corner.

You should now see the standard cells placed in your design.

Clock Tree Synthesis

Click On Clock -> Synthesize clock tree

Click on gen spec, and select all the clock buffers and clock inverters available in the library.
(ie all cells named bufb** and invb**) and click ADD and OK
Click OK

Your clock tree should get synthesized after this step.

Routing

Click on route -> nano route -> route

Click on Insert Diode, and specify ADIODE as the diode name.
Click OK, leaving all other options as default

This should complete a vanilla detailed route run.

Basic Timing Analysis

Timing check - Let us see how our setup checks look.

setDelayCalMode -SIAware false

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Timing -> report timing

Choose post-route under design stage
Choose "setup" under analysis type.
Click OK

Check the reports on the terminal (or detailed reports in your work directory).
Check the setup reports in terms of FEP, WNS and TNS. In case there are any violations, you may run the
following command to make the tool try and optimize the design to fix these violations.

optDesign -incr -postRoute

Timing check - Let us see how our hold checks look.

Timing -> report timing

Choose post-route under design stage
Choose "hold" under analysis type.
Click OK

Check the reports on the terminal (or detailed reports in your work directory).
Check the hold reports in terms of FEP, WNS and TNS. There would most likely be a few hold violations. Use
the following command to fix the violations.

optDesign -incr -postRoute -hold

You might need to run it multiple times to clean all violations, or, you might have to manually fix the violations
(highly unlikely for this design).

Further Steps

Adding filler cells - Any unused area in your floorplan must be filled up with fillers to ensure well continuity
among other things. Do the following to add filler cells

Place -> Physical Cell -> Add filler

Select all available filler cells
Click OK

Adding IO fillers

addIoFiller -cell {pfeed30000 pfeed10000 pfeed02000 pfeed01000 pfeed00540 pfeed00120 pfeed00040 pfeed00010} -prefix FILLE

Basic Physical Verification

Please follow the steps that were discussed in the lecture.

Dumping

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You need to provide logical power connections to all standard cells. You need to run global net connects for this

globalNetConnect VDD_CORE -type pgpin -pin VDD -all

globalNetConnect VSS_CORE -type pgpin -pin VSS -all

To save your post-PnR netlist, do the following

1. With pg pins
saveNetlist -includePowerGround top_chip_wrapper.pnr.pg.v

2. Without pg pins
saveNetlist top_chip_wrapper.pnr.v

To export the GDS, do the following

File -> Save -> GDS/OASIS

Select GDSII as the format
Name the file as top_chip_wrapper.gds
The Map file should be - gds2_fe_4l.map
Click OK

The GDS should get written out in your working directory.

You can try out other options/commands with encounter.

Finally, close encounter

encounter 1> exit

Synthesis to post-PnR LEC

As before, we need to ensure the logical equivalence between the synthesized netlist and the post-PnR netlist.
We'll copy the same dofile generated after synthesis and change appropriate pointers.

cp -rf ../intermediate2final.lec.do .
mv intermediate2final.lec.do synth2postpnr.lec.do

You need to make a few changes to this file

Open synth2postpnr.lec.do
Change line 7 to set log file lec.logs -replace

We need to change the golden and revised netlists. Golden should be the input netlist to the PnR tool and the
Revised netlist should be the non-pg netlist dumped by encounter.

Open synth2postpnr.lec.do
Change lines 34 & 37 to top_chip_wrapper.v
Change lines 46 & 49 to top_chip_wrapper.pnr.v

We need to give the list of LEF files as an input to the tool, as the pin info of the MACROs need to be captured.

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Open synth2postpnr.lec.do
Add these lines after the library files are read in (near line 30)
read lef file -both \
~/synth_pnr/pnr_new/lef/tsl18fs120_scl.lef \
~/synth_pnr/pnr_new/lef/delaycell.lef \
~/synth_pnr/pnr_new/lef/top_4lm.lef \
~/synth_pnr/pnr_new/lef/VCO.lef \
~/synth_pnr/pnr_new/lef/tsl18cio150_4lm.lef \
~/synth_pnr/pnr_new/lef/tsl180l4.lef

Change the library files to the following (lines 24 to 29)

~/synth_pnr/library/tsl18fs120_scl_ss.lib \
~/synth_pnr/library/tsl18cio150_max.lib \
~/synth_pnr/library/pmemss.lib \
~/synth_pnr/library/dmemss.lib \
~/synth_pnr/library/VCOss.lib \
~/synth_pnr/library/Delayss.lib

Delete line 28 which says ~/synth_pnr/library/VCOss.lib \

Finally, run lec

lec -xl -Dofile synth2postpnr.lec.do

The log file lec.log will contain the results.

Acronyms

RTL - Register Transfer Logic

GDS - Graphical Database System
PnR - Place and Route
SDC - Synopsys Design Constraints
lib - Liberty format
RC - Cadence RTL Compiler
CTS - Clock Tree Synthesis
DFM - Design for Manufacturability
DFY - Design for yield
LEF - Library Exchange Format
FEP - Failing End Points
WNS - Worst Negative Slack
TNS - Total Negative Slack

Basic vim commands

Opening a file

vim <filename>

Vim has 2 modes, command mode and insert mode. Command mode is where you enter vim commands and
insert mode is where you type. By default, vim enters command mode on launch. To enter insert mode, press i

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To return to command mode, press ESC

ESC

To save a file, in command mode, type

:w!

To quit without saving, in command mode, type

:q!

To save and quit, in command mode, type

:wq!

To view line numbers, in command mode, type

:se nu

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