Gate Dielectric Scaling for High-Performance CMOS: from SiOl to High-K
Robert Chaq Suman Datta, Mark Doczy, Jack Kavalieros and Matthew Metz
Intel Corporation
5200 N.E. Elam Young Parkway, Hillshoro, OR 97124, USA. Mail-stop: RA3-252
m -
503-613-6141,
Abstract
We have successfully demonstrated VeV high-performance
PMOS and NMOS transistors with high-Wmetal-gate gate
stacks with the right threshold V o k W for both P and
channels on bulk Si. We believe that high-Wmetal-gate is an
option for the 45nm high-performance logic technology node.
1. Introduction
The silicon industry has been scaling Si02 aggressively for
the past 15 years for low-power, high-performance CMOS
logic as thin as 1 . 2 (physical
~ ~ Tax) has
already been successfully implemented in the 90nm logic
technology node [ref. I]. Research transistors with 0.8nm
Si02 have also been demonstrated in the laboratory [ref. 2-31.
However, continual gate dielectric scaling will require high-
k as si02 Will eventually OUf of atoms for further
scaling. Most of the high-K gate dielectrics investigated are
Hf-hased and &based [ref. 461. Both PobSi and metals are
being evaluated as gate electrodes for the high-K dielectrics
[ref. 7-91, There are many challenges repotted in literature in
replacing with high-l( for high.perf,,rmance cM0s[ref,
IO-121. This paper will present results on the 0.8nm Si02 and
very high-performance PMOS and NMOS transistors with
high-Wmetal-gate for high-performance logic applications.
2. Si% Scaling
The physical thickness of Sio2has been scaled aggressively
for low.power, high.perfomance logic appl,cat,ons, ~i~~~~ 1
shows the physical thickness trend of Si02 for the various
logic 1 . 2 ~ physical si02 has already been
successfully implemented in the 90nm logic node [ref. I]. In
addition, 0.8nm physical S i 0 2 has also been produced [ref. 2-
31. TEM cross sections of the 1.2nm and 0.8nm si% gate
oxides are shown in ~i~~~~~ 2-3, The cv and lg.
Vg characteristics of the 0 . 8 m Si02 are shown in ~ i g u r e s4
5. Figures 6-7 show the device characteristics of the
experimental 15nm (physical gate length) NMOS transistor
with 0.8m Si@. The data shows that the 15nm transistor
with 0.8nm physical Si02 has well-controlled shortshannel
characteristics.
3. HighK Dielectrics
It has been reported in literature [ref. 121 that Fermi level
pinning at the high-WpolySi interface causes high threshold
voltages in MOSFET transistors. It has also been reported
that high-WpolySi transisbr exhibits severely degraded
channel mobility due to the coupling of low energy surface
4-89114-037-2?/03 124
optical (SO) phonon modes arising from the polarization of
the high-K to the inversion channel charge carriers [ref. 131,
and that metal gate may be more effective in screening the
high.K so phonons fro,,, coupling to the channel ,,,,der
inversion conditions [ref, 13-141, On the other hand, the use
of high-WmetaLgate requires a ptype metal and a -type
metal with the right work functions for high-performance
logic applications On "Ik si [Ief. "1.
We have successfully fabricated high-performance PMOS
and NMOS transistors with high-Wmetabgate stacks. The
transistors have physical gate length (k) of 80nm and the
electrical oxide thickness (Toxe) is 1.45nm measured at
inversion. Figure 8 compares the leakage characteristics of
the high-WmetaLgate stacks with the conventional
SiqipolySi. Figures 910 show the device characteristics of
the PMOS transistor with high-l(/metal-gate, while ~i~~~~~
11-12 show the device characteristics ofthe NMOS
with high-Wmetabgate, Both the high-l</metal-gate PMOS
and NMOS transistors show very high drive performance
(Idsat) with the right Vth both p and n-ehannel
devices on bulk Si, with very low gate leakage.
4. F'rom Si02 to High-K
We have implemented 1.2nm physical Si02 in our 90nm
logic technology node 111, and have scaled physical Si02
further down to 0.8nm and integrated it in research transistors
with 15nm Physical gate length which show well-controlled
short-channel characteristics. We have also successfully
demonstrated high-Performance and
transiston with W - W m e t a k a t e gate Stacks with the right
Vfh for both P- and n-channels on bulk Si, with very low gate
leakage. We believe high-Wmetal-gate is an option for the
45nm logic technology node for high-performance CMOS,
5. References
[I] S. Thompsonetal.,lEDMTechnicalD;~~~tgest,p.6I,2OO2.
[2] R. Chauctal., I E D M T ~ C ~ige~t,p.45,2000.
~~~C~I
[3] R. Chau et al., Physica E, Low-dimensional Systems and N m o m c h r e ~ ,
Vol. 19,lssues 1-2,p.1,2003.
[4] R. Choi et al., IEDM Technical Digcsl, p.613,2002.
[SI G. L U C O V S ~et ai., IEDM rehnical Digest, p.617.2002.
[6] s. humiya et al., s p p . ofVLS1 Technology, p.17,2003.
[7]Y. ~ i eta!.,
m s ~ pofVLsi~echnology,p.l67,2003.
.
[XI J.H.Lee et al., IEDM Technical Digest, p.359.2002.
[9]S.B. samavedam et al., IEDM Technical Digat, p.433,2002.
IWGI2003, Tokyo
[IO] R.M. Wallace, G. W i l t MRS Bulletm. Vol. 27, NO. 3. p.192. 2002. [I31 M. Fmheni et al., J. Appl. Phys.,Vol. 90,p.4587,2001
[1I]V.Misrraetal.,MRSBulletin.Vol.27,No.3,p.212.2002. [I41 S. Dam et al.. to be prcsented at 2003 IEDM.
[ I21 C. Hobbs et al., Symp. ofVLSl Technology,p.9.2003. [I 51 I. D? at al., Solid State Electron., Vol. 44,p.1077. 2000.

E E E @
Fig. 1 Scaling of physical thickness of S O 2 gale oxide Fig. 2 High resolution TEM cross section of 1.2nm
across technology generations. physical S O i gate oxide at the 90nm logic technology
node.

1 -05 0 0.5 1

vg M
Inversion Capacitance

F i g . 3 High resolution TEM cross section of 0.8nm Fig. 4 Inversion split C-V measurements o f 0.8nm
physical S O 2 gate oxide. physical S O 2 gate oxide for NMOS and PMOS.

"1'
E
,,. .

1-,
\ sal 15nmNMOS
,--
"I * 0.8"

,E-l

,I-@
4.5
y 0.5
0 O Z Q A M O d
vs (v*)
DWnVoltaaoM
Fig. 5 Inversion gate leakage measurements of 0.8nm Fig. 6 Id-Vds characteristics of 15nm Lg experimental
physical S i 0 2 gate oxide for NMOS and PMOS. NMOS transistor with 0.8nm physical S O 2 gate oxide

125 IWGI 2003,Tokyo

 4
5,02,pol'rs, ',
I.E+Ql
'.L
I
- 1.ElOO
.
l
l

3
i l . E Q 6 Y S.S. ,= 95mVldecade
,
-3 HigbWmatal-gab
DlBL = 100mVN
1.M3
.-Ca 1.EQ loff = 180nAlum
r3
6 1.EQ 1.e04 1
0 5 10 15 20 25
0 0.2 0.4 0.6 0.8
bx,a,.ss I'[
Gate Voltage 0 Fig. 8 Accumulation gate leakage as a function o f electrical
Fig. 1 Id-Vg charactenstics of 15nm Lg expenmental thickness for high-Wmetal-gategate stacks. Also shown for
NMOS transntor with 0 8nm physical SiO, gate oxide comparison is leakage for Si0,ipolySi gate stack.

1E-03 -7.E-04
Vdr1.3
1E -04 -6.E-04
- 1E-05 -5.E-04

a9f 1E-06
1E-07
Ion = 693 pAlpm
loff = 25 nAlpm
f
3
9
-4.E-04
-3.E-04
1E-08 Lg = 80nm -2.E-04
1E-09 Toxe =14.5A
-l.E-04
1E-10
O.E+OO
-0.1 -0.3 -0.5 -0.7 -0.9 -1.1 -1.3
-0.1 -0.3 -0.5 -0.7 -0.9 -1.1 -1.3
v g (V)
Vds (4
Fig. 9 Id-Vg characteristics of the 80 nm Lg PMOS Fig. 10 Id-Vds characteristics ofthe 80 nm Lg PMOS
transistors with high-Wmetal-gate gate stack at Vcc=1.3V. trmsistors with high-Wmetal-gate gate stack.

l.E-02 0.0016
1.GO3 0.0014
1.E-04 0.0012

E l.E-05 g 0.001
5 l.E-06
I

p l.E-07
Ion = 1.5 mAlpm
loff = 43 nA/pm
-
a
p 0.0006
0.0008

l.E-08 Lg = 80nm 0.0004

I.E-09 Toxe =14.5A 0.0002

l.E-IO 0

0 0.2 0.4.0.6 0.8 I 1.2 1.4 0 0.2 0.4 0.6 0.8 I 1.2 1.4
Vd (V)
' vg (VI
Fig. 1 1 Id-Vg characteristics o f the 80 nm Lg NMOS Fig. 12 Id-Vds characteristics of the 80 nm Lg NMOS
transistors with high-Wmetal-gate gate stack at Vcc=I.3V. transistors with high-Wmeta-gate gate stack.

4-89114-037-2/03 126 IWGIZOO3, Tokyo