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    Memory Interleaving

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    Jain Mukul
    Memory interleaving allows an instruction pipeline and arithmetic pipeline to fetch instructions and operands from different memory segments simultaneously by dividing memory into multiple arrays each with their own address and data registers that can be accessed independently and in parallel through a common adder bus and bidirectional data bus.

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    Memory Interleaving

    Uploaded by

    Jain Mukul
    11 views3 pages
    Memory interleaving allows an instruction pipeline and arithmetic pipeline to fetch instructions and operands from different memory segments simultaneously by dividing memory into multiple arrays each with their own address and data registers that can be accessed independently and in parallel through a common adder bus and bidirectional data bus.

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    Memory interleaving allows an instruction pipeline and arithmetic pipeline to fetch instructions and operands from different memory segments simultaneously by dividing memory into multiple arrays each with their own address and data registers that can be accessed independently and in parallel through a common adder bus and bidirectional data bus.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    Download as pdf or txt
    11 views3 pages

    Memory Interleaving

    Uploaded by

    Jain Mukul
    Memory interleaving allows an instruction pipeline and arithmetic pipeline to fetch instructions and operands from different memory segments simultaneously by dividing memory into multiple arrays each with their own address and data registers that can be accessed independently and in parallel through a common adder bus and bidirectional data bus.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    Memory Interleaving

    • Inst. Pipeline may require the fetching of an inst. & an


    operand at the same time from 2 different segments.
    • An arithmetic pipeline usually requires 2 or more
    operands to enter the pipeline at the same time
    • Memory module is a memory array together with its
    own adder & data registration
    • Each memory array has its own AR & DR
    • AR receive into from a common adder bus & DR
    communicate with a bidirectional late bus

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