UNIVERSITY OF NEW SOUTH WALES

Assignment 1 Design
Report
ELEC2141-Digital Circuit Design
David Zhou
19/04/2017
Table of Contents
1. Design Approach -Q1........................................................................................................................1
2. Formulation -Q1................................................................................................................................1
3. Optimisation -Q1...............................................................................................................................3
4. Circuit implementation -Q1...............................................................................................................4
Logic Block -NAND.........................................................................................................................5
Arithmetic Block -NAND..................................................................................................................6
1-bit ALU -NAND.............................................................................................................................7
1-bit ALU -Final Design....................................................................................................................8
8-bit ALU........................................................................................................................................10
5. Verification -Q1...............................................................................................................................11
Verilog Test File...............................................................................................................................11
Simulation........................................................................................................................................11
1. Design Approach -Q2......................................................................................................................13
2. Formulation -Q2..............................................................................................................................14
3. Optimisation -Q2.............................................................................................................................16
4. Circuit implementation -Q2.............................................................................................................18
Nickels.............................................................................................................................................18
Dime Route......................................................................................................................................19
Change Output.................................................................................................................................20
No Change.......................................................................................................................................21
Combinational Circuit Block...........................................................................................................22
5. Verification -Q2...............................................................................................................................23
Verilog Test File...............................................................................................................................23
Simulation.......................................................................................................................................23
References...........................................................................................................................................25
Table of Figures
Figure 1 -1.1: Logic and Arithmetic Blocks Prototype..........................................................................1
Figure 2 -3.1: Logical K-map of output F..............................................................................................3
Figure 3 -3.2: Arithmetic K-map of output Cout......................................................................................4
Figure 4 -4.1: Logic Block -1 -NAND...................................................................................................5
Figure 5 -4.2: Logic Block -2 -NAND...................................................................................................5
Figure 6 -4.3: Logic Block Symbol -NAND..........................................................................................5
Figure 7 -4.4: Arithmetic Block -1 -NAND...........................................................................................6
Figure 8 -4.5: Arithmetic Block -2 -NAND...........................................................................................6
Figure 9 -4.6 Arithmetic Block -3 -NAND............................................................................................6
Figure 10 -4.7: Arithmetic Block -4 -NAND.........................................................................................7
Figure 11 -4.7: 1-bit ALU Block -NAND..............................................................................................7
Figure 12 -4.8: 1-bit ALU Block -1.......................................................................................................8
Figure 13 -4.9: 1-bit ALU Block -2.......................................................................................................8
Figure 14 -4.10: 1-bit ALU Block -3.....................................................................................................8
Figure 15 -4.11: 1-bit ALU Block -4.....................................................................................................9
Figure 16 -4.12 1-bit ALU Block -5......................................................................................................9
Figure 17 -4.13 1-bit ALU Block -6......................................................................................................9
Figure 18 -4.14 ALU Block Symbol....................................................................................................10
Figure 19 -4.8: 8-bit ALU Block..........................................................................................................10
Figure 20 -5.1: Verilog file of the 1-bit ALU.......................................................................................11
Figure 21 -5.2: Simulation of a 1-bit ALU when M=0, Cin=0..............................................................11
Figure 22 -5.3: Simulation of a 1-bit ALU when M=0, Cin=1..............................................................11
Figure 23 -5.4: Simulation of a 1-bit ALU when M=1, Cin=0..............................................................12
Figure 24 -5.5: Simulation of a 1-bit ALU when M=1, Cin=1..............................................................12
Figure 25 -3.1: K-Map for 0 Dimes.....................................................................................................16
Figure 26 -3.2: K-Map for 1 Dime.......................................................................................................16
Figure 27 -3.3: K-map for Dime 2:15..................................................................................................17
Figure 28 -3.4: K-map which outputs true when D=2:15....................................................................17
Figure 29 -4.1: Nickel Block-1............................................................................................................18
Figure 30 -4.2 Nickel Block Symbol...................................................................................................19
Figure 31 -4.3 Dime_route Block -1....................................................................................................19
Figure 32 -4.4 Dime_route Block Symbol...........................................................................................19
Figure 33 -4.5: Change_Output Block -1.............................................................................................20
Figure 34 -4.6: Change_Output Block Symbol....................................................................................21
Figure 35 -4.7: No_Change Block -1...................................................................................................21
Figure 36 -4.8: No_Change Block Symbol..........................................................................................22
Figure 37 -4.9: Combination Circuit Block.........................................................................................22
Figure 38 -5.1: Verilog Test File..........................................................................................................23
Figure 39 -5.2: Simulation of the Combinational Circuit Block at D=0, Q=1.....................................23
Figure 40 -5.3: Simulation of the Combinational Circuit Block at D=1, Q=1.....................................24
Figure 41 -5.4: Simulation of the Combinational Circuit Block at D=2, Q=1.....................................24
Figure 42 -5.5: Simulation of the Combinational Circuit Block at D=3, Q=1.....................................24
Figure 43 -5.6 Simulation of the Combination Circuit Block at D=4, Q=1.........................................24
Figure 44 -5.7: Simulation of the Combination Circuit Block at D=4:8, Q=1.....................................24
Figure 45 -5.8: Simulation of the Combinational Circuit Block at D=9:13, Q=1................................25
Figure 46 -5.9: Simulation of a Combinational Circuit Block at D=14:15, Q=1..................................25
Figure 47 -5.10: Simulation of a Combinational Circuit Block at D=0:15, Q=0..................................25
David Zhou ELEC2141 Assignment 1 5157517

1. Design Approach -Q1

Question one requires designing an 8-bit Arithmetic Logic Unit (ALU) through cascading 1-bit ALUs.
The inputs of the 1-bit ALU are M, S0, S1, A, B, and C0, where M controls the type of operation, and
S0 and S1 select the operation. The inputs A and B are each 1-bit of data, C 0 is the carry-in bit. The
design assumes the Cout is the same as Cin for the logical circuit (M=0)
NOTE: C0 and Cin are used interchangeably.
The 1-bit ALU initially used two function blocks as seen below, however, after completing the NAND
implementation the design is switched to an all gate implementation to reduce the GIC.

Figure 1 -1.1: Logic and Arithmetic Blocks Prototype

The final design should have Cout same as the Cin, and F should be derived from a K-map of variables
S0, S1, A, and B. To use the K-map for optimisation, the columns for M, C in, S0, S1, A, and B should
be placed on a truth table. The mode is then used to select either logical or arithmetic operations.

2. Formulation -Q1
The formulation process involves placing the specified results into the truth table format, they are:

Bit 1 Logic Cin=X

M Cin S0 S1 A B F Term Cout
0 X 0 0 0 0 0 0 X
0 X 0 0 0 1 0 1 X
0 X 0 0 1 0 1 2 X
0 X 0 0 1 1 1 3 X
0 X 0 1 0 0 1 4 X
0 X 0 1 0 1 1 5 X
0 X 0 1 1 0 0 6 X
0 X 0 1 1 1 0 7 X
0 X 1 0 0 0 0 8 X
0 X 1 0 0 1 1 9 X
0 X 1 0 1 0 1 10 X
0 X 1 0 1 1 0 11 X
0 X 1 0 0 0 1 12 X
0 X 1 0 0 1 0 13 X
0 X 1 0 1 0 0 14 X
0 X 1 0 1 1 1 15 X
Table 2.1: Truth table for the 1-bit logic block

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David Zhou ELEC2141 Assignment 1 5157517

Bit 1 Arithmetic Cin=0

M Cin S0 S1 A B F Term Cout
1 0 0 0 0 0 0 0 0
1 0 0 0 0 1 0 1 0
1 0 0 0 1 0 1 2 0
1 0 0 0 1 1 1 3 0
1 0 0 1 0 0 1 4 0
1 0 0 1 0 1 1 5 0
1 0 0 1 1 0 0 6 0
1 0 0 1 1 1 0 7 0
1 0 1 0 0 0 0 8 0
1 0 1 0 0 1 1 9 0
1 0 1 0 1 0 1 10 0
1 0 1 0 1 1 0 11 1
1 0 1 0 0 0 1 12 0
1 0 1 0 0 1 0 13 1
1 0 1 0 1 0 0 14 0
1 0 1 0 1 1 1 15 0
Table 2.2: Truth table for 1-bit logic block when carry-in=0

Bit 1 Arithmetic Cin=1

M Cin S0 S1 A B F Term Cout
1 1 0 0 0 0 1 0 0
1 1 0 0 0 1 1 1 0
1 1 0 0 1 0 0 2 1
1 1 0 0 1 1 0 3 1
1 1 0 1 0 0 0 4 1
1 1 0 1 0 1 0 5 1
1 1 0 1 1 0 1 6 0
1 1 0 1 1 1 1 7 0
1 1 1 0 0 0 1 8 0
1 1 1 0 0 0 0 9 1
1 1 1 0 1 0 0 10 1
1 1 1 0 1 1 1 11 1
1 1 1 0 0 0 0 12 1
1 1 1 0 0 1 1 13 1
1 1 1 0 1 0 1 14 0
1 1 1 0 1 1 0 15 1
Table 2.3: Truth table for 1-bit logic block when carry-in=1

Given these truth tables, it is seen that the F outputs for logic and arithmetic when the carry-in is zero
are the same, and the arithmetic output F when carry-in is one is simply NOT F.

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David Zhou ELEC2141 Assignment 1 5157517

HenceF=Σm(2,3,4,5,9,10,12,15) , when M=0 or M=0 and Cin=0.

F=Σm(0,1,6,7,8,11,13,14 ) , when M=1 and Cin=1.
The carry-out for the logical operation is the same as the carry-in which can be easily implemented in
the logical block.
The carry-out for the arithmetic operation are slightly more challenging as they are given by:

C¿ =Σ m(11,13) when M=1, Cin=0.

C¿ =Σ m ( 2,3,4,5,9,10,11,12,13,15 ) when M=1, Cin=1.
The Boolean expression at this stage is not used since it currently requires a significant number of
gates, and should be optimised through a K-map before implementation.
The design approach chosen for the 1-bit ALU requires two blocks, logic and arithmetic, which can be
seen in Figure 1.1.

3. Optimisation -Q1
To optimise the Sum of Products expression derived earlier, K-maps are used.

Figure 2 -3.1: Logical K-map of output F

Note: as stated in Figure 3.1, all the prime implicants are essential prime implicants.
Since the sum of products expressions for F in logic, and arithmetic when C in=0 are identical the same
optimised expression can be recycled. Since output F for the arithmetic operations when C in=1 is just
the previous F (logical F) through a NOT gate the 0s on the K-map does not need to be optimised.
This expression can be further optimised through multi-level optimisation:

S 1 Á B́+ Ś0 S 1 Á+ Ś 0 Ś1 A+ Ś1 A B́+ S 0 Ś1 Á B+ S 0 S1 AB=S´0 ( S 1 Á+ Ś 1 A ) + B́ ( S 1 Á+ Ś1 A ) + S 0 B ( S 1 A+ Ś 1 Á )
¿ S´0 ( S 1 ⊕ A ) + B́ ( S1 ⊕ A ) + S0 B ( S 1 ⊕
´ A) ¿ S´0 B́ ( S1 ⊕ A ) + S0 B ( S 1 ⊕
´ A) ¿ S 0 B ⊕ S1 ⊕ A

M Cin F
0 0 S 0 B ⊕ S1 ⊕ A
0 1 S 0 B ⊕ S1 ⊕ A
1 0 S 0 B ⊕ S1 ⊕ A
1 1 S 0 B ⊕´S1 ⊕ A

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David Zhou ELEC2141 Assignment 1 5157517

Table 3.1: Optimised output F for different values of M and C i n

The carry-out for the logical block (M=0) is equal to the carry-in, however, for the arithmetic block,
the carry-outs given in min-terms need to be further simplified through a K-map.

Figure 3 -3.2: Arithmetic K-map of output Cout

Note: as stated in Figure 3.2, all the prime implicants are essential prime implicants.
Multi-level optimisation:

When Cin=0, C out ( S 0 , S 1 , A , B ) When Cin=1, C out ( S 0 , S 1 , A , B )

¿ S 0 S 1 Á B+S 0 Ś 1 AB ¿ S 1 Á+ S 0 B+ Ś1 A
¿ S 0 B ( S1 Á + Ś1 A ) ¿ S 0 B( S 1 ⊕ A) ¿ S 1 ⊕ A+ S 0 B

M Cin Cout
0 0 0
0 1 1
1 0 S 0 B( S 1 ⊕ A)
1 1 S 1 ⊕ A+ S 0 B
Table 3.2: Optimised output C o u t for different values of M and C i n

4. Circuit implementation -Q1

The advantages of the NAND gate are a more native application of CMOS technology, which results
in a reduced chip area and increased chip speed, however, by using a NAND gate design the gate
input cost becomes very expensive. Because of the high GIC from a NAND implementation every
gate is used to minimise the gate input cost. (A NAND implementation was previously done, however,
after evaluating the GIC, the design is switched to using every single gate)
NOTE: The NAND design has been left in the design report below in headings under NAND, which
shows the previous NAND implementation. However, the final design did not use a NAND
implementation.

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David Zhou ELEC2141 Assignment 1 5157517

Logic Block -NAND

Figure 4 -4.1: Logic Block -1 -NAND

This section of the logic block reads in A, B, S0, and S1 and produces the NOT versions of each
variable. It also reads in Cin and passes it out as Cout as per the design specifications. Figure 4.1 has a
GIC of 12.

Figure 5 -4.2: Logic Block -2 -NAND

The equation S 1 Á B́+ Ś0 S 1 Á+ Ś 0 Ś1 A+ Ś1 A B́+ S 0 Ś1 Á B+ S 0 S1 AB is applied in the expression
above. Through passing signals through the NAND gate twice, it is equivalent to passing the initial
signals to an AND gate, then passing all the AND gate outputs to an OR gate. Through it connects to
the signals read in during figure 4.1 to the corresponding gates, and outputs F. Figure 4.2 has a GIC of
26.

Figure 6 -4.3: Logic Block Symbol -NAND

The block Logic has a GIC of 12+26=38.

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David Zhou ELEC2141 Assignment 1 5157517

Arithmetic Block -NAND

Figure 7 -4.4: Arithmetic Block -1 -NAND

This section of the logic block reads in A, B, S0, S1, and Cin and produces the NOT versions of each
variable. Figure 4.4 has a GIC of 10.

Figure 8 -4.5: Arithmetic Block -2 -NAND

The above section is almost identical to the previous logic section as it has the same equation:
S 1 Á B́+ Ś0 S 1 Á+ Ś 0 Ś1 A+ Ś1 A B́+ S 0 Ś1 Á B+ S 0 S1 A Figure 4.5 routes the earlier input except
for Cin to produce F_1 which equal to F when the carry-in is zero. It also passes F_1 into both inputs
of ta NAND gate to produce N_F_1 which is equal to F when the carry-in is one. Figure 4.5 has a GIC
of 28.

Figure 9 -4.6 Arithmetic Block -3 -NAND

The section of the block above uses all the inputs except Cin to create two separate Cout outputs which
correspond to the equations, S 0 S 1 Á B+S 0 Ś 1 AB and S 1 Á+ S 0 B+ Ś1 A , respectively. The one
of the two outputs are selected based on the carry-in as seen in the later figures. Figure 4.6 has a GIC
of 19.

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David Zhou ELEC2141 Assignment 1 5157517

Figure 10 -4.7: Arithmetic Block -4 -NAND

The section of the arithmetic block above routes F_1 and C_out_1 to outputs F and C_out, if the
carry-in is zero. Conversely, it also routes F_2 and C_out_2 to outputs F and C_out if the carry-in is
one. Figure 4.7 has a GIC of 12.
The arithmetic block has a total GIC of 69.

1-bit ALU -NAND

Figure 11 -4.7: 1-bit ALU Block -NAND

The 1-bit ALU block reads in A, B, S0, S1, and Cin into both the logic and arithmetic block which
produces F1 and Cout 1, and F2 and Cout 2. The mode is read in and inverted through a NAND gate; the
mode is then used to route the correct F1 or F2 to output F. The mode is also used to route the correct
Cout 1 or Cout 2 to Cout. The GIC of the 1-bit ALU is 38+69+2+6x2=121.
It should be noted that the NAND get was chosen because it is a universal gate as well as the NAND
gate being a natural implementation of CMOS technology in terms of chip speed and area. [1]
The 1-bit ALU can be further optimised regarding GIC if every single gate is used and if the logical
block is recycled. Due to the NAND gate restriction, multi-level optimisation would result in
increasing the total gate input cost. (It is further optimised, and the NAND design is removed below)

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David Zhou ELEC2141 Assignment 1 5157517

1-bit ALU -Final Design

Note: the following GIC calculations are assuming the GIC of a 3-input XOR gate is three, despite how “A
XOR gate can only have two inputs” [1]

Figure 12 -4.8: 1-bit ALU Block -1

The section above is used to read in the inputs, M, Cin, S0, S1, A, and B, and produces the inverted
version of Cin and M as N_Cin and N_M, respectively. Figure 4.8 has a GIC of 2.

Figure 13 -4.9: 1-bit ALU Block -2

The Figure above produces the output F1, which is the output for the logical calculations, and when
arithmetic when Cin=0. It has the equation: S 0 B ⊕ S1 ⊕ A
Figure 4.9 has a GIC of 5.

Figure 14 -4.10: 1-bit ALU Block -3

The section above considers two cases, logical and arithmetic, and assigns the current mode’s output
to output F. In the first instance when M=0, then N_M=1, hence the output will be F1. In the second
instance where M=1, the output depends on Cin, the equation can be described as F1 when Cin=0 and
NOT F1 when Cin=1, thus the equation is: F 1× Ć¿ + F´ 1 ×C ¿=F ⊕C ¿ . The arithmetic and
logical F outputs are then fed into an OR and the output F.
Figure 4.10 has a GIC of 8.

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David Zhou ELEC2141 Assignment 1 5157517

Figure 15 -4.11: 1-bit ALU Block -4

Figure 4.11 provides the two Cout for the arithmetic mode; it implements the two equations:

C out =S 0 B (S 1 ⊕ A)
1
C out =S1 ⊕ A+ S 0 B The output C_Out_1 is for when the carry-in is zero,
2

while the output C_Out_2 is for the carry-in one.

Figure 4.11 has a GIC of 11.

Figure 16 -4.12 1-bit ALU Block -5

Figure 4.12 outputs take C out1 , C out2 , C¿ and N_C_in as inputs, it outputs C out 1
when
Cin=0, and C out when Cin=1, the correct output is then passed onto Carith through an OR gate.
2

Figure 4.12 has a GIC of 6.

Figure 17 -4.13 1-bit ALU Block -6

Figure 4.13 take Cin, Carith, M, and N_M as inputs, and outputs the Cout based on the current mode of
the operation. If M=0 then per the custom design specifications, C out=Cin, however, if M=1 then Carith
from earlier will be output to Cout.
Figure 4.13 has a GIC of 6.

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David Zhou ELEC2141 Assignment 1 5157517

Figure 18 -4.14 ALU Block Symbol

The 1-bit ALU has a total GIC of 2+5+8+11+6+6=33.

8-bit ALU
The 1-bit ALUs can then be cascaded eight times to produce the 8-bit ALU as seen below:

Figure 19 -4.8: 8-bit ALU Block

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David Zhou ELEC2141 Assignment 1 5157517

The 8-bit ALU takes inputs M, A(7:0), B(7:0), S0, S1, and outputs Cout and F(7:0), through cascading
eight 1-bit ALUs. It has a gate input cost of 8x33=264, while the original NAND implementation has
a GIC of 8x121=968. Hence the XOR gate based design was chosen over the NAND design.

5. Verification -Q1
The schematics of each component of the circuit is included above in the circuit implementation
section.

Verilog Test File

Figure 20 -5.1: Verilog file of the 1-bit ALU

The length of the simulation is set to 6400ns to cycle through all the possible inputs.

Simulation

Min-terms 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Figure 21 -5.2: Simulation of a 1-bit ALU when M=0, Cin=0

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David Zhou ELEC2141 Assignment 1 5157517

Min-terms 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Figure 22 -5.3: Simulation of a 1-bit ALU when M=0, Cin=1

Min-terms 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Figure 23 -5.4: Simulation of a 1-bit ALU when M=1, Cin=0

Min-terms 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Figure 24 -5.5: Simulation of a 1-bit ALU when M=1, Cin=1

NOTE: The midterm show in the figures above reset every 16 terms to make the comparison and
verification more convenient. If all the inputs are treated as cumulative terms, the min-terms should be
a counter from 0 to 63.
The simulated results are then compared to the original truth table. For when M=0 (Logic) the C out
values should be the same as the Cin values, as there is only one logic truth table.

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David Zhou ELEC2141 Assignment 1 5157517

1. Design Approach -Q2

Question 2 requires the design of a combinational circuit block which produces change for a quarter
from dimes and nickels, which will aim to provide the least amount of coins as change. The inputs of
question 2 are the numbers of dimes and nickels left in the system, and the number of quarters which
change needs to be provided. The number of dimes and nickels left in the system are presented in 4-
bits. Thus the maximum number dimes and nickels left in the system is 15 each. The number of
quarters for the input is assumed to be a 1-bit number, which defines the maximum number of input
quarters as 1.
The outputs of combination circuit block are the number of dimes and nickels dispensed as a 4-bit
number, and another output to indicate if sufficient change is not available. The assumption is made
that the system either provides exact change for the quarter or no change at all. For example, if the
input is a quarter (25c), and the machine only has three dimes left (3x10c), there would be no change
provided and the NC (no change) output will be true. This logic is flawed in a real-world application;
however, it makes sense if it is assumed that machine does this calculation before accepting the
quarter.
When designing, the circuit block the obvious pattern is the number of possible outputs, the machine
has four possible outputs for the dime and nickel outputs:

Dimes Nickels
0 5
1 3
2 1
0 0
Table 1.1: Output Combinations for Dimes and Nickels

In the first scenario, there are no dimes. Hence all the change is provided in nickels.
In the second case there is one dime, so that dime is provided instead of two nickels.
In the third outcome which is the optimal scenario, there is sufficient nickels and dimes to provide the
change in the least amount of coins.
In the final scenario, there is not enough dimes and nickels to produce the EXACT change.
The no change output can be designed through checking if there is no dime and nickel outputs, since
if there are no dime and nickel outputs the no change must be true, assuming there is an input quarter.
If all the inputs Q, D(3:0), and N(3:0) are placed in a truth table, the number of inputs would be nine;
this means there would be 512 different combinations. Rather than having 512 combinations the truth
table can assume the case when Q=1, reducing the number of inputs down to eight. An 8-variable
truth table is still highly tedious and error prone, so a 4-input (nickels) truth table is made for each
input of dimes.

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David Zhou ELEC2141 Assignment 1 5157517

Another truth table is then created with the input D(3:0) and outputs as the different possible pairs,
which essentially uses the input dimes to route the input to the correct nickel truth table.
The design plans to use four functional blocks:
Nickels -Responsible for routeing the N(3:0) to the three different nickel output and no change
conditions. Provides outputs Out_0:2 and NC_0:2.
Dime_route -Forms three pair outputs from D(3:0), only one pair is true. Outputs Pair_0:2.
Change_Output -Outputs D_O(3:0) and N_O(3:0) which is the change from the inputs Q, Pair_0:2
and Out_0:2.
No_Change -Outputs the condition NC from the inputs Q, Pair_0:2, and NC_0:2.
NOTE: D=Dimes_Left N=Nickels_Left NC=No_Change D_O=Dimes_Out N_O=Nickels_Out

2. Formulation -Q2
The formulation process involves placing the specified results into the truth table format, they are:

Q=1 D=0
N(3) N(2) N1) N(0) N_O(3) N_O(2) N_O(1) N_O(0) NC
0 0 0 0 0 0 0 0 1
0 0 0 1 0 0 0 0 1
0 0 1 0 0 0 0 0 1
0 0 1 1 0 0 0 0 1
0 1 0 0 0 0 0 0 1
0 1 0 1 0 1 0 1 0
0 1 1 0 0 1 0 1 0
0 1 1 1 0 1 0 1 0
1 0 0 0 0 1 0 1 0
1 0 0 1 0 1 0 1 0
1 0 1 0 0 1 0 1 0
1 0 1 1 0 1 0 1 0
1 1 0 0 0 1 0 1 0
1 1 0 1 0 1 0 1 0
1 1 1 0 0 1 0 1 0
1 1 1 1 0 1 0 1 0
Table 2.1: Truth table for the number of nickels when D=0

The outputs for this truth table are either NC or five nickels. (25c)

Q=1 D=1
N(3) N(2) N1) N(0) N_O(3) N_O(2) N_O(1) N_O(0) NC
0 0 0 0 0 0 0 0 1
0 0 0 1 0 0 0 0 1
0 0 1 0 0 0 0 0 1
0 0 1 1 0 0 1 1 0
0 1 0 0 0 0 1 1 0
0 1 0 1 0 0 1 1 0
0 1 1 0 0 0 1 1 0
0 1 1 1 0 0 1 1 0
1 0 0 0 0 0 1 1 0

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David Zhou ELEC2141 Assignment 1 5157517

1 0 0 1 0 0 1 1 0
1 0 1 0 0 0 1 1 0
1 0 1 1 0 0 1 1 0
1 1 0 0 0 0 1 1 0
1 1 0 1 0 0 1 1 0
1 1 1 0 0 0 1 1 0
1 1 1 1 0 0 1 1 0
Table 2.2: Truth table for the number of nickels when D=1

The outputs for this truth table are either NC or one dime and three nickels. (25c)

Q=1 D=2:15
N(3) N(2) N1) N(0) N_O(3) N_O(2) N_O(1) N_O(0) NC
0 0 0 0 0 0 0 0 1
0 0 0 1 0 0 0 1 0
0 0 1 0 0 0 0 1 0
0 0 1 1 0 0 0 1 0
0 1 0 0 0 0 0 1 0
0 1 0 1 0 0 0 1 0
0 1 1 0 0 0 0 1 0
0 1 1 1 0 0 0 1 0
1 0 0 0 0 0 0 1 0
1 0 0 1 0 0 0 1 0
1 0 1 0 0 0 0 1 0
1 0 1 1 0 0 0 1 0
1 1 0 0 0 0 0 1 0
1 1 0 1 0 0 0 1 0
1 1 1 0 0 0 0 1 0
1 1 1 1 0 0 0 1 0
Table 2.2: Truth table for the number of nickels when D=2 to 15

The outputs for these truth tables are either NC or two dimes and nickel. The outputs for when D=2
and above are all the same because two dimes are enough to give the least amount of coins as change.
The output is NC when N=0 because the change must be EXACTLY 25 cents, no more, no less.
Note that the output NC is always NOT the output of the non-zero column(s), it should also be noted
that the outputs of the non-zero columns are always identical.

Q=1 Condition for various pairs

D(3) D(2) D(1) D(0) 5x5 3x5, 10 5, 2x10 Min terms
0 0 0 0 1 0 0 0
0 0 0 1 0 1 0 1
0 0 1 0 0 0 1 2
0 0 1 1 0 0 1 3
0 1 0 0 0 0 1 4
0 1 0 1 0 0 1 5
0 1 1 0 0 0 1 6
0 1 1 1 0 0 1 7
1 0 0 0 0 0 1 8

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David Zhou ELEC2141 Assignment 1 5157517

1 0 0 1 0 0 1 9
1 0 1 0 0 0 1 10
1 0 1 1 0 0 1 11
1 1 0 0 0 0 1 12
1 1 0 1 0 0 1 13
1 1 1 0 0 0 1 14
1 1 1 1 0 0 1 15
Table 2: Truth table for using four dime inputs as a selection of three truth tables

The truth table above use dimes as a selection variable to route the output to the correct nickels truth
table based on the input of dimes.

3. Optimisation -Q2

Figure 25 -3.1: K-Map for 0 Dimes

All the prime implicants are essential prime implicants; they are: N ( 3) , N ( 2) N ( 0 ) , N ( 2) N ( 1)

∴ N O (2)=N O (1)=N (3)+ N (2) N (1)+ N (2)N ( 0)

Since NC_0 is NOT N_O(2), NC 0= N (3)+ N (2) N ´(1)+ N (2) N (0) (refer to truth table)

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David Zhou ELEC2141 Assignment 1 5157517

Figure 26 -3.2: K-Map for 1 Dime

All the prime implicants are the essential prime implicants; they are: N ( 2) , N ( 3) , N ( 1) N ( 0)
∴ N O (1)=N O (0)=N (2)+ N (3)+ N (1)N (0)

Since NC_1 is NOT N_O(1), ´ N (1)N (0)

N C 1= N ( 2)+ N (3)+

Figure 27 -3.3: K-map for Dime 2:15

All the prime implicants are essential prime implicants; they are: N ( 3) , N ( 2) , N ( 1) , N ( 0 )
∴ N O (0)=N (3)+ N (2)+ N (1)+ N (0)

Since NC_2 is NOT N_O(0), ´ N (1)+ N (0)

NC 2= N (3)+ N ( 2)+

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David Zhou ELEC2141 Assignment 1 5157517

Note when D is ≥ 2 the input is the same since there are sufficient dimes, so only a single nickel is
needed to provide exactly 25 cents in change, in the least amount of coins.

Figure 28 -3.4: K-map which outputs true when D=2:15

All prime implicants are essential prime implicants; they are; D (3 ) , D ( 2 ) , D ( 1 )

∴ Pair 2=D(3)+ D(2)+ D(1)

Since Pair_0 (5N, 0D) and Pair_1 (3N, 1D), have only a single min-term, k-map optimisation is not
necessary.

∴ Pair 0 (D(3), D (2) , D(1), D(0))=m0 ∴ Pair 1 ( D(3), D(2) , D (1) , D(0))=m1
¿ D´(3 ) D´( 2 ) D´( 1 ) D´( 0 ) ¿ D´(3 ) D´( 2 ) D´( 1 ) D(0)
´ ´
¿ D´(3 )+ D´( 2 ) + D´( 1 ) + D´( 0 ) ¿ D´(3 )+ D´( 2 ) + D´( 1 ) + D(0)
´
¿ D (3 )+ D ( 2 ) +´ D ( 1 ) + D(0) ´ ´
¿ D (3 )+ D ( 2 ) + D ( 1 ) + D(0)
The De Morgan’s law is then applied to the min-terms to reduce the GIC later.

D=0 D=1 D=2:15

N_O(3 0 0 0
)
N_O(2 N(3)+N(2)N(0)+N(2)N(1) 0 0
)
N_O(1 0 N(2)+N(3)+N(1)N(0) 0
)
N_O(0 N(3)+N(2)N(0)+N(2)N(1) N(2)+N(3)+N(1)N(0) N(3)+N(2)+N(1)+N(0)
)
NC NOT NOT NOT
(N(3)+N(2)N(0)+N(2)N(1)) (N(2)+N(3)+N(1)N(0)) (N(3)+N(2)+N(1)+N(0))
Table 3.1: Output terms of N for different values of D

D=0 D=1 D=2:15

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David Zhou ELEC2141 Assignment 1 5157517

Pair_0 1 0 0
Pair_1 0 1 0
Pair_2 0 0 1
Table 3.2: Conditions where Pair_x is true

The inputs N(3:0) is passed into each equation which outputs Out_2:0 and NC_2:0. Out_2:0 and
NC_2:0 is then routed the correct outputs terminals using the Pair_2:0 conditions. E.g. when D=0,
N(2)=N(0)=Out_0, and N(1)=N(3)=0

4. Circuit implementation -Q2

The circuit designed used every gate necessary to minimise the gate input cost of the circuit. This is
advantageous over a NAND gate implementation regarding the gate input cost, however, because of
using multiple types of gates, this is not a native implementation of CMOS technology and will have
lower speeds.

Nickels

Figure 29 -4.1: Nickel Block-1

Figure 4.1 takes in the 4-bit nickel input and outputs Out_2:0 and NC_2:0. Out_0 has the equation
N ( 3 ) + N (2 ) N ( 0 ) + N (2) N (1) , and NC_0 is simply Out_0 passed through an inverter.
Out_1 has the equation N ( 2 )+N ( 3 )+N ( 1 ) N (0) , and NC_1 is just Out_1 passed through an
inverter. While Out_2 has an equation of N ( 3 ) + N (2 )+ N ( 1 ) + N (0) and NC_2 is Out_2 through
a NOT gate. (refer to truth table)

Figure 30 -4.2 Nickel Block Symbol

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David Zhou ELEC2141 Assignment 1 5157517

The block Nickels has a GIC of 19.

Dime Route

Figure 31 -4.3 Dime_route Block -1

The Dime_route block takes D(3:0) as an input and outputs which of the three pairs will be formed if
there is sufficient change. Pair_0 has an equation of D (3 )+ D ( 2 )+´ D ( 1 ) + D(0) , and Pair_1 has an
equation of
´ ´ D (3 )+ D ( 2 )+D( 1) .
D (3 )+ D ( 2 )+ D ( 1 ) + D ( 0 ) . While Pair_2 has an equation of

Figure 32 -4.4 Dime_route Block Symbol

The block Dime_route has a GIC of 14.

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David Zhou ELEC2141 Assignment 1 5157517

Change Output

Figure 33 -4.5: Change_Output Block -1

The inputs for the Change_Output block are Q, Pair_2:0 and Out_2:0, through this the block outputs
D_O(3:0) and N_O(3:0).

D=0 D=1 D=2:15

Pair_0 1 0 0
Pair_1 0 1 0
Pair_2 0 0 1

Note: X in the context below represents any constant number from 0 to 2, inclusive.
The initial AND gates in Figure 26 -4.5 with inputs Out_X, Q, and Pair_X, pass the output Out_X
through if Q and Pair_X are true. Which means only one Out_X value is passed through since only
one Pair_X value can be true.
Assuming Q=1 for the below scenarios,
When Pair_0 and Out_0 are true, then N_O(2) and N_(0) are equal to Out_0.
When Pair_1 and Out_1 are true, then N_O(1) and N_(0) are equal to Out_1.
When Pair_2 and Out_2 are true, then N_O(0) is equal to Out_2.
Therefore when the other AND gates are false, the unused values are automatically set to ground.
The final 3-OR gate is used to set N_O(0).
The outputs N_O(3), D_O(2), and D_O(3), are never true and are hence connected to ground.
Pair_1 and Pair_2 are both attached to a 3 AND gate with Q and, Out_1 and Qut_2, which is
subsequently passed to D_O(0) and D_O(1), respectively. Since if Pair_1 is true the number of dimes
should be one, then D_O(0) should be one since only one Pair_X can be true Pair_2 will be zero. This
logic also applies for Pair_2 since the number of dimes should be two, Pair_2 is connected to D_O(1).
If Pair_0 is true then D_O(3:0)={0}, because only Pair_ X can be true at any time, then D_O(0) and
D_O(1) are equal to zero.

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David Zhou ELEC2141 Assignment 1 5157517

Figure 34 -4.6: Change_Output Block Symbol

The block Change_Output has a GIC of 18.

No Change

Figure 35 -4.7: No_Change Block -1

The No_Change block takes in inputs Q, NC_2:0, and Pair_2:0 and outputs NC. The no change
conditions for each of the pairs is read-in and Pair_2:0 is used to pass the no change conditions of the
right pair through to the OR gate which is used to ignore the zero values of the other inputs. The OR
gate output is then passed through an AND gate to check whether Q is true if it is then the NC_X
initially passed though is passed to the output NC.

Figure 36 -4.8: No_Change Block Symbol

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David Zhou ELEC2141 Assignment 1 5157517

The block No_Change has a GIC of 11.

Combinational Circuit Block

Figure 37 -4.9: Combination Circuit Block

The combination circuit block consists of all four of the blocks previously mentioned, the inputs are
Q, N(3:0), and D(3:0), and through this, it outputs N_O(3:0), D_O(3:0), and NC. The outputs of each
of the Nickel and Dime_route blocks are connected to the Change_Output and No_Change blocks.
The total gate input cost of the Combination Circuit Block is 19+14+18+11=62.
The GIC can be reduced if the assumption that there is always an input quarter is made, so Q=1,
however, Q has been left as in input to make the block more future proof. The block can be reused as
a combination circuit block which evaluates the first bit from a n-bit number of quarters.

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David Zhou ELEC2141 Assignment 1 5157517

5. Verification -Q2
The Xilinx ISE schematics are all included in section 4. Circuit Implementation.

Verilog Test File

Figure 38 -5.1: Verilog Test File

Simulation

Figure 39 -5.2: Simulation of the Combinational Circuit Block at D=0, Q=1

Figure 40 -5.3: Simulation of the Combinational Circuit Block at D=1, Q=1

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David Zhou ELEC2141 Assignment 1 5157517

Figure 41 -5.4: Simulation of the Combinational Circuit Block at D=2, Q=1

Figure 42 -5.5: Simulation of the Combinational Circuit Block at D=3, Q=1

Figure 43 -5.6 Simulation of the Combination Circuit Block at D=4, Q=1

Figure 44 -5.7: Simulation of the Combination Circuit Block at D=4:8, Q=1

Figure 45 -5.8: Simulation of the Combinational Circuit Block at D=9:13, Q=1

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David Zhou ELEC2141 Assignment 1 5157517

Figure 46 -5.9: Simulation of a Combinational Circuit Block at D=14:15, Q=1

Figure 47 -5.10: Simulation of a Combinational Circuit Block at D=0:15, Q=0

References
[1]ELEC2141 Lecture Week 3, 1st ed. Sydney: UNSW Sydney, 2017, pp. 30,37.

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