Department of Electrical & Electronic Engineering

Brac University
Spring-2022

EEE283
Digital Electronics

Open Ended Project

Section: 01

Group(8) members:
Sl. ID Name

1. 20121060 KHANDAKAR SAJID RAHMAN

2. 20121069 MOTASIM FAIYAZ

3. 20121077 MD. AR RIZA RUHANY

4. 20121079 MD. OMAR HOSSAIN KHAN

Project title:
Digital Alarm Clock

Objective:
To Implement our knowledge on sequential circuits and logic gates to make a device that is beneficial

Specification and requirement:

Alarm

● 7SEG_BCD_GRN – 4 pcs
● 4-bit counter IC-74161 – 4 pcs
● 4-bit comparator IC-7485
● Sounder
● Logic toggle
● NAND gate
● NOT gate
● 3 Input AND gate
● Ground
● Power
● Clock pulse (4269Hz)
● Connecting wires

Digital Clock

● 7SEG_BCD_GRN – 6 pcs
● 4-bit counter IC-74161 – 6 pcs
● 74157 Quadruple 2 to 1 Multiplexer
● Clock
● LogicToggles
● 2 Input NAND Gate
● 3 Input NAND Gate
● Power
● Ground
● Connecting Wires
MUX TRUTH TABLE
Design Methodology:
Digital Clock Subsystem Methodology:

In the entire project, the general idea is to cascade 4-bit counters 74161 with different reset points.

HOUR COUNTERS

C2 status C2C1 C1 status

00 Counter2 resets to 0 when c2 and c1 are at 2,3
01 respectively.
02
03 Counter1 has to reset at 9 and at 2,3 (i.e., with counter2)
04
05 Reset conditions for a 74161 counter
06
07 CLOCK LOAD
08 (RESET) ↑ 0
09
10
11 To have Counter1 reset at both the points, we have used a
12 XOR gate. And passed through the resets of the two
13 NAND gates through it.
14
15 So, Counter1 resets when:
16
17 2 ∙3 ⊕ 9
(RESET)
18
19
20
(RESET) 21 (RESET)
22
23
MINUTES and SECONDS counters
From right to left
Counter 1: Counts from 0-9
As it hits 9, the two binary 1’s goes through a NAND gate to the load and through a
NOT gate to counter 2.
Counter 2: Counts from 0-5
But it resets only when counter 1 hits 9 and counter 2 hits 5. The binary 5 and 9
fed into the load of counter 2 through the NAND gate. The 2nd NAND gate output
is fed through a NOT gate into the ENT of counter 3. So, it registers 1 when
counters 2 and1 hits 5 and 9 simultaneously.
Counter 3: Counts from 0-9
Made to rest when counters 3, 2 and 1 hit 9,5 and 9 respectively. And as its hits
9:59 counter 4 registers 1.
Counter 4: Counts from 0-5
Made to reset when counters 5,4,3,2 and 1 hit 5,9,5 and 9 respectively.

DIGITAL CLOCK SUBCIRCUIT

U5 U6
3 14 3 14
4
D0 Q0
13 4
D0 Q0
13 U4 U3 U2
5
D1 Q1
12 5
D1 Q1
12 3 14 3 14 3 14 U1
D2 Q2 D2 Q2 D0 Q0 D0 Q0 D0 Q0
6 11 6 11 4 13 4 13 4 13 3 14
D3 Q3 D3 Q3 D1 Q1 D1 Q1 D1 Q1 D0 Q0
15 15 5 12 5 12 5 12 4 13
RCO RCO D2 Q2 D2 Q2 D2 Q2 D1 Q1
7 7 6 11 6 11 6 11 5 12
ENP ENP D3 Q3 D3 Q3 D3 Q3 D2 Q2
10 10 15 15 15 6 11
ENT ENT RCO RCO RCO D3 Q3
2 2 7 7 7 15
CLK CLK ENP ENP ENP RCO
9 9 10 10 10 7
LOAD LOAD ENT ENT ENT ENP
1 1 2 2 2 10
MR MR CLK CLK CLK ENT
9 9 9 2
LOAD LOAD LOAD CLK
74161 74161 1 1 1 9
U19 MR MR MR LOAD
3

1
MR
U16:A 74161 74161
U9
74161
4077 74161
U7
U18 U17
NAND_4 U12
U8
U10 NAND_3
1

NAND
NOT
NAND_3 U11
NAND_3
NOT
U13 NOT

NOT

U14
NAND_3

NOT
TRUTH TABLE (0-5) COUNTERS

D C B A Previous LOAD
counter’s NOT
NAND gate
0 0 0 0 0 1
0 0 0 1 0 1
0 0 1 0 0 1
0 0 1 1 0 1
0 1 0 0 0 1
0 1 0 1 1 0 (RESET)

TRUTH TABLE (0-9) COUNTERS

D C B A Previous LOAD
counter’s NOT
NAND gate
0 0 0 0 0 1
0 0 0 1 0 1
0 0 1 0 0 1
0 0 1 1 0 1
0 1 0 0 0 1
0 1 0 1 0 1
0 1 1 0 0 1
0 1 1 1 0 1
1 0 0 0 0 1
1 0 0 1 1 0 (RESET)

NOTE: the shaded columns are the, columns whose inputs the RESET is dependent on. And Counter1 has
the same Truth table of 0-9 except it is independent of its previous counter’s NOT NAND gate.
Design Methodology:
Alarm Subsystem Methodology:

The Alarm subsystem consists of 4 counters and 4 BCD 7 segment displays. Two for Hours and two for
minutes. The HOURS and MINUTES are independent of each other. There are two Logictoggles. One to set
the alarm hour and one to set the alarm minute.

7485 4-bit comparators are cascaded and used to check if the time on clock matches the time set for
Alarm. If it does, it will send an output high to a 3_input AND gate. The second input is connected to clock
pulse with audible frequency which is used to make the SOUND ER sound. And the third input goes to
another LOGIC toggle. With the help of which, the Alarm can be turned on or off.

ALARM SYSTEM SUB-CIRCUIT

U21 U22
3
D0 Q0
14 3
D0 Q0
14 U27 U28
4 13 4 13 3 14 3 14
D1 Q1 D1 Q1 D0 Q0 D0 Q0
5 12 5 12 4 13 4 13
D2 Q2 D2 Q2 D1 Q1 D1 Q1
6 11 6 11 5 12 5 12
D3 Q3 D3 Q3 D2 Q2 D2 Q2
15 15 6 11 6 11
RCO RCO D3 Q3 D3 Q3
7 ENP 7 ENP RCO 15 RCO 15
10 10 7 7
ENT ENT ENP ENP
2 2 10 10
CLK CLK ENT ENT
9 9 2 2
LOAD LOAD CLK CLK
1 1 9 9
MR MR LOAD LOAD
1 1
MR MR
74161 74161
3

74161 74161
U26:A U29 U30
4077

U25
NAND_3 NAND
1

A HRS U31
NAND_3
0 U23
NOT
A MIN U24
0 NAND

NOT

ALARM ON/OFF
1
U35
10
A0
12
A1
13
A2
15
A3
9
B0
11
B1
14
B2
1
B3
2 7
U33 U34 A<B QA<B
3 6
A=B QA=B
10 10 4 5
A0 A0 A>B QA>B
12 12
A1 A1
13 13 7485
A2 A2
15 15
A3 A3
9 9
B0 B0 U36
11 11
14
B1
14
B1 LS1
B2 B2
1 1
B3 B3
2 A<B QA<B 7 2 A<B QA<B 7
3 6 3 6
U32 4
A=B QA=B
5 4
A=B QA=B
5 AND_3
A>B QA>B A>B QA>B
10 SOUNDER
A0
12 A1 7485 7485
13
A2
15
A3
9
B0
11
B1
14
B2
1
B3
2 7
A<B QA<B
3 6
A=B QA=B
4 5
A>B QA>B
7485
 TRUTH TABLE (0-5) COUNTERS TRUTH TABLE (0-9) COUNTERS

D C B A LOAD D C B A LOAD

0 0 0 0 1 0 0 0 0 1
0 0 0 1 1 0 0 0 1 1
0 0 1 0 1 0 0 1 0 1
0 0 1 1 1 0 0 1 1 1
0 1 0 0 1 0 1 0 0 1
0 1 0 1 0 (RESET) 0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0 (RESET)

ADDITIONAL FEATURES
Time setting feature: The first thing that a person does after purchasing a clock, is to sync it with a pre-
running one. This is why time setting is a vital feature for any clock.
The time setting for the digital implements a 2 to1 Quadruple Multiplexer 74157 and XOR gates. To set
time ENT input must be 1 and the clock must have a rising pulse. Therefore, to set the time you have to
press and hold the minute or the hour set button. And the minute or hour will by increasing by 1 every
second. 1

Snooze: Every annoying alarm clock has it and so does ours. Our snooze button can postpone the alarm for 1
minute. It’s the same button as A MIN.
FULL CIRCUIT DIAGRAM

HOURS MINUTES

U21 U22
3 14 3 14 U27 U28
D0 Q0 D0 Q0
4 13 4 13 3 14 3 14
D1 Q1 D1 Q1 D0 Q0 D0 Q0
5 12 5 12 4 13 4 13
D2 Q2 D2 Q2 D1 Q1 D1 Q1
6 11 6 11 5 12 5 12
D3 Q3 D3 Q3 D2 Q2 D2 Q2
15 15 6 11 6 11
RCO RCO D3 Q3 D3 Q3
7 7 15 15
ENP ENP RCO RCO
10 10 7 7
ENT ENT ENP ENP
2 2 10 10
CLK CLK ENT ENT
9 9 2 2
LOAD LOAD CLK CLK
1 1 9 9
MR MR LOAD LOAD
1 1
MR MR
74161 74161
3
74161 74161
U26:A U29 U30
4077

U25
NAND_3 NAND
1

A HRS U31
NAND_3
0 U23
NOT
A MIN U24
0 NAND

NOT

ALARM ON/OFF
1
U35
10
A0
12
A1
13
A2
15
A3
9
B0
11
B1
14
B2
1
B3
2 7
U33 U34 3
A<B QA<B
6
A=B QA=B
10 10 4 5
A0 A0 A>B QA>B
12 12
A1 A1
13 13 7485
A2 A2
15 15
A3 A3
9 9
11
B0
11
B0 U36
B1 B1 LS1
14 14
B2 B2
1 1
B3 B3
2 7 2 7
A<B QA<B A<B QA<B
3 6 3 6
U32 A=B QA=B A=B QA=B
4 5 4 5 AND_3
A>B QA>B A>B QA>B
10 SOUNDER
A0
12 7485 7485
A1
13
A2
15
A3
9
B0
11
B1
14
B2
1
B3
2 7
A<B QA<B
3 6
A=B QA=B
4 5
A>B QA>B
7485

HOURS MINUTES SECONDS

U5 U6
3 14 3 14 U4 U3 U2
D0 Q0 D0 Q0 U1
4 13 4 13 3 14 3 14 3 14
D1 Q1 D1 Q1 D0 Q0 D0 Q0 D0 Q0
5 12 5 12 4 13 4 13 4 13 3 14
D2 Q2 D2 Q2 D1 Q1 D1 Q1 D1 Q1 D0 Q0
6 11 6 11 5 12 5 12 5 12 4 13
D3 Q3 D3 Q3 D2 Q2 D2 Q2 D2 Q2 D1 Q1
15 15 6 11 6 11 6 11 5 12
RCO RCO D3 Q3 D3 Q3 D3 Q3 D2 Q2
7 7 15 15 15 6 11
ENP ENP RCO RCO RCO D3 Q3
10 10 7 7 7 15
ENT ENT ENP ENP ENP RCO
2 2 10 10 10 7
CLK CLK ENT ENT ENT ENP
9 9 2 2 2 10
LOAD LOAD CLK CLK CLK ENT
1 1 9 9 9 2
MR MR LOAD LOAD LOAD CLK
1 1 1 9
MR MR MR LOAD
74161 74161 1
U19 MR
3

74161 74161 74161

U16:A U9 74161
4077
U7
U17
U12
NAND_4 U8
NAND_3
NAND
U11
1

NAND_3
NAND_3 U10 NOT
NOT
U13 U18 NOT
NOT

U14
NAND_3

NOT

U15
15
E
1
A/B
13
4B
12 14
4Y 4A
10
3B
9 3Y 3A 11
6
2B
7 5
2Y 2A
3
1B
4 2
1Y 1A
74157

U20
XOR
0

HOUR SET MIN SET