Ele230 Lecture Notes PDF

Electronics I
Hacettepe University
27 May 2018
1. These lecture notes are complete and regularly updated at the address below:
http://www.ee.hacettepe.edu.tr/∼usezen/ele230/.
2. These lecture notes use material from several other sources like Prof. Selçuk Geçim's lecture
notes, Electronic Devices and Circuit Theory, 11th ed. by Boylestad and Nashelsky and and
its instructor materials.
Contents
List of Figures xvi

List of Examples xviii
List of Homeworks xix
Textbook xx
1 Semiconductor Diodes 1
1.1 Circuit Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Ideal Diode Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2.1 Determining State of an Ideal Diode . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 p -n Junction Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3.1 No Bias Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3.2 Reverse Bias Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3.3 Forward Bias Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3.4 Diode Characteristic Equation . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3.5 Zener Region (or Avalanche Breakdown Region) . . . . . . . . . . . . . . . . . 10
1.3.6 Peak Inverse Voltage (PIV) Rating . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3.7 Forward Bias Turn-On Voltage (VD(ON ) ) . . . . . . . . . . . . . . . . . . . . . 11
1.3.8 Temperature Eects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.3.9 Load Line and Operating Point (Q-point) . . . . . . . . . . . . . . . . . . . . 12
1.3.10 DC Resistance (Static Resistance) . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.3.11 AC Resistance (Dynamic Resistance) . . . . . . . . . . . . . . . . . . . . . . . 15
1.3.12 DC and Small-Signal AC (SSAC) Analysis . . . . . . . . . . . . . . . . . . . . 16
1.3.13 Average AC Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.4 Piecewise-Linear Diode Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5 Simplied Diode Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5.1 Determining State of a Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.6 Diode Specication Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.6.1 Semiconductor Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.6.2 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.7 Other Types of Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.8 Zener Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.9 Light Emitting Diode (LED) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
i
2 Diode Applications 28
2.1 Clippers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.1.1 Parallel Clippers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.2 Clampers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.3 Voltage Multiplier Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.3.1 Peak Rectier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.3.2 Voltage Doubler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.3.3 Voltage Tripler and Quadrupler . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.4 Zener Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.4.1 Zener Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.4.2 Other Zener Diode Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.4.3 Zener Diode Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.5 Practical Applications of Diode Circuits . . . . . . . . . . . . . . . . . . . . . . . . . 43
3 Rectiers and Voltage Regulating Filters 44

3.1 Properties of Electrical Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.1.1 DC Component (Average Value) and AC Component . . . . . . . . . . . . . . 44
3.1.2 Eective Value (RMS Value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.2 Half-Wave Rectier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.3 Full-Wave Rectier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.3.1 Center-Tapped Transformer Full-Wave Rectier . . . . . . . . . . . . . . . . . 54
3.3.2 Full-Wave Bridge Rectier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.4 Rectier Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.5 Voltage Regulation and Ripple Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.5.1 Voltage Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.5.2 Ripple Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.6 Capacitor Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.6.1 Ripple Factor of Capacitor Filter . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.6.2 Diode Conduction Period and Peak Diode Current . . . . . . . . . . . . . . . 64
3.7 Additional RC Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.7.1 DC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.7.2 AC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.8 π -Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4 Bipolar Junction Transistor (BJT) 72

4.1 Bipolar Junction Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.2 Common-Base Conguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.2.1 Input and Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.2.2 Three Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.2.3 Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.2.4 Alpha (α) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.2.5 Simplication (Active Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.2.6 AC Amplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.3 Common-Emitter Conguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.3.1 Input and Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.3.2 Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
ii
4.3.3 Beta (β ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.3.3.1 Determining β from a graph . . . . . . . . . . . . . . . . . . . . . . . 82
4.3.4 Relationship between β and α . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
4.3.5 Simplication (Active Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
4.4 Common-Collector Conguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
4.5 Operating Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.6 Simplied BJT Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5 DC Biasing of BJTs 87
5.1 DC Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
5.2 Three States of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.3 BJT DC Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.4 DC Biasing Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.4.1 Fixed-Bias Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.4.1.1 Base-Emitter Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
5.4.1.2 Collector-Emitter Loop . . . . . . . . . . . . . . . . . . . . . . . . . 90
5.4.1.3 Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.4.1.4 DC Load Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5.4.2 Emitter-Stabilized Bias Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5.4.2.3 DC Load Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.4.2.4 Improved Biased Stability . . . . . . . . . . . . . . . . . . . . . . . . 99
5.4.3 Voltage Divider Bias Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
5.4.3.1 Base-Emitter Loop (Exact Analysis) . . . . . . . . . . . . . . . . . . 101
5.4.3.2 Base-Emitter Loop (Approximate Analysis) . . . . . . . . . . . . . . 102
5.4.3.3 Collector-Emitter Loop and DC Load line . . . . . . . . . . . . . . . 103
5.4.4 Collector Feedback Bias Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 104
5.4.4.3 DC Load line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.4.5 Various Dierent Bias Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.4.6 pnp Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.5 Bias Stabilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.5.1 Stability Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
5.5.1.1 Derivation of Stability Factors (Voltage-Divider Bias Circuit) . . . . 109
5.5.1.2 Stability Factors for Other Bias Circuits . . . . . . . . . . . . . . . . 110
5.5.2 Stability of Transistor Circuits with Active Components . . . . . . . . . . . . 112
5.6 Practical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
5.6.1 Relay Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
5.6.2 Transistor Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
5.6.3 Transistor Switching Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
5.6.4 Logic Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
5.6.5 Current Mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
5.6.6 Voltage Level Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
iii
6 AC-DC Load Lines of BJT Circuits 119
6.1 BJT AC Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6.1.1 DC Load Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
6.1.2 Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.1.3 AC Load Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6.1.4 AC-DC Load Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.1.4.1 Maximum Symmetric Undistorted Swing Design . . . . . . . . . . . . 124
6.1.4.2 Other Amplier Congurations . . . . . . . . . . . . . . . . . . . . . 125
7 Field Eect Transistors (FETs) 131

7.1 Similarities and Dierences with BJTs . . . . . . . . . . . . . . . . . . . . . . . . . . 131
7.2 FET Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
7.3 FET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
7.4 Junction Field-Eect Transistor (JFET) . . . . . . . . . . . . . . . . . . . . . . . . . 133
7.4.1 Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
7.4.2 Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
7.4.2.1 VGS = 0 and VDS > 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
7.4.2.2 VGS < 0 and VDS > 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
7.4.2.3 Voltage-Controlled Resistor (Ohmic Region) . . . . . . . . . . . . . . 136
7.4.3 p-channel JFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7.4.3.1 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7.4.4 Circuit Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
7.4.5 Transfer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
7.5 Metal-Oxide-Semiconductor Field-Eect Transistors (MOSFETs) . . . . . . . . . . . . 140
7.5.1 Depletion-Type MOSFET (DMOSFET) . . . . . . . . . . . . . . . . . . . . . 140
7.5.1.1 Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
7.5.1.2 Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 141
7.5.1.3 Transfer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 142
7.5.1.4 p-channel DMOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . 143
7.5.2 Circuit Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
7.5.3 Enhancement-Type MOSFET (EMOSFET) . . . . . . . . . . . . . . . . . . . 144
7.5.3.1 Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
7.5.3.2 Transfer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 145
7.5.3.3 p-channel EMOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . 146
7.5.4 Circuit Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
7.5.5 MOSFET Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
7.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
8 DC Biasing of FETs 150

8.1 DC Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
8.2 FET DC Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
8.3 DC Biasing Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
8.3.1 Fixed-Bias Conguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
8.3.1.1 Gate-Source Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
8.3.1.2 Drain-Source Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
8.3.2 Self-Bias Conguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
iv
8.3.2.1 Gate-Source Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
8.3.3 Voltage-Divider Bias Conguration . . . . . . . . . . . . . . . . . . . . . . . . 157
8.3.3.1 Gate-Source Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
8.3.4 Voltage-Feedback Bias Conguration . . . . . . . . . . . . . . . . . . . . . . . 163
8.3.4.1 Gate-Source Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
8.3.5 p-channel FETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
8.4 Practical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
8.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
9 AC-DC Load Lines of FET Circuits 170

9.1 FET AC Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
9.1.1 AC and DC Load Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
9.1.2 Maximum Symmetric Undistorted Swing Design . . . . . . . . . . . . . . . . . 171
9.1.3 Other Amplier Congurations . . . . . . . . . . . . . . . . . . . . . . . . . . 172
10 BJT Small-Signal Analysis 173

10.1 Purpose of SSAC Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
10.1.1 BJT SSAC Analysis Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
10.2 BJT Small-Signal Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
10.2.1 Hybrid Equivalent Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
10.2.1.1 Simplied Hybrid Equivalent Model . . . . . . . . . . . . . . . . . . 176
10.2.1.2 Common-Emitter Hybrid Equivalent Model . . . . . . . . . . . . . . 177
10.2.1.3 Common-Emitter re Model . . . . . . . . . . . . . . . . . . . . . . . 178
10.2.1.4 Common-Base Hybrid Equivalent Model . . . . . . . . . . . . . . . . 178
10.2.1.5 Common-Base re Model . . . . . . . . . . . . . . . . . . . . . . . . . 179
10.2.1.6 Phase Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
10.3 Common-Emitter Fixed-Bias Conguration . . . . . . . . . . . . . . . . . . . . . . . . 180
10.3.1 Input Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
10.3.2 Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
10.3.3 Output Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
10.3.4 Phase Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
10.4 Common-Emitter Voltage-Divider Bias Conguration . . . . . . . . . . . . . . . . . . 184
10.4.2 Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
10.5 Common-Emitter Unbypassed-Emitter Bias Conguration . . . . . . . . . . . . . . . 186
10.5.2 Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
10.6 Emitter-Follower Conguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
v
10.6.2 Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
10.7 Common-Emitter Collector Feedback Conguration . . . . . . . . . . . . . . . . . . . 192
10.7.2 Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
10.8 Common-Base Conguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
10.8.2 Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
11 FET Small-Signal Analysis 201

11.0.1 FET SSAC Analysis Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
11.1 FET Small-Signal Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
11.1.0.1 Transconductance Parameter (gm ) . . . . . . . . . . . . . . . . . . . 203
11.1.0.2 Phase Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
11.2 Common-Source Fixed-Bias Conguration . . . . . . . . . . . . . . . . . . . . . . . . 204
11.2.2 Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
11.3 Common-Source Self-Bias Conguration . . . . . . . . . . . . . . . . . . . . . . . . . 206
11.3.2 Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
11.4 Common-Source Voltage-Divider Bias Conguration . . . . . . . . . . . . . . . . . . . 208
11.4.2 Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
11.5 Common-Source Unbypassed Self-Bias Conguration . . . . . . . . . . . . . . . . . . 210
11.5.2 Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
11.6 Source-Follower Conguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
11.6.2 Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
11.7 Common-Source Drain Feedback Conguration . . . . . . . . . . . . . . . . . . . . . 215
11.7.2 Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
11.8 Common-Gate Conguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
11.8.2 Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
vi
12 Frequency Response of Ampliers 220

12.1 First-Order RC Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
12.1.1 First-Order Highpass RC Filter . . . . . . . . . . . . . . . . . . . . . . . . . . 220
12.1.1.1 Cuto Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
12.1.1.2 Bode Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
12.1.1.3 Decibels (dB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
12.1.2 First-Order Lowpass RC Filter . . . . . . . . . . . . . . . . . . . . . . . . . . 224
12.1.2.1 Cuto Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
12.1.2.2 Bode Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
12.2 Typical Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
12.3 Low Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
12.3.1 BJT Ampliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
12.3.1.1 Eect of Coupling Capacitor C1 . . . . . . . . . . . . . . . . . . . . . 230
12.3.1.3 Eect of Bypass Capacitor C3 . . . . . . . . . . . . . . . . . . . . . . 231
12.3.1.4 Combined Eect of C1 , C2 and C3 . . . . . . . . . . . . . . . . . . . 231
12.3.2 FET Ampliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
12.3.2.3 Eect of Bypass Capacitor C3 . . . . . . . . . . . . . . . . . . . . . . 234
12.3.2.4 Combined Eect of C1 , C2 and C3 . . . . . . . . . . . . . . . . . . . 234
12.4 Miller Eect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
12.4.0.1 Miller Input Capacitance CMi . . . . . . . . . . . . . . . . . . . . . . 235
12.4.0.2 Miller Output Capacitance CMo . . . . . . . . . . . . . . . . . . . . . 236
12.4.0.3 Miller Representation . . . . . . . . . . . . . . . . . . . . . . . . . . 237
12.5 High Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
12.5.1 BJT Ampliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
12.5.1.1 Input Circuit Cuto Frequency fH 1 . . . . . . . . . . . . . . . . . . . 238
12.5.1.2 Output Circuit Cuto Frequency fH 2 . . . . . . . . . . . . . . . . . . 239
12.5.1.3 hf e (or β) Variation Cuto Frequency fβ . . . . . . . . . . . . . . . . 239
12.5.1.4 Combined Eect of fH1 , fH2 and fβ . . . . . . . . . . . . . . . . . . . 240
12.5.2 FET Ampliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
12.5.2.1 Input Circuit Cuto Frequency fH 1 . . . . . . . . . . . . . . . . . . . 242
12.5.2.2 Output Circuit Cuto Frequency fH 2 . . . . . . . . . . . . . . . . . . 242
12.5.2.3 Combined Eect of fH 1 and fH2 . . . . . . . . . . . . . . . . . . . . . 243
12.6 Gain-Bandwidth Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
13 Multistage (Cascaded) Ampliers 244

13.1 Cascaded Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
13.2 AC-Coupled Multistage Ampliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
13.3 DC-Coupled Multistage Ampliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
13.4 Cascode Amplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
13.5 Darlington Pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
13.6 Feedback Pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
vii
List of Figures
1.1 Diode circuit symbol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Ideal diode is short circuit when it is forward biased. . . . . . . . . . . . . . . . . . . 2
1.3 Ideal diode is open circuit when it is reverse biased. . . . . . . . . . . . . . . . . . . . 2
1.4 Characteristics curve of the ideal diode. . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.5 Diode circuit for Example 1.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.6 A p -n junction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.7 Depletion layer in a p -n junction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.8 p -n junction under no bias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.9 Diode behaviour under no bias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.10 p -n junction under reverse bias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.11 Diode behaviour under reverse bias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.12 p -n junction under forward bias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.13 Diode behaviour under forward bias. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.14 Diode characteristics curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.15 Zener region (or avalanche breakdown region) . . . . . . . . . . . . . . . . . . . . . . 10
1.16 Change of diode characteristics with temperature . . . . . . . . . . . . . . . . . . . . 12
1.17 Series diode conguration: (a) circuit, (b) diode characteristics curve. . . . . . . . . . 12
1.18 Drawing the load line and nding the point of operation. . . . . . . . . . . . . . . . . 13
1.19 Determining the DC resistance of a diode at a particular operating point. . . . . . . . 14
1.20 Dening the dynamic or AC resistance around an operating point . . . . . . . . . . . 15
1.21 Diode circuit with AC and DC sources. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.22 DC equivalent circuit of the circuit in Figure 1.21. . . . . . . . . . . . . . . . . . . . . 17
1.23 SSAC equivalent circuit of the circuit in Figure 1.21. . . . . . . . . . . . . . . . . . . 17
1.24 Determining the average AC resistance between indicated limits. . . . . . . . . . . . . 18
1.25 Piecewise-linear characteristics curve (blue line on the left) and piecewise-linear equi-
valent circuit (on the right) of the diode. . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.26 Simplied characteristics curve (on the left) and simplied equivalent circuit (on the
right) of the diode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.28 Simplied circuit for the diode circuit in Figure 1.27. . . . . . . . . . . . . . . . . . . 21
1.30 Simplied circuit for the diode circuit in Figure 1.29. . . . . . . . . . . . . . . . . . . 22
1.32 Semiconductor diode notation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.33 Some diode types and packagings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.34 Transition and diusion capacitance versus applied bias for a Silicon diode. . . . . . . 25
viii
1.35 Zener diode symbol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.36 Circuit symbol of an LED. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.37 Litronix 7-segment LED display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.38 Relative intensity versus wavelength. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.1 A series clipper circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.2 Voltage transfer characteristics (VTC) curve of the series clipper circuit Figure 2.1. . 29
2.3 Positive half-cycle operation of the series clipper circuit in Figure 2.1. . . . . . . . . . 29
2.4 Negative half-cycle operation of the series clipper circuit in Figure 2.1. . . . . . . . . . 29
2.5 A series clipper circuit with a DC supply. . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.6 Input and output of the series clipper circuit in Figure 2.5. . . . . . . . . . . . . . . . 30
2.7 Various series clipper examples (diodes are ideal). . . . . . . . . . . . . . . . . . . . . 31
2.8 A parallel clipper circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.9 Sample input and output waveforms of the parallel clipper circuit in Figure 2.8. . . . 32
2.10 A parallel clipper circuit with a DC supply. . . . . . . . . . . . . . . . . . . . . . . . . 32
2.11 A diode limiter circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.12 Outputs of the circuit in Figure 2.11: (a) VTC diagram, (b) output waveform. . . . . 33
2.13 Various parallel clipper examples (diodes are ideal). . . . . . . . . . . . . . . . . . . . 33
2.14 A clamper circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.15 Charging operation of the clamper circuit in Figure 2.14. . . . . . . . . . . . . . . . . 35
2.16 Discharging operation of the clamper circuit in Figure 2.14. . . . . . . . . . . . . . . . 35
2.17 A clamper circuit with a square wave input. . . . . . . . . . . . . . . . . . . . . . . . 36
2.18 Output of the circuit given in Figure 2.17. . . . . . . . . . . . . . . . . . . . . . . . . 36
2.19 A clamper circuit with a sinusoidal input. . . . . . . . . . . . . . . . . . . . . . . . . 36
2.20 Output of the circuit given in Figure 2.19. . . . . . . . . . . . . . . . . . . . . . . . . 37
2.21 Various clamper examples (diodes are ideal and capacitors are charged). . . . . . . . . 37
2.22 A peak rectier circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.23 For the circuit in Figure 2.22: (a) input waveform, (b) output waveform. . . . . . . . 38
2.24 Voltage doubler circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.25 Operation of the circuit in Figure 2.24 at (a) rst positive half-cycle, and (b) rst
negative half-cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.26 Voltage tripler/quadrupler circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.27 Zener diode operation: (a)ON (b) OFF. . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.28 A general Zener diode circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.29 Zener diode circuit for Example 2.9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.30 Single Zener diode clipper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.31 Dual Zener diode clipper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.1 Ideal half-wave rectier output of a sinusoidal input vi (t) = Vm sin(2πt/T ). . . . . . . 45

3.2 Ideal full-wave rectier output of a sinusoidal input vi (t) = Vm sin(2πt/T ). . . . . . . 45
3.3 Triangular waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.4 AC component of the triangular waveform in Figure 3.3. . . . . . . . . . . . . . . . . 47
3.5 Triangular waveform and its analytical expression. . . . . . . . . . . . . . . . . . . . . 49
3.6 A half-wave rectier circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.7 Input and ideal output waveforms for the half-wave rectier given in Figure 3.6. . . . 52
3.8 Input and output waveforms for the half-wave rectier when VD(ON ) = 0.7 V. . . . . . 53
ix
3.9 Input and ideal output waveforms of the full-wave rectier. . . . . . . . . . . . . . . . 53
3.10 Center-tapped transformer full-wave rectier. . . . . . . . . . . . . . . . . . . . . . . . 54
3.11 Positive half-cycle operation of the center-tapped transformer full-wave rectier in Fi-
gure 3.10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.12 Negative half-cycle operation of the center-tapped transformer full-wave rectier in
Figure 3.10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.13 Full-wave bridge rectier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.14 Positive half-cycle operation of the full-wave bridge rectier in Figure 3.13. . . . . . . 56
3.15 Negative half-cycle operation of the full-wave bridge rectier in Figure 3.13. . . . . . . 56
3.16 Positive-half cycle operation and full output of the full-wave bridge rectier when
VD(ON ) = 0.7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.17 Block diagram showing parts of a power supply. . . . . . . . . . . . . . . . . . . . . . 58
3.18 Filter voltage waveform showing DC and ripple voltages. . . . . . . . . . . . . . . . . 59
3.19 Simple capacitor lter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.20 Capacitor lter after a center-tapped transformer full-wave rectier. . . . . . . . . . . 60
3.21 Capacitor lter operation: (a) ideal full-wave rectier output, (b) ltered output voltage. 60
3.22 Capacitor lter output after a full-wave rectier: (a) actual output, (b) approximate
output where ripple waveform is approximated by a triangular waveform. . . . . . . . 61
3.23 Capacitor lter output (after a full-wave rectier) with charging and discharging timings. 62
3.24 Capacitor lter output voltage and diode current waveforms for a half-wave rectier:
(a) small C, (b) large C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.25 Capacitor lter circuit for Example 3.15. . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.26 Additional RC lter stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.27 Center-tapped transformer full-wave rectier and RC lter circuit. . . . . . . . . . . . 66
3.28 DC equivalent circuit of the additional RC lter stage in Figure 3.26. . . . . . . . . . 67
3.29 AC equivalent circuit of the additional RC lter stage in Figure 3.26. . . . . . . . . . 67
3.32 π -lter stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.1 Types of transistors: (a) pnp, (b) npn. . . . . . . . . . . . . . . . . . . . . . . . . . . 72

4.2 Biasing a transistor: (a) base-emitter forward-biased, (b) base-collector reverse-biased. 73
4.3 Current ow in a properly biased pnp transistor. . . . . . . . . . . . . . . . . . . . . . 74
4.4 Notation and symbols used with the common-base conguration: (a) npn transistor,
(b) pnp transistor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.5 Characteristics of an npn common-base amplier: a) Input characteristics, b) Output
characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.6 Output characteristics of a common-base amplier. . . . . . . . . . . . . . . . . . . . 76
4.7 Common-base cuto current (or reverse saturation current), ICBO . . . . . . . . . . . . 77
4.8 Simplied output characteristics of a common-base amplier. . . . . . . . . . . . . . . 78
4.9 Simplied input characteristics of a common-base amplier. . . . . . . . . . . . . . . 79
4.10 AC equivalent circuit of a common-base amplier. . . . . . . . . . . . . . . . . . . . . 79
4.11 Notation and symbols used with the common-emitter conguration: (a) npn transistor,
(b) pnp transistor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.12 Characteristics of an npn common-emitter amplier: a) Input characteristics, b) Output
characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
x
4.13 Common-emitter cuto current, ICEO . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.14 Determining βDC and βac from the output characteristics. . . . . . . . . . . . . . . . . 82
4.15 Notation and symbols used with the common-collector conguration: (a) npn transistor,
(b) pnp transistor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.16 Dening the region of operation for a transistor. . . . . . . . . . . . . . . . . . . . . . 84
4.17 An example BJT packaging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.18 States of the simplied npn BJT model: (a) Cuto, (b) Active, (c) Saturation . . . . 86
5.1 Various operating points within the limits of operation of a BJT transistor. . . . . . . 87
5.2 Fixed-bias BJT circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.3 DC equivalent circuit of the xed-bias circuit in Figure 5.2. . . . . . . . . . . . . . . . 89
5.4 Base-emitter loop of the xed-bias circuit in Figure 5.2. . . . . . . . . . . . . . . . . . 90
5.5 Collector-emitter loop of the xed-bias circuit in Figure 5.2. . . . . . . . . . . . . . . 90
5.6 Saturation regions: (a) actual, (b) approximate. . . . . . . . . . . . . . . . . . . . . . 91
5.7 Determining IC(sat) for the xed-bias conguration.Example 5.0. . . . . . . . . . . . . 92
5.8 Fixed-bias circuit for Example 5.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5.9 Load line of the xed-bias circuit in Figure 5.2. . . . . . . . . . . . . . . . . . . . . . 93
5.10 Movement of the Q-point with increasing level of IB . . . . . . . . . . . . . . . . . . . 94
5.11 Eect of an increasing level of RC on the load line and the Q-point. . . . . . . . . . . 94
5.12 Eect of lower values of VCC on the load line and the Q-point. . . . . . . . . . . . . . 95
5.13 Fixed-bias load line for Example 5.2. . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
5.14 Emitter-stabilized bias circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5.15 DC equivalent circuit of the emitter-stabilized bias circuit in Figure 5.14. . . . . . . . 96
5.16 Base-emitter loop of the emitter-stabilized bias circuit in Figure 5.14: (a) normal circuit,
(b) equivalent circuit for common base current. . . . . . . . . . . . . . . . . . . . . . 97
5.17 Equivalent circuit for common emitter current for the base-emitter loop of the emitter-
stabilized bias circuit in Figure 5.14. . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
5.18 Collector-emitter loop of the emitter-stabilized bias circuit in Figure 5.14. . . . . . . . 98
5.19 Load line of the emitter-stabilized bias circuit in Figure 5.14. . . . . . . . . . . . . . . 99
5.20 Emitter-stabilized bias circuit for Example 5.3. . . . . . . . . . . . . . . . . . . . . . . 99
5.21 Voltage divider bias BJT circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
5.22 DC equivalent circuit of the voltage divider bias circuit in Figure 5.21. . . . . . . . . . 101
5.23 Base-emitter loop of the voltage divider bias circuit in Figure 5.21: (a) normal circuit,
(b) Thévenin equivalent circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
5.24 Thévenin analysis circuits for the circuit in Figure 5.23(a): (a) Open-circuit voltage
calculation, (b) Test-voltage method for Thévenin resistance calculation. . . . . . . . 102
5.25 Voltage-divider bias circuit for Example 5.4. . . . . . . . . . . . . . . . . . . . . . . . 103
5.26 Collector feedback bias circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
5.27 DC equivalent circuit of the collector feedback circuit in Figure 5.26. . . . . . . . . . 104
5.28 Base-emitter loop of the collector feedback circuit in Figure 5.26. . . . . . . . . . . . . 105
5.29 Collector-emitter loop of the collector feedback circuit in Figure 5.26. . . . . . . . . . 105
5.30 Common-collector bias circuit for Example 5.5. . . . . . . . . . . . . . . . . . . . . . 106
5.31 pnptransistor in a voltage-divider bias conguration Example 5.6. . . . . . . . . . . . 107
◦ ◦
5.32 Shift in operating point (Q-point) due to change in temperature: (a) 25 C, (b) 100 C. 108
5.33 Equivalent circuit for the voltage-divider conguration. . . . . . . . . . . . . . . . . . 109
5.34 Active VBE compensation using a reverse-biased diode at the emitter. . . . . . . . . . 113
xi
5.35 Active ICO compensation replacing R2 with a reverse-biased diode. . . . . . . . . . . . 113
5.36 Active IC compensation using a current mirror. . . . . . . . . . . . . . . . . . . . . . 113
5.37 Relay driver in the absence of protective device. . . . . . . . . . . . . . . . . . . . . . 114
5.38 Relay driver protected with a diode across the relay coil. . . . . . . . . . . . . . . . . 114
5.39 Using the BJT as a switch to control the onâo states of a bulb with a limiting
resistor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
5.40 A BJT inverter circuit and its operation. . . . . . . . . . . . . . . . . . . . . . . . . . 115
5.41 Load-line of the inverter circuit in Figure 5.40. . . . . . . . . . . . . . . . . . . . . . . 116
5.42 Dening the time intervals of a pulse waveform. . . . . . . . . . . . . . . . . . . . . . 116
5.43 BJT logic OR gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
5.44 BJT logic AND gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
5.45 BJT logic OR gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
5.46 Voltage level indicator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.1 A voltage-divider common-emitter BJT circuit. . . . . . . . . . . . . . . . . . . . . . 119

6.2 DC and AC equivalent circuits of the common-emitter circuit in Figure 6.1: (a) DC
equivalent circuit (b) AC equivalent circuit. . . . . . . . . . . . . . . . . . . . . . . . 120
6.3 DC equivalent circuit of Figure 6.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
6.4 Input and output swings around the Q-points: (a) input swing (b) output swing. . . . 121
6.5 Distorted output swings: (a) incorrect Q-point (b) incorrect input (i.e., high input). . 122
6.6 AC-equivalent circuit of Figure 6.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6.7 AC-DC load lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.8 Maximum undistorted swing design with Q-point in the middle of the AC load line. . 124
6.9 BJT amplier circuit for Example 6.1. . . . . . . . . . . . . . . . . . . . . . . . . . . 126
6.10 AC-DC load-lines for Example 6.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
7.1 BJT (npn) and FET (n-channel) comparison: (a) current-controlled device (BJT), (b)
voltage-controlled device (FET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
7.2 Water analogy for the FET control mechanism. . . . . . . . . . . . . . . . . . . . . . 132
7.3 n-channel junction eld-eect transistor (JFET) construction. . . . . . . . . . . . . . 133
7.4 JFET at VGS = 0 V and VDS > 0 V: (a) DC biasing, (b) variation of the gate-channel
junction reverse-bias voltages through the channel. . . . . . . . . . . . . . . . . . . . 134
7.5 Pinch-o (VGS = 0 V, VDS = −VP ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
7.6 Output characteristics, i.e., ID versus VDS , for VGS = 0 V. . . . . . . . . . . . . . . . . 135
7.7 Output characteristics of an n-Channel JFET with IDSS = 8 mA and VP = −4 V. . . 136
7.8 p-Channel JFET biasing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7.9 Output characteristics of an p-Channel JFET with IDSS = 6 mA and VP = +6 V. . . . 138
7.10 JFET circuit symbols: (a) n-channel, (b) p-channel. . . . . . . . . . . . . . . . . . . . 138
7.11 Transfer and output characteristics curves together for an n-channel JFET. . . . . . . 139
7.12 Scaled transfer characteristics curve. . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
7.13 n-channel depletion-type MOSFET construction. . . . . . . . . . . . . . . . . . . . . 140
xii
7.14 Change in channel width (and depletion region) for a xed value of VGS (VGS determines
the initial channel width) with VDS > 0. . . . . . . . . . . . . . . . . . . . . . . . . . 141
7.15 Increase (or enhancement) in initial channel width when VGS > 0. . . . . . . . . . . . 142
7.16 Transfer and output characteristics curves together for an n-channel DMOSFET. . . . 142
7.17 p-channel DMOSFET with IDSS = 6 mA and VP = +6 V: (a) construction, (b) transfer
characteristics, (c) output characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 143
7.18 DMOSFET circuit symbols: (a) n-channel, (b) p-channel. . . . . . . . . . . . . . . . . 144
7.19 n-channel enhancement-type MOSFET construction. . . . . . . . . . . . . . . . . . . 144
7.20 Transfer and output characteristics curves together for an n-channel EMOSFET. . . . 145
7.21 p-channel EMOSFET with VGS(T h) = 2 V and k = 0.5 mA/V2 : (a) construction, (b)
transfer characteristics, (c) output characteristics. . . . . . . . . . . . . . . . . . . . . 146
7.22 EMOSFET circuit symbols: (a) n-channel, (b) p-channel. . . . . . . . . . . . . . . . . 147
7.23 n-channel FET summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
7.24 Circuit behaviour of the n-channel FET model: (a) Cuto state, (b) Saturation state 149
8.1 Fixed-bias JFET circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

8.2 DC equivalent circuit (with IG = 0) of the xed-bias conguration in Figure 8.1. . . . 152
8.3 Graphical solution (for transfer load-line and transfer characteristics equations) for the
xed-bias conguration in Figure 8.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
8.4 Self-bias JFET circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
8.5 DC equivalent circuit (with IG = 0) of the self-bias conguration in Figure 8.4. . . . . 154
self-bias conguration in Figure 8.4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
8.7 Self-bias JFET circuit for Example 8.1. . . . . . . . . . . . . . . . . . . . . . . . . . . 156
8.8 Obtaining IDQ graphically for the circuit in Figure 8.7. . . . . . . . . . . . . . . . . . 157
8.9 Voltage-divider bias JFET circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
8.10 DC equivalent circuit of the voltage-divider conguration in Figure 8.9. . . . . . . . . 158
voltage-divider conguration in Figure 8.9. . . . . . . . . . . . . . . . . . . . . . . . . 158
8.12 Voltage-divider bias JFET circuit for Example 8.2. . . . . . . . . . . . . . . . . . . . 159
8.13 Obtaining IDQ graphically for the circuit in Figure 8.12. . . . . . . . . . . . . . . . . 160
8.14 Voltage-divider bias DMOSFET circuit for Example 8.3. . . . . . . . . . . . . . . . . 160
8.15 Obtaining IDQ graphically for the circuit in Figure 8.14 with RS = 750 Ω. . . . . . . . 161
8.16 Obtaining IDQ graphically for the circuit in Figure 8.14 with RS = 150 Ω. . . . . . . . 162
8.17 Voltage-divider bias EMOSFET circuit for Example 8.4. . . . . . . . . . . . . . . . . 162
8.19 Voltage-feedback bias EMOSFET circuit. . . . . . . . . . . . . . . . . . . . . . . . . . 163
8.20 DC equivalent circuit (with IG = 0) of the voltage-feedback conguration in Figure 8.19.164
voltage-feedback conguration in Figure 8.19. . . . . . . . . . . . . . . . . . . . . . . 164
8.22 Voltage-feedback bias EMOSFET circuit for Example 8.5. . . . . . . . . . . . . . . . 165
8.24 Voltage-divider bias JFET circuit for Example 8.6. . . . . . . . . . . . . . . . . . . . 167
8.26 n-channel JFET bias circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
8.27 n-channel MOSFET bias circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
xiii
9.1 AC-DC load lines for FETs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
9.2 Maximum undistorted swing design for FETs with Q-point in the middle of the AC
load line. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
10.1 Two-port voltage-gain amplier model. . . . . . . . . . . . . . . . . . . . . . . . . . . 173

10.2 Complete hybrid equivalent circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
10.3 Common-emitter conguration and its complete hybrid equivalent circuit. . . . . . . . 176
10.4 Common-base conguration and its complete hybrid equivalent circuit. . . . . . . . . 176
10.5 Simplied hybrid equivalent circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
10.6 Approximate hybrid equivalent circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . 177
10.7 Common-emitter simplied hybrid equivalent circuit. . . . . . . . . . . . . . . . . . . 177
10.8 Common-emitter re model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
10.9 Common-base simplied hybrid equivalent circuit. . . . . . . . . . . . . . . . . . . . . 179
10.10Common-base re model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
10.11Common-emitter xed-bias conguration. . . . . . . . . . . . . . . . . . . . . . . . . . 181
10.12AC equivalent circuit of the xed-bias circuit in Figure 10.11. . . . . . . . . . . . . . 181
10.13Small-signal equivalent circuit of the xed-bias circuit in Figure 10.11. . . . . . . . . . 181
10.14Test voltage circuit of Figure 10.13 in order to calculate the output resistance Ro . . . 183
◦
10.15Demonstrating the 180 phase shift between input and output waveforms. . . . . . . . 183
10.16Common-emitter voltage-divider bias conguration. . . . . . . . . . . . . . . . . . . . 184
10.17Small-signal equivalent circuit of the voltage-divider bias circuit in Figure 10.16. . . . 184
10.19Common-emitter unbypassed-emitter bias conguration. . . . . . . . . . . . . . . . . 186
10.20Small-signal equivalent circuit of the unbypassed-emitter bias circuit in Figure 10.19. . 187
10.22Emitter-follower conguration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
10.23Small-signal equivalent circuit of the emitter-follower circuit in Figure 10.22. . . . . . 190
10.25Common-emitter collector feedback bias conguration. . . . . . . . . . . . . . . . . . 192
10.26Small-signal equivalent circuit of the collector feedback bias circuit in Figure 10.25. . 192
10.28Common-base conguration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
10.29Small-signal equivalent circuit of the common-base circuit in Figure 10.28. . . . . . . 195
10.31BJT amplier circuit for Example 10.1. . . . . . . . . . . . . . . . . . . . . . . . . . . 197
10.32DC equivalent circuit of Figure 10.31: (a) as it is (b) Thévenin applied. . . . . . . . . 197
10.33Small-signal equivalent circuit of Figure 10.31. . . . . . . . . . . . . . . . . . . . . . . 198
10.34AC-DC load-lines for Example 10.1with input vs = 100 sin (ωt) mV. . . . . . . . . . . 199
10.35AC-DC load-lines for Example 10.1with input vs = 900 sin (ωt) mV. . . . . . . . . . . 200
11.1 FET small-signal equivalent circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

11.2 FET small-signal equivalent circuit with the voltage-controlled voltage source. . . . . 202
11.3 Graphical denition of the transconductance gm . . . . . . . . . . . . . . . . . . . . . . 203
11.4 Common-source xed-bias conguration. . . . . . . . . . . . . . . . . . . . . . . . . . 204
11.5 Small-signal equivalent circuit of the xed-bias circuit in Figure 11.4. . . . . . . . . . 204
11.6 Test voltage circuit of Figure 11.5 in order to calculate the output resistance Ro . . . . 205
xiv
11.7 Common-source self-bias conguration. . . . . . . . . . . . . . . . . . . . . . . . . . . 206
11.8 Small-signal equivalent circuit of the self-bias circuit in Figure 11.7. . . . . . . . . . . 206
11.9 Test voltage circuit of Figure 11.8 in order to calculate the output resistance Ro . . . . 207
11.10Common-source voltage-divider bias conguration. . . . . . . . . . . . . . . . . . . . . 208
11.11Small-signal equivalent circuit of the voltage-divider bias circuit in Figure 11.10. . . . 208
11.13Common-source unbypassed self-bias conguration. . . . . . . . . . . . . . . . . . . . 210
11.14Small-signal equivalent circuit of the unbypassed self-bias circuit in Figure 11.13. . . . 210
11.16Source-follower conguration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
11.17Small-signal equivalent circuit of the source-follower circuit in Figure 11.16. . . . . . . 213
11.19Common-source drain feedback bias conguration. . . . . . . . . . . . . . . . . . . . . 215
11.20Small-signal equivalent circuit of the drain feedback bias circuit in Figure 11.19. . . . 215
11.22Common-gate conguration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
11.23Small-signal equivalent circuit of the common-gate circuit in Figure 11.22. . . . . . . 217
12.1 First order highpass RC lter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

12.2 Asymptotic Bode plot (scalar) of the rst order highpass RC lter in Figure 12.1. . . 222
12.3 Asymptotic Bode plot (dB) of the rst order highpass RC lter in Figure 12.1. . . . . 223
12.4 Magnitude (top) and phase (bottom) responses of the rst order highpass RC lter in
Figure 12.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
12.5 First order lowpass RC lter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
12.6 Asymptotic Bode plot (dB) of the rst order lowpass RC lter in Figure 12.5. . . . . 226
12.7 Magnitude (top) and phase (bottom) responses of the rst order lowpass RC lter in
Figure 12.5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
12.8 Typical magnitude response of a transistor amplier. . . . . . . . . . . . . . . . . . . 228
12.9 Normalized scalar plot of the magnitude response given in Figure 12.8. . . . . . . . . 229
12.10Normalized decibel plot of the magnitude response given in Figure 12.8. . . . . . . . . 229
12.11A common-emitter voltage-divider bias BJT circuit. . . . . . . . . . . . . . . . . . . . 230
12.12Low-frequency plot for the circuit given in Figure 12.11. . . . . . . . . . . . . . . . . . 232
12.13A common-source self-bias JFET circuit. . . . . . . . . . . . . . . . . . . . . . . . . . 233
12.14Low-frequency plot for the circuit given in Figure 12.13. . . . . . . . . . . . . . . . . . 235
12.15Circuit employed in the derivation of an equation for the Miller input capacitance CMi ,
where Av < 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
12.16Circuit employed in the derivation of an equation for the Miller output capacitance
CMo , where Av < 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
12.17Miller representation of the feedback capacitance in negative gain ampliers. . . . . . 238
12.18A common-emitter voltage-divider bias BJT circuit with the capacitors that aect the
high-frequency response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
12.19 hf e and hf b versus frequency in the high-frequency region. . . . . . . . . . . . . . . . 240
12.20Normalized magnitude response (normalized gain vs. frequency) for the circuit given
in Figure 12.18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
xv
12.21A common-source self-bias JFET circuit with the capacitors that aect the high-
frequency response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
13.1 A cascaded (or multistage) system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

13.2 Overall representation of the system as a single voltage-gain amplier. . . . . . . . . . 244
13.3 A two-stage cascaded system for Example 13.1. . . . . . . . . . . . . . . . . . . . . . 245
13.4 An AC-coupled two-stage FET amplier for Example 13.2. . . . . . . . . . . . . . . . 246
13.5 An AC-coupled two-stage BJT amplier for Example 13.3. . . . . . . . . . . . . . . . 247
13.6 An AC-coupled two-stage BJT amplier for Example 13.4. . . . . . . . . . . . . . . . 248
13.7 A DC-coupled two-stage BJT amplier for Example 13.5. . . . . . . . . . . . . . . . . 249
13.8 AC-DC load-line for the rst transistor in Example 13.5. . . . . . . . . . . . . . . . . 250
13.9 AC-DC load-line for the second transistor in Example 13.5. . . . . . . . . . . . . . . . 251
13.10A DC-coupled two-stage BJT amplier for Example 13.6. . . . . . . . . . . . . . . . . 252
13.11A DC-coupled two-stage BJT amplier for Example 13.7. . . . . . . . . . . . . . . . . 253
13.12A cascode conguration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
13.13A cascode amplier circuit for Example 13.8. . . . . . . . . . . . . . . . . . . . . . . . 255
13.14SSAC equivalent circuit for Example 13.8. . . . . . . . . . . . . . . . . . . . . . . . . 256
13.15Darlington combination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
13.16Single npn transistor representation of the Darlington pair. . . . . . . . . . . . . . . . 257
13.17Feedback pair connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
13.18Single pnp transistor representation of the feedback pair. . . . . . . . . . . . . . . . . 258
xvi
List of Examples
Example 1.1 (Diode Example 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Example 2.1 (Series Clipper with a DC source) . . . . . . . . . . . . . . . . . . . . . . . 30
Example 2.2 (Various Series Clippers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Example 2.3 (Parallel Clipper with a DC source) . . . . . . . . . . . . . . . . . . . . . . 32
Example 2.4 (Diode Limiter or Dual-Diode Parallel Clipper) . . . . . . . . . . . . . . . 32
Example 2.5 (Various Parallel Clippers) . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Example 2.6 (Clamper Example 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Example 2.7 (Clamper Example 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Example 2.8 (Various Clampers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Example 2.9 (Zener Regulator) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Example 3.1 (DC Component of Half-Wave Rectier Output) . . . . . . . . . . . . . . . 45
Example 3.2 (DC Component of Full-Wave Rectier Output) . . . . . . . . . . . . . . . 45
Example 3.3 (DC Component of Triangular Waveform) . . . . . . . . . . . . . . . . . . 46
Example 3.4 (AC Component of Triangular Waveform) . . . . . . . . . . . . . . . . . . 46
Example 3.5 (RMS value of an AC+DC signal) . . . . . . . . . . . . . . . . . . . . . . . 48
Example 3.6 (RMS value of Triangular Waveform) . . . . . . . . . . . . . . . . . . . . . 49
Example 3.7 (RMS value of Half-Wave Rectier Output) . . . . . . . . . . . . . . . . . 50
Example 3.8 (RMS value of Full-Wave Rectier Output) . . . . . . . . . . . . . . . . . . 50
Example 3.9 (RMS value of AC component - Triangular Waveform) . . . . . . . . . . . 50
Example 3.10 (RMS value of AC component - Half-wave Rectier Output) . . . . . . . . 51
Example 3.11 (RMS value of AC component - Full-wave Rectier Output) . . . . . . . . 51
Example 3.12 (Voltage Regulation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Example 3.13 (Ripple Factor of Half-Wave Rectier Output) . . . . . . . . . . . . . . . . 59
xvii
Example 3.14 (Ripple Factor of Full-Wave Rectier Output) . . . . . . . . . . . . . . . . 59
Example 3.15 (Capacitor Filter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Example 3.16 (RC Filter Example 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Example 3.17 (RC Filter Ecample 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Example 3.18 (π Filter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Example 4.1 (Amplication in Common-Base Conguration) . . . . . . . . . . . . . . . 79
Example 4.2 (Determining β) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Example 5.1 (Fixed-Bias BJT Circuit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Example 5.2 (Fixed-Bias Load Line) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Example 5.3 (Emitter-Stabilized Bias BJT Circuit) . . . . . . . . . . . . . . . . . . . . . 99
Example 5.4 (Voltage-Divider Bias BJT Circuit) . . . . . . . . . . . . . . . . . . . . . . 103
Example 5.5 (Common-Collector Bias Circuit) . . . . . . . . . . . . . . . . . . . . . . . 106
Example 5.6 (Voltage-Divider Bias pnp Circuit) . . . . . . . . . . . . . . . . . . . . . . 107
Example 5.7 (Bias Stabilization) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Example 6.1 (AC-DC Load Lines Example 1) . . . . . . . . . . . . . . . . . . . . . . . . 126
Example 8.1 (Self-Bias JFET Circuit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Example 8.2 (Voltage-Divider JFET Circuit) . . . . . . . . . . . . . . . . . . . . . . . . 159
Example 8.3 (Voltage-Divider DMOSFET Circuit) . . . . . . . . . . . . . . . . . . . . . 160
Example 8.4 (Voltage-Divider EMOSFET Circuit) . . . . . . . . . . . . . . . . . . . . . 162
Example 8.5 (Voltage-Feedback EMOSFET Circuit) . . . . . . . . . . . . . . . . . . . . 165
Example 8.6 (p-channel JFET Circuit) . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Example 10.1 (Small-Signal Common-Base Example) . . . . . . . . . . . . . . . . . . . . 197
Example 13.1 (Two-stage Cascaded System) . . . . . . . . . . . . . . . . . . . . . . . . . 245
Example 13.2 (AC-Coupled FET Amplier) . . . . . . . . . . . . . . . . . . . . . . . . . 246
Example 13.3 (AC-Coupled BJT Amplier 1) . . . . . . . . . . . . . . . . . . . . . . . . 247
Example 13.4 (AC-Coupled BJT Amplier 2) . . . . . . . . . . . . . . . . . . . . . . . . 248
Example 13.5 (DC-Coupled BJT Amplier 1) . . . . . . . . . . . . . . . . . . . . . . . . 249
Example 13.8 (Cascode Amplier) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
xviii
List of Homeworks
Homework 1.1 (Diodes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Homework 2.1 (Parallel Clipper 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Homework 2.2 (Parallel Clipper 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Homework 3.1 (Full-Wave Rectiers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Homework 5.1 (Current Mirror) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Homework 6.1 (AC-DC Load Lines) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Homework 7.1 (MOSFET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Homework 13.1 (Two-Stage Cascaded System) . . . . . . . . . . . . . . . . . . . . . . . . . 246
Homework 13.2 (AC-Coupled BJT Amplier) . . . . . . . . . . . . . . . . . . . . . . . . . 248
Homework 13.3 (DC-Coupled BJT Amplier 1) . . . . . . . . . . . . . . . . . . . . . . . . 252
Homework 13.4 (DC-Coupled BJT Amplier 2) . . . . . . . . . . . . . . . . . . . . . . . . 253
Homework 13.5 (Cascode Amplier) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Homework 13.6 (Darlington Pair) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Homework 13.7 (Feedback Pair) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
xix
Textbook
Textbooks:
1. Boylestad and Nashelsky, Electronic Devices and Circuit Theory , Prentice Hall, 11th ed,
2012.
2. Sedra and Smith, Microelectronic Circuits , Oxford Press, 2009 (6th ed.)
Supplementary books:
1. Millman and Halkias, Integrated Electronics , McGraw-Hill.
2. Horowitz and Hill, The Art of Electronics, Cambridge, 3rd ed.
xx
Chapter 1
Semiconductor Diodes
1.1 Circuit Symbol

Diode is a nonlinear two-terminal device whose circuit symbol is like an arrowhead shown in
Figure 1.1 below.
Figure 1.1: Diode circuit symbol.
• Voltage across the diode, VD , is normally dened as the voltage dierence between back end
of the arrowhead and front end of the arrowhead (voltage dierence between terminal A and
terminal B ), i.e.,
VD = VA − VB (1.1.1)
• Current through the diode, ID , is dened in the direction of the arrowhead (owing from terminal
A to terminal B ), i.e.,
ID = IAB (1.1.2)
• Diode is called forward biased (FB) when VA ≥ VB , i.e., VD ≥ 0, and called reverse biased
(RB) when VA < VB , i.e., VD < 0.
1.2 Ideal Diode Model

Ideally diode conducts current in only one direction and blocks current in the opposite direction.
Thus,
1
• Ideal diode is short circuit (i.e., ON) when it is forward biased.
Figure 1.2: Ideal diode is short circuit when it is forward biased.
and open circuit (i.e., OFF) when it is reverse biased.
Figure 1.3: Ideal diode is open circuit when it is reverse biased.
Consequently, characteristics curve of the ideal diode is given by
Figure 1.4: Characteristics curve of the ideal diode.
We can summarize the ideal diode with its state and circuit behaviour with
(
ON, if VD ≥ 0
Ideal diode state = (1.2.3)
OF F, if VD < 0
and
Ideal Diode Model

State Circuit Behaviour Test Condition
ON VD = 0 ID ≥ 0
OFF ID = 0 VD < 0
2
If you make a wrong assumption about the state of the diode, then you will nd that the test
condition will fail (once you calculate the circuit voltage and currents).
• For example, if you have assumed the diode to be ON while it should be OFF, then you will
nd ID < 0, failing the test condition.
• Similarly, if you have assumed the diode to be OFF while it should be ON, then you will nd
VD ≥ 0, failing the test condition.
1.2.1 Determining State of an Ideal Diode

Using circuit behaviour and the test condition for the OFF state, let us devise a method to determine
the state of the ideal diode.
Determining State of an Ideal Diode

1. Obtain the expression for VD in terms of the diode current ID from the electronic
circuit.
2. Insert ID = 0 in to this expression
3. Then, the diode state is given by
(
ON, if VD |ID =0 ≥ 0
OF F, if VD |ID =0 < 0
Example 1.1: Consider the circuit below and nd ID and VD . Assume the diode is ideal.
Figure 1.5: Diode circuit for Example 1.1.
Solution: First we need to determine the state of the ideal diode (i.e., ON or OFF). So, let us
write down the KVL equation and obtain VD
VD = 5 − 5 ID
3
From the equation above, VD |ID =0 = 5 ≥ 0. So, the diode is ON. Thus,
VD = 0 V . . . from circuit behaviour
5 − VD 5−0
ID = = = 1 A.
5 5
1.3 p-n Junction Diodes

In an n-type semiconductor, majority carriers are electrons and minority carriers are
holes.
Similarly, in a p-type semiconductor, majority carriers are holes and minority carriers are
electrons.
When we join n-type and p-type semiconductors (Silicon or Germanium) together, we obtain a
p- n junction as shown in Figure 1.6 below.
Figure 1.6: A p -n junction.
Current formed due to the movement of majority carriers across the junction is called the
majority carrier current, Imajority .
Similarly, current formed due to the movement of minority carriers across the junction is called
theminority carrier current, Is . Note that, minority carrier and majority carrier currents
ow in opposite directions.
When the materials are joined, the negatively charged atoms of the n-type side are attracted to
the positively charged atoms of the p-type side.
Electrons in the n-type material migrate across the junction to the p-type material (electron
ow).
Or, you could also say that holes in the p-type material migrate across the junction to the n-type
material (conventional current ow).
The result is the formation of a depletion layer around the junction intersection, as shown in
Figure 1.7 below.
4
Figure 1.7: Depletion layer in a p -n junction.
Normally, depletion layer is not symmetric around the intersection as the doping levels of n-side
and p-side are usually not the same.
Operating Conditions
• No Bias: No voltage is applied and no current is owing.
• Reverse Bias: Negative voltage (i.e., opposite polarity with the p -n junction) is applied.
• Forward Bias: Positive voltage (i.e., same polarity with the p -n junction) is applied.
1.3.1 No Bias Condition

• No external voltage is applied to the p -n junction as shown in Figure 1.8 below. So, VD = 0 V
and no current is owing ID = 0 A. Under no bias, only a modest depletion layer exists as seen
in Figure 1.8 below.
Figure 1.8: p -n junction under no bias.
• No bias circuit behaviour is also shown in Figure 1.9 below
5
Figure 1.9: Diode behaviour under no bias.
1.3.2 Reverse Bias Condition

• External voltage is applied across the p -n junction in the opposite polarity of the p- and n-type
materials, as shown in Figure 1.10 below.
• This causes the depletion layer to widen as shown below, as electrons in the n-type material are
attracted towards the positive terminal and holes in the p-type material are attracted towards
the negative terminal. Thus, the majority carrier current is zero, i.e., Imajority = 0.
• However, minority carriers move along the electric eld across the junction forming the minority
carrier current, Is . Sometimes, this current is also called as the reverse saturation current.
Figure 1.10: p -n junction under reverse bias.
• Reverse bias circuit behaviour is also shown in Figure 1.11 below
6
Figure 1.11: Diode behaviour under reverse bias.
• Thus, diode current ID under reverse bias is given by
ID = Imajority − Is = 0 − Is = −Is . (1.3.5)
1.3.3 Forward Bias Condition

• External voltage is applied across the p- n junction in the same polarity of the p- and n-type
materials, as shown in Figure 1.12 below.
• The depletion layer is narrow. So, electrons from the n-type material and holes from the p-type
material have sucient energy to cross the junction forming the majority carrier current,
Imajority
• Minority carrier current Is is still present in the opposite direction
Figure 1.12: p -n junction under forward bias.
• Forward bias circuit behaviour is also shown in Figure 1.13 below
7
Figure 1.13: Diode behaviour under forward bias.
• Thus, diode current ID under forward bias is given by
ID = Imajority − Is . (1.3.6)
• Normally Imajority Is , so diode current ID under forward bias is approximately equal to the
majority carrier current, i.e.,
ID ≈ Imajority . (1.3.7)
1.3.4 Diode Characteristic Equation

Empirically obtained diode characteristics curve covering all three operating conditions is
shown in Figure 1.14 below
Figure 1.14: Diode characteristics curve
8
• Diode characteristic equation (also known as the Shockley diode equation) describing the diode
characteristics curve is given below
ID = Is eVD /γ − 1

(1.3.8)
where γ, sometimes expressed as VT , is the thermal voltage given by

kT
γ= (1.3.9)
q
with k, q and T
being the Boltzman constant, the charge of an electron and temperature in
k
Kelvins, respectively. Note that, is constant given by
q
k
= η 8.6173 × 10−5 V/K (1.3.10)
q
where η=1 for Ge and η = 2 for Si for relatively low levels of diode current (at or below the
knee of the curve) and η = 1 for Ge and Si for higher levels of diode current (in the rapidly
increasing section of the curve). We can safely assume η = 1 for most cases.
• Under forward bias, diode characteristic equation simplies (as eVD /γ 1) to the simplied
forward bias diode equation below
ID ≈ Is eVD /γ (1.3.11)
• Under reverse bias, diode characteristic equation simplies (as eVD /γ 1) to the following
ID ≈ −Is (1.3.12)
• Note that, γ only depends on the temperature (expressed in Kelvin units).
So, thermal voltage γ at room temperature T = 300 K (i.e., T = 27 ◦ C) is given by
γ = γ |T =300 K = 26 mV. (1.3.13)
If we take the room temperature as T = 25 ◦ C, then thermal voltage becomes
γ |T =298 K = 25 mV. (1.3.14)
NOTE: Temperature in Kelvin (T ) is obtained from the temperature in Celsius (TC ) as follows
T = TC + 273 (1.3.15)
9
1.3.5 Zener Region (or Avalanche Breakdown Region)
Figure 1.15: Zener region (or avalanche breakdown region)
Even though the scale of Figure 1.14 is in tens of volts in the negative region, there is a point where
the application of too negative a voltage will result in a sharp change in the characteristics, as shown
in Figure 1.15. The current increases at a very rapid rate in a direction opposite to that of the positive
voltage region. The reverse-bias potential that results in this dramatic change in characteristics is
called the Zener potential and is given the symbol VZ .
As the voltage across the diode increases in the reverse-bias region, the velocity of the minority
carriers responsible for the reverse saturation current Is will also increase. Eventually, their velocity
and associated kinetic energy will be sucient to release additional carriers (i.e., avalanche eect)
through collisions with otherwise stable atomic structures. That is, an ionization process will result
whereby valence electrons absorb sucient energy to leave the parent atom. These additional carriers
can then aid the ionization process to the point where a high avalanche current is established and the
avalanche breakdown region determined.
The avalanche region (VZ ) can be brought closer to the vertical axis by increasing the doping levels
in the p- and n-type materials. However, as VZ decreases to very low levels, such as 5 V, another
mechanism, called Zener breakdown, will contribute to the sharp change in the characteristic.
It occurs because there is a strong electric eld in the region of the junction that can disrupt the
bonding forces within the atom and generate carriers generally via tunnelling (sometimes called as
tunnelling breakdown) of the majority carriers under reverse-bias electric eld when the valence band
of the highly doped p-region is aligned with the conduction band of the highly doped n-region.
Although the Zener breakdown mechanism is a signicant contributor only at lower levels of VZ , this
sharp change in the characteristic at any level is called the Zener region and diodes employing this
unique portion of the characteristic of a p -n junction are called Zener diodes.
10
1.3.6 Peak Inverse Voltage (PIV) Rating
Avalanche breakdown region of the semiconductor diode must be avoided if the diode is supposed
to work as an ON and OFF device.
The maximum reverse-bias potential that can be applied before entering the avalanche break-
peak inverse voltage (referred to simply as the PIV rating ) or the
down region is called the
peak reverse voltage (denoted by PRV rating).
If an application requires a PIV rating greater than that of a single unit, a number of diodes of
the same characteristics can be connected in series.
Similarly, diodes can be also connected in parallel to increase the current-carrying capacity.
1.3.7 Forward Bias Turn-On Voltage (VD(ON ))

The point at which the diode changes from No Bias condition to Forward Bias condition happens
when the electron and holes are given sucient energy to cross the p -n junction. This energy
comes from the external voltage applied across the diode.
This voltage (can be deduced from the diode characteristics curve) is called the turn-on voltage
or the threshold voltage, and denoted by VD(ON ) (VT or V0 notations are also used).
The forward bias voltage required to turn on the diode for a
◦ Silicon diode: VD(ON ) = 0.7 V

◦ Germanium diode: VD(ON ) = 0.3 V
11
1.3.8 Temperature Eects
Figure 1.16: Change of diode characteristics with temperature
• As temperature increases it adds energy to the diode. From Figure 1.16 above, as temperature
increases
◦ It reduces the required turn-on voltage (VD(ON ) ) in forward bias condition,

◦ It increases the amount of reverse saturation current (Is ) in reverse bias condition,
◦ It increases the avalanche breakdown voltage in reverse bias condition.
• Germanium diodes are more sensitive to temperature variations than Silicon diodes.
1.3.9 Load Line and Operating Point (Q-point)
(a)
(b)
Figure 1.17: Series diode conguration: (a) circuit, (b) diode characteristics curve.
12
From Figure 1.17(a) above, we obtain
VD = E − ID R (1.3.16)
• We can rearrange the circuit equation (1.3.16) above to get ID on the left-hand side of the
equation, i.e.,
−1 E
ID = VD + (1.3.17)
R R
• This equation obtained from the diode circuit is called the load line equation.
The load line equation gives us all the possible current (ID ) values for all the possible voltage
(VD ) values obtained across the diode in a given circuit.
• Once we draw the load line over the diode characteristics curve given in Figure 1.17(b), and the
intersection point will give us the solution (IDQ , VDQ ) of the diode current and diode voltages
ID and VD for the given circuit, respectively. The result is shown in Figure 1.18 below.
Figure 1.18: Drawing the load line and nding the point of operation.
• This plot is called the load line plot. Also, the intersection point of the load line and the diode
characteristics curve is called the operating point or the Q-point specied by the (IDQ , VDQ )
pair. Note that Q stands for quiescent (i.e., still).
• For some examples, see Examples 2.1, 2.2 and 2.3 in the Boylestad and Nashelsky textbook (8th
ed.).
13
A load line plot like Figure 1.18 is actually the graphical way of solving the diode charac-
teristics equation
ID = IS eVD /γ − 1

and the electrical circuit equation, i.e., load line equation
VD E
ID = − +
R R
simultaneously. Load line plots are very practical and more ecient than solving these two
equations analytically.
1.3.10 DC Resistance (Static Resistance)
Figure 1.19: Determining the DC resistance of a diode at a particular operating point.
• For a specic applied DC voltage VDQ , the diode will have a specic current IDQ , and conse-
quently a specic resistance RDQ . The amount of resistance RDQ , depends on the applied DC
voltage and current.
• For a given operating point as shown in Figure 1.19 above, we can nd the DC resistance as
follows

VD
RDQ =
ID Q-point
(1.3.18)
VDQ
=
IDQ
14
1.3.11 AC Resistance (Dynamic Resistance)
Figure 1.20: Dening the dynamic or AC resistance around an operating point
• Dynamic resistance rd is determined around a Q-point (see Figure 1.20 above) as the ratio of
given very small voltage variation ∆Vd to the current variation ∆Id obtained, i.e.,

∆V
rd ∼
d
= .
∆Id Q-point
• As the magnitude of these small voltage and current variations go to zero this equation for the
dynamic resistance rd approaches to the following partial derivative

∂VD
rd = (1.3.19)
∂ID Q-point
• In the forward bias region, we can use the simplied forward bias diode equation
ID ≈ Is eVD /γ
as given in (1.3.11)
Then, the forward bias dynamic resistance is obtained as

∂VD 1 1
rd = = ≈
∂ID Q-point
∂ID
1
Is eVDQ /γ
∂VD Q-point
γ | {z }
IDQ
γ
=
IDQ
15
The forward bias dynamic resistance depends on the Q-point current IDQ and the temperature,
i.e.,
γ
rd = (1.3.20)
IDQ
We know that γ = 26 mV at room temperature (300 K), so the diode dynamic resistance can be
calculated as
26 mV
rd = (1.3.21)
IDQ
• In the reverse bias region, diode current is approximately constant
ID ≈ −Is
as given in (1.3.12)
So, the reverse bias dynamic resistance is essentially innite, i.e.,
rd = ∞. (1.3.22)
1.3.12 DC and Small-Signal AC (SSAC) Analysis
Figure 1.21: Diode circuit with AC and DC sources.
• Here, it is given that VDC − peak(vac (t)) > VD(ON ) and VDC >> peak(vac (t)).
First condition ensures that the diode state do not change for any value of the AC signal (i.e.,
diode is always ON) and the second condition ensures that diode behaviour is approximately
linear around the Q-point.
The two conditions together provide linearity (approximately), so that we can employ the
superposition theorem. Remember that, superposition theorem can only be employed in
linear systems.
• Then, we can apply the superposition theorem and express the diode current and voltages
as follows
iD (t) = IDQ + id (t) (1.3.23)
vD (t) = VDQ + vd (t). (1.3.24)
16
• Diode is always ON and magnitude of the AC signal is very small compared to the DC signal
(e.g., 10 mV vs. 10 V). law of superposition and perform DC analysis
So, we can apply the
and small-signal AC (SSAC) analysis separately, that is, we obtain IDQ and id (t) independently
using dierent circuits.
• We obtain DC equivalent circuit by killing the AC sources as shown in Figure 1.22 below
Figure 1.22: DC equivalent circuit of the circuit in Figure 1.21.
In DC analysis, IDQ and VDQ are found using the load-line analysis, i.e., by solving the diode
characteristic equation and load-line equation simultaneously.
• We obtainSSAC equivalent circuit by killing the DC sources and replacing the diode with
its SSAC model (rd ) where
26 mV
rd =
IDQ
as shown in Figure 1.23 below
Figure 1.23: SSAC equivalent circuit of the circuit in Figure 1.21.
• In SSAC analysis, diode is replaced by its dynamic resistance rd and we can nally nd id (t)
and vd (t) as follows
vac (t)
id (t) = (1.3.25)
R + rd
rd
vd (t) = vac (t). (1.3.26)
R + rd
17
1.3.13 Average AC Resistance
Figure 1.24: Determining the average AC resistance between indicated limits.
• Average AC resistance can be determined by picking two points on the characteristic curve
developed for a particular circuit where the voltage and current variations (i.e., ∆Vd and ∆Id )
are large, as shown in Figure 1.24 above. It is used to develop the piecewise-linear diode model.
• Thus, the average AC resistance rav is calculated as
∆VD
rav = (point-to-point) (1.3.27)
∆ID
18
1.4 Piecewise-Linear Diode Model
Figure 1.25: Piecewise-linear characteristics curve (blue line on the left) and piecewise-linear equivalent
circuit (on the right) of the diode.
• Piecewise-linear approximation of the diode characteristics curve is obtained and depicted as

the blue lines on the left of Figure 1.25 above.
• Similarly, obtained piecewise-linear equivalent circuit is shown on the right of Figure 1.25 above.
• Here, rav is the forward bias average AC resistance (i.e., internal resistance) of the diode.
1.5 Simplied Diode Model
Figure 1.26: Simplied characteristics curve (on the left) and simplied equivalent circuit (on the
right) of the diode.
• Simplied diode characteristics curve is obtained and shown on the left of Figure 1.26 above.
• Similarly, obtained simplied equivalent circuit is shown on the right of Figure 1.26 above.
19
We can summarize the simplied diode model with its state and circuit behaviour with
(
ON, if VD ≥ VD(ON )
Diode state = (1.5.28)
OF F, if VD < VD(ON )
and
Simplied Diode Model

ON VD = VD(ON ) ID ≥ 0
OFF ID = 0 VD < VD(ON )
• For the ideal diode model, the turn-on voltage is zero, i.e., VD(ON ) = 0 V.
In this course, we will mostly use the simplied diode model unless otherwise stated.
1.5.1 Determining State of a Diode

• Using circuit behaviour and the test condition for the OFF state, let us devise a method to
determine the state of a diode under simplied diode model.
Determining State of a Diode

1. Obtain the expression for VD in terms of the diode current ID from the electronic
circuit.
2. Insert ID = 0 in to this expression
3. Then, the diode state is given by
(
ON, if VD |ID =0 ≥ VD(ON )
OF F, if VD |ID =0 < VD(ON )
Example 1.2: Consider the circuit below and nd ID and VD with VD(ON ) = 0.7 V and E > 0.7 V.
20
Solution: First we need to determine the state of the diode (i.e., ON or OFF). So, let us write
down the KVL equation and obtain VD
VD = E − ID R
From the equation above, VD |ID =0 = E ≥ VD(ON ) . So, the diode is ON. Thus,
VD = VD(ON ) = 0.7 V . . . from circuit behaviour
E − VD E − 0.7
ID = =
R R
VR = E − VD = E − 0.7
Thus, our diode circuitin Figure 1.27 is simplied to the circuit shown in Figure 1.28 below
Figure 1.28: Simplied circuit for the diode circuit in Figure 1.27.
Note that IR = ID .
Example 1.3: Consider the circuit below and nd ID and VD with VD(ON ) = 0.7 V and E > 0.7 V.
21
Solution: First we need to determine the state of the diode (i.e., ON or OFF). So, let us write
down the KVL equation and obtain VD
VD = −E − ID R
From the equation above, VD |ID =0 = −E < VD(ON ) . So, the diode is OFF. Thus,
ID = 0 A . . . from circuit behaviour
VD = −E − ID R = −E
VR = −ID R = 0 V
Thus, our diode circuitin Figure 1.29 is simplied to the circuit shown in Figure 1.30 below
Figure 1.30: Simplied circuit for the diode circuit in Figure 1.29.
Note that IR = −ID = 0 A.
Example 1.4: Consider the circuit below and nd I1 , Vo , ID1 and ID2 with VD(ON ) = 0.7 V and
D1 ≡ D2 .
22
Solution: First we need to determine the state of the diodes (i.e., ON or OFF). As the diodes
are parallel, we let us make the following denitions
VD = VD1 = VD2
ID = ID1 + ID2 = I1
So, let us write down the KVL equation and obtain VD
VD = E − ID R = 10 − 0.33k ID
From the equation above, VD |ID =0 = 10 ≥ VD(ON ) . So, both diodes are ON.
Thus,
VD1 = VD(ON ) = 0.7 V . . . from circuit behaviour
VD2 = VD(ON ) = 0.7 V . . . from circuit behaviour
Vo = VD = 0.7 V
E − VD 10 − 0.7
I1 = = = 28.18 mA
R 0.33k
I1
ID1 = ID2 = = 14.09 mA . . . as D1 ≡ D2
2
Homework 1.1: What will happen if D2 is replaced by a Germanium diode and D1 remains as a
Silicon diode?
1.6 Diode Specication Sheets

Data about a diode is presented uniformly for many dierent diodes. This makes cross-matching of
diodes for replacement or design easier.
Some of the key elements is listed below:
1. VF : forward voltage at a specic current and temperature
2. IF : maximum forward current at a specic temperature
23
3. IR : maximum reverse current at a specic temperature
4. PIV or PRV or VBR: maximum reverse voltage at a specic temperature
5. Power Dissipation: maximum power dissipated at a specic temperature
6. C: Capacitance levels in reverse bias
7. trr : reverse recovery time
8. Temperatures: operating and storage temperature ranges
1.6.1 Semiconductor Notation
Figure 1.32: Semiconductor diode notation.
• Anode is abbreviated as A.
• Cathode is abbreviated as K (because the Cathode end of the diode symbol looks like a backwards
K).
Examples of some diode types and packagings are shown in Figure 1.33 below.
24
Figure 1.33: Some diode types and packagings.
1.6.2 Capacitance
Figure 1.34: Transition and diusion capacitance versus applied bias for a Silicon diode.
25
• In reverse bias, the depletion layer is very large. The diode's strong positive and negative
polarities create capacitance, CT . The amount of capacitance depends on the reverse voltage
applied.
• In forward bias, storage capacitance or diusion capacitance (CD ) exists as the diode voltage
increases
1.7 Other Types of Diodes

Other types of diodes we like to mention are listed below
1. Zener Diode
2. Light Emitting Diode
1.8 Zener Diode
Figure 1.35: Zener diode symbol.
• A Zener is a diode operated in reverse bias at the Peak Inverse Voltage (PIV) called the Zener
voltage (VZ ).
• Common Zener voltages: 1.8 V to 200 V.
• We are going to cover Zener diodes in more detail later in the course.
26
1.9 Light Emitting Diode (LED)
Figure 1.36: Circuit symbol of an LED.
• This diode when forward biased emits photons. These can be in the visible spectrum.
• The forward bias turn-on voltage is higher, usually around 2-3 V.

• A Litronix 7-segment LED display is shown in Figure 1.37 below
Figure 1.37: Litronix 7-segment LED display
• Relative intensity of each color versus wavelength appears in Figure 1.38 below.
Figure 1.38: Relative intensity versus wavelength.
27
Chapter 2
Diode Applications
2.1 Clippers
Clipper diode circuits have the ability to clip o a portion of the input signal without distorting
the remaining part of the alternating waveform.
Depending on the orientation of the diode, the positive or negative region of the input signal is
clipped o.
There are two general categories of clippers: series and parallel. The series conguration is
dened as one where the diode is in series with the load as shown in Figure 2.1 below, while the
parallel variety has the diode in a branch parallel to the load.
Figure 2.1: A series clipper circuit.
• Let us write down the KVL equation for the circuit in Figure 2.1 above
vi − vD − iD R = 0 ⇒ vD = vi − iD R (2.1.1)
As vD |iD =0 = vi , we have
(
ON, if vi ≥ VD(ON )
OF F, if vi < VD(ON )
28
As the output vo is across the resistor R, i.e., vo = iD R = vi − vD , we have
(
vi − VD(ON ) , if vi ≥ VD(ON )
vo = (2.1.3)
0, if vi < VD(ON )
• Let us plot equation (2.1.3) above, as a voltage transfer characteristics (VTC) curve, i.e.,
output versus input plot, in order to understand the clipper behaviour visually, as shown in
Figure 2.2 below.
Figure 2.2: Voltage transfer characteristics (VTC) curve of the series clipper circuit Figure 2.1.
• Let us analyse the operation of the series clipper circuit Figure 2.1 for a sinusoidal input, using
the ideal diode model, i.e., VD(ON ) = 0.
Figure 2.3: Positive half-cycle operation of the series clipper circuit in Figure 2.1.
Figure 2.4: Negative half-cycle operation of the series clipper circuit in Figure 2.1.
As we see from Figure 2.3 and Figure 2.4 above, negative half-cycle portion of the signal is
clipped o while the positive half-cycle portion remains intact.
29
Example 2.1: By adding a DC source to the circuit as shown in Figure 2.5, the voltage required
to forward bias the diode can be changed.
Figure 2.5: A series clipper circuit with a DC supply.
Consequently, the output will be given by
(
vi + 5 V − VD(ON ) , if vi ≥ VD(ON ) − 5 V
vo = (2.1.4)
0, if vi < VD(ON ) − 5 V
Let us sketch the output of the series clipper circuit Figure 2.5 for a sinusoidal input, using the
ideal diode model, as shown in Figure 2.6 below.
Figure 2.6: Input and output of the series clipper circuit in Figure 2.5.
30
Example 2.2: Various series clipper examples are shown in Figure 2.7 below (diodes are ideal).
Figure 2.7: Various series clipper examples (diodes are ideal).
2.1.1 Parallel Clippers

By taking the output across the diode shown in Figure 2.8 below, the output equals to the input
voltage when the diode is not conducting.
Figure 2.8: A parallel clipper circuit.
Hence, the output for this circuit will be given by
(
VD(ON ) , if vi ≥ VD(ON )
vo = (2.1.5)
vi , if vi < VD(ON )
Example input and output waveforms of the parallel clipper circuit Figure 2.8 for the ideal
diode model are shown in Figure 2.9 below.
31
Figure 2.9: Sample input and output waveforms of the parallel clipper circuit in Figure 2.8.
Example 2.3: A DC source can also be added to change the diode's required forward bias
voltage, as shown in Figure 2.10
Figure 2.10: A parallel clipper circuit with a DC supply.
Consequently, the output will be given by

(
−VD(ON ) − VBB , if vi ≤ −VD(ON ) − VBB
vo = (2.1.6)
vi , if vi > −VD(ON ) − VBB
Homework 2.1: Draw the VTC diagram of the parallel clipper circuit given in Figure 2.10
above.
Homework 2.2: Draw the output waveform and the VTC diagram when the diode is reversed.
Example 2.4: For the circuit shown in Figure 2.11 below, nd the output for a sinusoidal input
vi (t) = Vm sin(2πt/T ) where (VB1 , VB2 ) < Vm and draw the VTC diagram.
Figure 2.11: A diode limiter circuit.
Consequently, the output is given below and also shown in Figures 2.12(a) and 2.12(b) below

VD(ON ) + VB1 ,
 if vi ≥ VD(ON ) + VB1 ,
vo = −VD(ON ) − VB2 , if vi ≤ −VD(ON ) − VB2 , (2.1.7)

vi , else.

32
(b)
(a)
Figure 2.12: Outputs of the circuit in Figure 2.11: (a) VTC diagram, (b) output waveform.
Example 2.5: Various parallel clipper examples are shown in Figure 2.13 below (diodes are
ideal).
Figure 2.13: Various parallel clipper examples (diodes are ideal).
2.2 Clampers
Clamper circuits clamp a signal to dierent DC levels. The circuit must have a capacitor, a diode,
and a resistive element as shown in Figure 2.14 below, but it can also employ an independent
DC supply to introduce an additional shift.
33
Figure 2.14: A clamper circuit.
Throughout the analysis, we will assume that for all practical purposes the capacitor will fully
discharge in ve time constants, i.e., 5τdischarge , where time constant τdischarge = RC .
The magnitude of R and C time constant τdischarge = RC is large
must be chosen such that the
enough capacitor does not discharge signicantly
to ensure that the voltage across the
during the interval the diode is nonconducting.
For the circuit in Figure 2.14 above, the diode state is given by
(
ON, if vi ≥ VD(ON ) + VC
OF F, if vi < VD(ON ) + VC
where VC is the voltage across the capacitor C.
The clamper output is given by

vo = vi − VC . (2.2.9)
• Consequently, when the capacitor is charged at the maximum voltage, i.e., VC = Vm − VD(ON )
and diode is OFF, the clamper output will be
vo = vi − (Vm − VD (ON )). (2.2.10)
IMPORTANT: The clamper shifts the signal in the direction of the diode arrowhead
by an amount of (Vm − VD(ON ) ).
• Let us generate steps for the clamper operation for the circuit in Figure 2.14 above, assuming
capacitor is fully discharged initially, i.e., at t = 0, using the ideal diode model.
1. The diode will be ON in the rst VC = 0 and the capacitor will
positive half cycle as
charge up very quickly to the peak value Vm with a time constant τcharge = Crav ∼= 0 where
∼
rav = 0 Ω is the internal resistance of the diode as shown in Figure 2.15 below.
34
Figure 2.15: Charging operation of the clamper circuit in Figure 2.14.
2. Once the capacitor is charged, i.e., VC = Vm . then the diode turns OFF, as shown in
Figure 2.16 below.
Figure 2.16: Discharging operation of the clamper circuit in Figure 2.14.
3. Capacitor will discharge until the input waveform gets larger than the capacitor voltage,
T
i.e., vi (t) > vC (t). Thus, the discharging period ( ) must be much smaller than the
2
fully discharge constant 5τdischarge in order to keep the voltage across the capacitor almost
constant at VC ∼
= Vm , i.e.,
T
5τdischarge (2.2.11)
2
5τdischarge ≥ 50 T2

So, if take , then we obtain the following condition for the clamping
operation
τdischarge ≥ 5T (2.2.12)
where T is the period of the input signal vi .
• For a clamping operation, selected capacitor C and resistor R values should satisfy
the discharge condition in (2.2.12).
• IMPORTANT: If it is not explicitly stated we are going to assume that capacitor is already
charged, e.g., VC = Vm − VD(ON ) .
Example 2.6: Consider the clamping circuit below and plot the output waveform. Assume the
diode is ideal.
35
Figure 2.17: A clamper circuit with a square wave input.
Solution: As this is a clamping circuit, i.e., τdischarge ≤ 5T , we obtain the following output
vo = vi − V + VD(ON )
where VD(ON ) = 0 V. The resulting waveform is shown in Figure 2.18 below.
Figure 2.18: Output of the circuit given in Figure 2.17.
Example 2.7: Consider the clamping circuit below and plot the output waveform. Assume the
diode is ideal.
Figure 2.19: A clamper circuit with a sinusoidal input.
Solution: Assuming the capacitor is already charged at VC = −Vm + VD(ON ) + VBB = −20 +
0 + 10 = −10 V, we obtain the following output
vo = vi − (−Vm + VD(ON ) + VBB ) = vi + Vm − VD(ON ) − VBB = vi + 20 − 0 − 10

= vi + 10 V.
36
The resulting waveform is shown in Figure 2.20 below.
Figure 2.20: Output of the circuit given in Figure 2.19.
Example 2.8: Various clamper examples are shown in Figure 2.21 below (diodes are ideal).
Figure 2.21: Various clamper examples (diodes are ideal and capacitors are charged).
2.3 Voltage Multiplier Circuits

2.3.1 Peak Rectier
Once we consider a clamper circuit and take the output over the capacitor instead of the diode,
we obtain the peak rectier circuit shown in Figure 2.22 below producing a DC output at peak
value of the input signal.
37
Figure 2.22: A peak rectier circuit.
Corresponding input and output are also shown in gures 2.23(a) and 2.23(b) below. The

capacitor is charged to the maximum value Vm − VD(ON ) in the rst positive half cycle (i.e.,
between 0 and T /4), then the diode turns OFF and capacitor cannot discharge retaining the
charged value. This value is equal to the peak value Vm for the ideal diode.
(b)
(a)
Figure 2.23: For the circuit in Figure 2.22: (a) input waveform, (b) output waveform.
• When a load RL is connected, the discharge constant τdischarge = RL C should have a very high
T

value compared to the half period of the signal, otherwise ripples are observed at the output
2
voltage, i.e., RL should have a very large value.
• Using a combination of diodes and capacitors we can step up the output voltage of rectier
circuits. These circuits (some listed below) are called voltage multiplier circuits.
1. Voltage Doubler
2. Voltage Tripler
3. Voltage Quadrupler
2.3.2 Voltage Doubler

A voltage doubler circuit is shown in Figure 2.24 below.
38
Figure 2.24: Voltage doubler circuit.
Using the ideal diode model, operation of the voltage doubler circuit are shown for the rst
positive and negative half-cycles in gures 2.25(a) and 2.25(b) below, respectively. After the
rst cycle, both diodes retain their OFF state.
(a) (b)
Figure 2.25: Operation of the circuit in Figure 2.24 at (a) rst positive half-cycle, and (b) rst negative
half-cycle.
2.3.3 Voltage Tripler and Quadrupler

By adding more diode-capacitor networks the voltage can be increased as shown in Figure 2.26
below.
Figure 2.26: Voltage tripler/quadrupler circuit.
39
2.4 Zener Diode
Zener diode operates in reverse bias (RB) at the Zener Voltage (VZ ). Zener diode is ON when
it operates on the Zener region, i.e., −VD ≥ VZ , and is OFF when 0 < −VD < VZ , as shown in
gures 2.27(a) and 2.27(b) below.
(a) (b)
Figure 2.27: Zener diode operation: (a)ON (b) OFF.
• Although Zener diode behaves like a normal diode in forward bias, Zener diode is not normally
used in forward bias.
• Zener diode also needs some minimum current IZ(min) in order to turn ON, although voltage
threshold −VD ≥ VZ is satised. If not given, IZ(min) = 0 A.
• There is also a maximum power limit PZ(max) for the Zener diode. Note that, maximum power
PZ(max)
limit results in a maximum current limit IZ(max) given by IZ(max) = .
VZ
2.4.1 Zener Regulator
Figure 2.28: A general Zener diode circuit.
In a Zener regulator circuit likein Figure 2.28 above, Zener diode must be always ON in order
to continuously regulate the voltage over the load RL . So, let us derive the necessary equations
for the two limiting factors IZ(min) and IZ(max) using
IZ = I1 − IL (2.4.13)
40
• Let us rst write down the equation for IZ(min)
IZ(min) = I1(min) − IL(max) (2.4.14)
where IL(max) and I1(min) are given by
VZ
IL(max) = (2.4.15)
RL(min)
Vs(min) − VZ
I1(min) = (2.4.16)
R1(max)
• Similarly, we can also write down the equation for IZ(max)
IZ(max) = I1(max) − IL(min) (2.4.17)
where IL(min) and I1(max) are given by
VZ
IL(min) = (2.4.18)
RL(max)
Vs(max) − VZ
I1(max) = (2.4.19)
R1(min)
• Note that the values of VZ , IZ(min) and IZ(max) (or PZ(min) and PZ(max) ) are specied in the
specication sheet (or data sheet) of a Zener diode.
Example 2.9: (2004-2005 MI) In the gure below, Vs is an unregulated voltage that varies
between 6 V and 7 V while the Zener diode voltage is VZ = 5 V. The load resistor RL can have
a value from 100 Ω to ∞ (i.e., open circuit). Also you can take IZ(min) ∼
= 0 A.
a) Find the maximum value of R1 so that the load voltage VL would be still kept constant
at 5 V for all values of RL and Vs .
b) Provide a symbolic expression for the maximum power dissipated by the Zener diode.
c) Determine the minimum value of R1 so that the power dissipated by the Zener diode
never exceeds 1 W for all values of RL and Vs .
Figure 2.29: Zener diode circuit for Example 2.9.
Solution:
41
a) As IZ(min) = I1(min) − IL(max) = 0, I1(min) = IL(max) , i.e.,
Vs(min) − VZ VZ
=
R1(max) RL(min)
Vs(min) − VZ 6−5
R1(max) = RL(min) = 100 = 20 Ω.
VZ 5
b) PZ(max) = VZ IZ(max) .
c) It is given that PZ(max) = 1 W, so
PZ(max) 1
IZ(max) = = = 0.2 A
VZ 5
VZ 5
IL(min) = = = 0A
RL(max) ∞
I1(max) = IZ(max) + IL(min) = IZ(max) = 0.2 A
Vs(max) − VZ 7−5
R1(min) = = = 10 Ω.
I1(max) 0.2
2.4.2 Other Zener Diode Regulators

• A single Zener diode can limit one side of a sinusoidal waveform to the Zener voltage while
clamping the other side to near zero as shown in Figure 2.30 below
Figure 2.30: Single Zener diode clipper.
• With two opposing Zeners, the waveform can be limited to the Zener voltage on both polarities
as shown in Figure 2.31 below.
Figure 2.31: Dual Zener diode clipper.
2.4.3 Zener Diode Parameters

The basic parameters of a Zener diode are:
42
a) Obviously, the Zener voltage must be specied. The most common range of Zener voltage is 3.3
volts to 75 volts, however voltages out of this range are available.
b) A tolerance of the specied voltage must be stated. While the most popular tolerances are 5%
and 10%, more precision tolerances as low as 0.05% are available. A test current (IZ(test) ) must
be specied with the voltage and tolerance.
c) The power handling capability must be specied for the Zener diode. Popular power ranges are:
0.25, 0.5, 1, 5, 10, and 50 Watts.
2.5 Practical Applications of Diode Circuits

• Rectier Circuits
◦ Conversions of AC to DC for DC operated circuits
◦ Battery Charging Circuits
• Simple Diode Circuits

◦ Protective Circuits against
− Overcurrent
− Polarity Reversal
− Currents caused by an inductive kick in a relay circuit
• Zener Circuits
◦ Overvoltage Protection
◦ Setting Reference Voltages
43
Chapter 3
Rectiers and Voltage Regulating Filters
3.1 Properties of Electrical Signals

3.1.1 DC Component (Average Value) and AC Component
• Every (periodic) signal has a DC component and an AC component, i.e.,
v(t) = VDC + vac (t) (3.1.1)
where VDC is the DC component and vac (t) is the AC component.
• DC component VDC is dened as the time-average or mean of the signal within one period,
i.e.,
Z T
1
VDC = Vavg = v(t)dt (3.1.2)
T 0
where T is the period of the signal.
VDC is the voltage value displayed for v(t) on a DC voltmeter.
• AC component vac (t) is the zero-mean time-varying component of the signal given by
vac (t) = v(t) − VDC (3.1.3)
IMPORTANT: In this course, we are going to use

1. capital letters for both quantity symbols and subscripts of DC components, e.g., IDQ ,
2. small letters for both quantity symbols and subscripts of AC components, e.g., id ,
3. small letters for quantity symbols and capital letters for subscripts of AC+DC signals,
e.g., iD where iD = IDQ + id .
44
Example 3.1: Let us calculate the DC component of the half-wave rectier output shown in
Figure 3.1 below.
Figure 3.1: Ideal half-wave rectier output of a sinusoidal input vi (t) = Vm sin(2πt/T ).
Solution: DC component of the signal given by its time-average in one period. However in the
case of the half-wave rectier output shown in Figure 3.1 above, second half-cycle of the signal
is zero. So, we only need to integrate rst half-cycle of the signal.
1 T /2
Z
VDC = Vm sin(2πt/T )dt
T 0
Z π
1 2πt
= Vm sin θ dθ . . . using change of variables with θ=
2π 0 T
Vm T
= [− cos θ]π0 . . . and dt = dθ.
2π 2π
Vm
= (3.1.4)
π
∼
= 0.318 Vm (3.1.5)
Example 3.2: Let us calculate the DC component of the full-wave rectier output shown in
Figure 3.2 below.
Figure 3.2: Ideal full-wave rectier output of a sinusoidal input vi (t) = Vm sin(2πt/T ).
Solution: DC component of the signal given by its time-average in one period. However in the
case of the full-wave rectier output shown in Figure 3.2 above, the period of the output signal
45
T
is .
2
2 T /2
Z
VDC = Vm sin(2πt/T )dt
T 0
Z π
1 2πt
= Vm sin θ dθ . . . using change of variables with θ=
π 0 T
Vm T
= [− cos θ]π0 . . . and dt = dθ.
π 2π
2Vm
= (3.1.6)
π
∼
= 0.636 Vm (3.1.7)
Example 3.3: Let us calculate the DC component of the triangular waveform shown in Fi-
gure 3.3 below.
Figure 3.3: Triangular waveform.
Solution: DC component of the signal given by its time-average in one period. In this case the
integral of the waveform in one period is the area of the triangle present (Vm T /2) in one period
as seen in Figure 3.2 above.
1 T
Z
VDC = v(t)dt
T 0

1 Vm T
= (3.1.8)
T 2
Vm
= (3.1.9)
2
Example 3.4: Let us nd the AC component of the triangular waveform shown in Figure 3.3.
Solution: AC component of the signal is obtained by subtracting the DC component, i.e.,
Vm
vac (t) = v(t) − VDC = v(t) − . (3.1.10)
2
46
Thus, the AC component of the triangular waveform is plotted as shown in Figure 3.4 below.
Figure 3.4: AC component of the triangular waveform in Figure 3.3.
3.1.2 Eective Value (RMS Value)

• Average power or mean power is dened as the time-average of the instantaneous power over
a period, i.e.,
Z T
1
Pavg = p(t)dt (3.1.11)
T 0
where p(t) is the instantaneous power and T is the period of p(t).
• The idea of eective current and voltage values comes from the need for writing the average
power as a multiple of voltage and current values just like the Watt's law, i.e.,
Pavg = Veective Ieective (3.1.12)
where Veective and Ieective are the eective voltage and current values, respectively.
Eective Voltage Value

• Let us obtain the eective voltage value Veective by dening average power over a resistor R
1 T v 2 (t)
Z
Pavg = dt
T 0 R
1 1 T 2
Z
= v (t)dt (3.1.13)
R T 0
| {z }
2
Veective
V2
= eective (3.1.14)
R
• Thus, eective voltage value Veective is given as the root-mean-square (RMS) of the voltage
signal, i.e.,
s
Z T
1
Veective = Vrms = v 2 (t)dt (3.1.15)
T 0
47
Vrms is the voltage value displayed for v(t) on an AC voltmeter.
Eective Current Value

• Let us obtain the eective current value Ieective by dening average power over a resistor R
1 T 2
Z
Pavg = i (t)Rdt
T 0
Z T
1 2
= i (t)dt R (3.1.16)
T 0
| {z }
2
Ieective
2
= Ieective R (3.1.17)
• Thus, eective current value Ieective is given as the root-mean-square (RMS) of the current
signal, i.e.,
s
Z T
1
Ieective = Irms = i2 (t)dt (3.1.18)
T 0
Irms is the voltage value displayed for i(t) on an AC ammeter.
Example 3.5: Calculate the RMS value Vrms of the mixed signal
v(t) = A + B cos ωt.
Solution: Let us nd

2
Vrms rst where ω = 2πf = 2π/T
1 T
Z
2
Vrms = (A + B cos ωt)2 dt
T 0
1 T 2
Z
+ B 2 cos2 ωt dt

= A + (2AB
((( cos
(ωt
((
T 0
1 2 T B 2 T
Z
= A t 0 + (1 + cos 2ωt) dt
T 2 0
T
B 2 B 2 sin 2ωt

2

=A + +
2 2T T 0
2
B
= A2 +
2
So,
r
B2
Vrms = A2 +
2
• We can generalize the result of Example 3.5 for the RMS value Vrms of a general AC+DC signal
v(t) where
v(t) = VDC + vac (t),
48
as the combined RMS equation given below
q
2 2
Vrms = VDC + Vac(rms) (3.1.19)
Example 3.6: Calculate the RMS value of the triangular waveform shown in Figure 3.5 below.

 2Vm t,

0 ≤ t < T /2
v(t) = T
2V
2Vm − m t, T /2 ≤ t < T

T
Figure 3.5: Triangular waveform and its analytical expression.
Solution: Let us calculate

2
Vrms by using integration by parts
Z T /2 2 Z T 2 !
2 1 2Vm 2Vm
Vrms = t dt + 2Vm − t dt
T 0 T T /2 T
!
1 4Vm2 T /2 2
Z Z T
2 2 1 2
= t dt + 4Vm 1 − t + 2 t dt
T T2 0 T /2 T T
T /2 T
4Vm2 t3 4Vm2 t2 t3

= + t− +
T3 3 0 T T 3T 2 T /2
4Vm2
T3 4Vm2 T

3T 7T
= + − +
T3 24 T 2 4 24
2
Vm
=
3
So, the RMS value of the triangular waveform is given by

Vm
Vrms = √ (3.1.20)
3
49
Example 3.7: Calculate the RMS value of the ideal half-wave rectier output given in Fi-
gure 3.1.
Solution: Let us rst calculate the

2
Vrms
1 T /2 2 2
Z
2
Vrms = Vm sin (2πt/T )dt
T 0
1 2 π 2
Z
2πt
= V sin θ dθ . . . using change of variables θ=
2π m 0 T
Vm2 π 1
Z
= (1 −
cos
2θ

)dθ . . . using trigonometric identities
2π 0 2
Vm2
=
4
So, the RMS value of the ideal half-wave rectier output is given by
Vm
Vrms = (3.1.21)
2
Example 3.8: Calculate the RMS value of the ideal full-wave rectier output given in Figure 3.2.
Solution: Let us rst calculate the

2
Vrms
2 T /2 2 2
Z
2
Vrms = Vm sin (2πt/T )dt
T 0
1 2 π 2
Z
2πt
= V sin θ dθ . . . using change of variables θ=
π m 0 T
Vm2 π 1
Z
= (1 −
cos
2θ

)dθ . . . using trigonometric identities
π 0 2
Vm2
=
2
So, the RMS value of the ideal full-wave rectier output is given by
Vm
Vrms = √ ∼= 0.707 Vm (3.1.22)
2
Example 3.9: Calculate the RMS value Vac(rms) of the AC component of the triangular wa-
veform shown in Figure 3.4.
Solution: We are going to use the combined RMS equation given in (3.1.19) with the alre-
ady calculated DC and RMS values of the triangular waveform given in (3.1.9) and (3.1.20),
50
respectively as follows
2 2 2
Vac(rms) = Vrms − VDC
2 2
Vm Vm
= √ −
3 2
2 2
V V
= m− m
3 4
2
V
= m.
12
So, the RMS value of the AC component of the triangular waveform is given by
Vm
Vac(rms) = √ (3.1.23)
2 3
Example 3.10: Calculate the RMS value Vac(rms) of the AC component of the ideal half-wave
rectier output.
Solution: We are going to use the combined RMS equation given in (3.1.19) with the already
calculated DC and RMS values of the ideal half-wave rectier output given in (3.1.4) and (3.1.21),
respectively as follows
2 2 2
2 2
Vm Vm
= −
2 π
2 2
V V
= m − m2
4 π
So, the RMS value of the AC component of the half-wave rectier output is given by
r
1 1
Vac(rms) = Vm − 2 ∼
= 0.386 Vm (3.1.24)
4 π
Example 3.11: Calculate the RMS value Vac(rms) of the AC component of the ideal full-wave
rectier output.
Solution: We are going to use the combined RMS equation given in (3.1.19) with the already
calculated DC and RMS values of the ideal full-wave rectier output given in (3.1.6) and (3.1.22),
respectively, as follows
2 2 2
2 2
Vm 2Vm
= √ −
2 π
2 2
V 4V
= m − 2m
2 π
So, the RMS value of the AC component of the full-wave rectier output is given by
r
1 4
Vac(rms) = Vm − 2 ∼
= 0.308 Vm (3.1.25)
2 π
51
3.2 Half-Wave Rectier
• Generating a waveform with a non-zero mean value, i.e., non-zero DC component, from an
AC waveform (i.e., a zero-mean time-varying signal) is called rectication. The circuits which
perform rectication are called rectiers. This is a crude AC to DC conversion.
• A half-wave rectier recties only half-cycle of the waveform, i.e., circuits conducts only for
one-half of the AC cycle, maintaining the average of the output signal non-zero.
• A half-wave rectier circuit is the same as the series clipper circuit shown in Figure 3.6
below.
Figure 3.6: A half-wave rectier circuit.
• Sample input and ideal output waveforms for an half-wave rectier such as given inFigure 3.6
are given in Figure 3.7 below.
Figure 3.7: Input and ideal output waveforms for the half-wave rectier given in Figure 3.6.
52
• The DC voltage output of the half-wave rectier is the DC component of the output waveform
and as calculated before in (3.1.4) it is given by
1
VDC(half-wave) = Vm ∼
= 0.318 Vm (3.2.26)
π
where Vm is the peak voltage of the input sinusoidal signal.
• The output of the half-wave rectier for VD(ON ) = 0.7 V is shown in Figure 3.8 below
Figure 3.8: Input and output waveforms for the half-wave rectier when VD(ON ) = 0.7 V.
When VD(ON ) 6= 0, the DC voltage output of the half-wave rectier is approximately equal to
1 1
VDC(half-wave) ∼
= Vm − VD(ON ) = 0.318 Vm − 0.5 VD(ON ) (3.2.27)
π 2
• When the diode is OFF, maximum negative voltage between the terminals of the diode is
the negative peak value −Vm . So, the peak-inverse-voltage for the half-wave rectier is given by
PIV(half-wave rectier) = Vm (3.2.28)
Thus, we need to select a diode with a PIV rating greater than Vm , i.e., PIVdiode > Vm , to use
in our half-wave rectier circuit.
3.3 Full-Wave Rectier

• A full-wave rectier recties both cycles of the waveform producing a higher DC output as
shown in Figure 3.9 below
Figure 3.9: Input and ideal output waveforms of the full-wave rectier.
53
• The DC voltage output of the full-wave rectier is the DC component of the output waveform
and as calculated before in (3.1.6) it is given by
2
VDC(full-wave) = Vm ∼
= 0.636 Vm (3.3.29)
π
where Vm is the peak voltage of the input sinusoidal.
Full-Wave Rectier Circuits

There are two types of full-wave rectier circuits:
1. Center-Tapped Transformer Full-Wave Rectier
2. Full-Wave Bridge Rectier
3.3.1 Center-Tapped Transformer Full-Wave Rectier

Center-tapped transformer full-wave rectier shown in Figure 3.10 below requires a center-tapped
(CT) transformer to establish the replica of the input signal across each section of the secondary
of the transformer and then combining two half-wave rectiers together where the two half-wave
rectiers operate on opposite cycles of the input signal.
Figure 3.10: Center-tapped transformer full-wave rectier.
Here, D1 operates on the positive half-cycle and D2 operates on the negative half-cycle of input
vi .
• Using the ideal diode model, operation of the center-tapped transformer full-wave rectier are
shown for positive and negative cycles in Figure 3.11 and Figure 3.12 below, respectively.
54
Figure 3.11: Positive half-cycle operation of the center-tapped transformer full-wave rectier in Fi-
gure 3.10.
Figure 3.12: Negative half-cycle operation of the center-tapped transformer full-wave rectier in Fi-
gure 3.10.
• When the diodes are OFF, maximum negative voltage between the terminals of the diodes
are twice the negative peak value. So, the peak-inverse-voltage for the center-tapped transformer
full-wave rectier is given by
PIV(center-tapped) = 2Vm (3.3.30)
• When the diodes are not ideal, i.e., VD(ON ) 6= 0, the DC voltage output of the center-tapped
transformer full-wave rectier is approximately equal to
2
VDC(center-tapped) ∼
= Vm − VD(ON ) = 0.636 Vm − VD(ON ) (3.3.31)
π
3.3.2 Full-Wave Bridge Rectier

The most popular circuit to achieve full-wave rectication is four diodes in a bridge conguration
as shown in Figure 3.13 below. The popularity of the rectier comes from the fact that it
eliminates the need for a transformer.
55
Figure 3.13: Full-wave bridge rectier.
Here, D2 and D3 operate on the positive half-cycle, and D4 and D1 operate on the negative
half-cycle of input vi .
• Using the ideal diode model, operation of the full-wave bridge rectier are shown for positive
and negative cycles in Figure 3.14 and Figure 3.15 below, respectively.
Figure 3.14: Positive half-cycle operation of the full-wave bridge rectier in Figure 3.13.
Figure 3.15: Negative half-cycle operation of the full-wave bridge rectier in Figure 3.13.
• When the diodes are OFF, maximum negative voltage between the terminals of the diodes
are equal to the negative peak value. So, the peak-inverse-voltage for the full-wave bridge rectier
is given by
PIV(bridge) = Vm (3.3.32)
• The positive half-cycle operation and full output of the full-wave bridge rectier for VD(ON ) =
0.7 V is shown in Figure 3.16 below
56
Figure 3.16: Positive-half cycle operation and full output of the full-wave bridge rectier when
VD(ON ) = 0.7 V.
When the diodes are not ideal, i.e., VD(ON ) 6= 0, the DC voltage output of the full-wave bridge
rectier is approximately equal to
2
VDC(bridge) ∼
= Vm − 2VD(ON ) = 0.636 Vm − 2VD(ON ) (3.3.33)
π
3.4 Rectier Summary

Summary of the rectier circuits is given in Table 3.1 below.
Table 3.1: Rectier Summary
Rectier Ideal Output Realistic Output PIV

Half-Wave Rectier VDC = 0.318 Vm VDC = 0.318 Vm − 0.5 VD(ON ) Vm
Center-Tapped Transformer VDC = 0.636 Vm VDC = 0.636 Vm − VD(ON ) 2Vm
Full-Wave Rectier
Full-Wave Bridge Rectier VDC = 0.636 Vm VDC = 0.636 Vm − 2VD(ON ) Vm

Note: Vm is the peak value of the sinusoidal input voltage.
Homework 3.1: Compare the center-tapped transformer rectier and bridge rectier listing their
advantages and disadvantages. Which one is more preferable and why?
57
3.5 Voltage Regulation and Ripple Factor
Figure 3.17: Block diagram showing parts of a power supply.
A block diagram containing the parts of a typical power supply and the voltages at various
points in the unit is shown in shown in Figure 3.17 above.
1. The mains AC voltage (120 Vrms 60 Hz in USA, and 230 Vrms 50 Hz in Europe), is con-
nected to a transformer, which steps that AC voltage down to the level for the desired DC
output.
2. A diode rectier then provides a full-wave rectied voltage.
3. Full-wave rectied voltage is then ltered by a simple capacitor lter to produce a DC

voltage. This resulting DC voltage usually has some ripple or AC voltage variation.
4. Finally, obtained DC voltage is regulated to obtain a desired xed DC voltage. The regula-
tion circuit takes a DC voltage and provides a somewhat lower DC voltage, which remains
the same even if the input DC voltage varies or the output load changes. Although one
of the simplest regulators is a Zener regulator, usually an integrated circuit (IC) voltage
regulator unit is used for voltage regulation.
3.5.1 Voltage Regulation

• An important factor in a power supply is the amount the DC output voltage changes over a range
of loads. The voltage provided at the output under no-load condition (no current drawn from
the supply) is reduced when load current is drawn from the supply (under load). The amount
the DC voltage changes between the no-load (NL) and full-load (FL) conditions is described by
a factor called voltage regulation (VR) given by
VN L − VF L
%VR = × 100 (3.5.34)
VF L
Example 3.12: A DC voltage supply provides 60 V when the output is unloaded. When
connected to a load, the output drops to 56 V. Calculate the value of voltage regulation.
Solution:
VN L − VF L 60 − 56
%VR = × 100 = × 100 = 7.1%.
VF L 56
• The smaller the voltage regulation, the better the operation of the voltage supply circuit.
58
3.5.2 Ripple Factor
Figure 3.18: Filter voltage waveform showing DC and ripple voltages.
• The ltered output shown in Figure 3.18 above has a DC value and some AC variation (ripple).
The smaller the AC variation with respect to the DC level, the better the lter circuit's operation
(or the better the power supply). This ratio is called the ripple factor (r) expressed by
Vr(rms)
%r = × 100 (3.5.35)
VDC
where Vr(rms) the RMS value of the AC ripple voltage vr (t) uctuating around the DC value VDC
at the output.
Example 3.13: Calculate the ripple factor of the ideal half-wave rectier output shown in
Figure 3.1.
Solution: From (3.1.5) and (3.1.24), we can obtain the ripple factor as
Vac(rms)(half-wave) 0.386 Vm
%r(half-wave) = × 100 = × 100 = 121%.
VDC(half-wave) 0.318 Vm
Example 3.14: Calculate the ripple factor of the ideal full-wave rectier output shown in
Figure 3.2.
Solution: From (3.1.7) and (3.1.25), we can obtain the ripple factor as
Vac(rms)(full-wave) 0.308 Vm
%r(full-wave) = × 100 = × 100 = 48%.
VDC(full-wave) 0.636 Vm
59
3.6 Capacitor Filter
Figure 3.19: Simple capacitor lter.
• A very popular lter circuit is the capacitor-lter circuit shown in Figure 3.19 above. A capacitor
is connected at the rectier output, and a DC voltage is obtained across the capacitor.
Figure 3.20: Capacitor lter after a center-tapped transformer full-wave rectier.
• So, a full-wave rectier integrated with a capacitor lter is shown in Figure 3.20 above.
(a) (b)
Figure 3.21: Capacitor lter operation: (a) ideal full-wave rectier output, (b) ltered output voltage.
Figure 3.21(a) above shows the output voltage of the ideal full-wave rectier before the signal
is ltered,
60
while Figure 3.21(b) above shows the resulting waveform after the lter capacitor is connected
at the rectier output.
Notice that the ltered waveform is essentially a DC voltage with some ripple (or AC variation).
(b)
(a)
Figure 3.22: Capacitor lter output after a full-wave rectier: (a) actual output, (b) approximate
output where ripple waveform is approximated by a triangular waveform.
• When we analyse the capacitor lter output shown in Figure 3.22(a) above,
Time T1 is the time during which diodes of the full-wave rectier conduct, charging the capacitor
up to the peak rectier voltage, Vm .
Time T2 is the time interval during which the rectier voltage drops below the peak voltage,
and the capacitor discharges through the load.
Since the charge-discharge cycle occurs for each half-cycle for a full-wave rectier, the period of
the rectied waveform is T /2 (one-half the input signal frequency).
• The ripples of the ltered voltage can be approximated by a triangular waveform as shown
in Figure 3.22(b) above, where the output waveform has a DC level VDC and a triangular ripple
voltage Vr(rms) as the capacitor charges and discharges.
61
3.6.1 Ripple Factor of Capacitor Filter
Figure 3.23: Capacitor lter output (after a full-wave rectier) with charging and discharging timings.
Let us derive the expression for the ripple factor of the capacitor lter output shown in Figure 3.23
above
1. Charging period T1 and discharging period T2 together constitute the whole period T /2. Thus,
T
T2 = − T1 (3.6.36)
2
2. Peak-to-peak ripple voltage Vr(p-p) is given by
Vr(p-p) = 2 (Vm − VDC ) (3.6.37)
3. We can express discharge current (i.e., load current) IDC as follows
∆V Vr(p-p)
IDC = C =C (3.6.38)
∆t T2
4. Using similar triangles we can obtain an expression for T1

Vr(p-p) ∼ Vm
= (3.6.39)
T1 T /4
Vr(p-p) T
T1 ∼= (3.6.40)
Vm 4
∼ 2 (Vm − VDC ) T
= . . . from (3.6.37), (3.6.41)
Vm 4
∼ T V DC T
= − (3.6.42)
2 2Vm
5. We can obtain T2 from Step 1 and Step 3, i.e., from (3.6.37) and (3.6.42)
VDC T
T2 = (3.6.43)
2Vm
62
6. We can obtain Vr(p-p) from Step 3 and Step 5, i.e., from (3.6.38) and (3.6.43)
IDC VDC IDC VDC

Vr(p-p) = = (3.6.44)
2f C Vm fripple C Vm
where fripple = 2f and f = 1/T is the frequency of the input AC voltage.
7. Similarly, we can obtain Vr(rms) from Step 6 by using the RMS value of an AC triangular waveform
given in (3.1.23)
Vr(p-p) √
Vr(rms) = √ . . . i.e., Vr(p) = 3Vr(rms) (3.6.45)
2 3
IDC VDC
= √ (3.6.46)
2 3fripple C Vm
8. Thus, ripple factor r is given by
Vr(rms)
r= (3.6.47)
VDC
1 VDC
= √ . . . as VDC = IDC RL (3.6.48)
2 3fripple CRL Vm
√ VDC
Due to Vr(p) = 3Vr(rms) and Vm = VDC + Vr(p) , we obtain
Vm
as
VDC VDC 1 1 1
= = Vr(p)
= √ = √ (3.6.49)
Vm VDC + Vr(p) 3V r(rms) 1 + 3r
1 + VDC 1 + VDC
VDC 1
9. For light load (i.e., r < 6.5%), = √ ratio approaches to one, i.e.,
Vm 1 + 3r
VDC ∼
= 1.
Vm
So, expression for the ripple factor r reduces to
1
r∼
= √ (3.6.50)
2 3fripple CRL
10. Hence when

VDC ∼
= 1, peak-to-peak ripple voltage Vr(p−p) becomes
Vm
IDC
Vr(p-p) ∼
= (3.6.51)
fripple C
Thus, the larger the capacitor the smaller the ripple voltage and ripple factor.
63
3.6.2 Diode Conduction Period and Peak Diode Current
Larger values of capacitance provide less ripple and higher average voltage, thereby providing
better lter action. From this, one might conclude that to improve the performance of a capacitor
lter it is only necessary to increase the size of the lter capacitor. The capacitor, however, also
aects the peak current drawn through the rectifying diodes, and as will be shown next, the
larger the value of the capacitor, the larger the peak current drawn through the rectifying diodes.
Recall that the diodes conduct during period T1 , during which time the diode must provide the
necessary average current to charge the capacitor. The shorter this time interval, the larger the
amount of the charging current. Figure 3.24 shows this relation for a half-wave rectied signal
(it would be the same basic operation for full-wave). Notice that for smaller values of capacitor,
with T1 larger, the peak diode current is less than for larger values of lter capacitor.
(a) (b)
Figure 3.24: Capacitor lter output voltage and diode current waveforms for a half-wave rectier: (a)
small C, (b) large C.
Since the total discharge must equal to total charge, the following relation can be used (assuming
constant diode current during charging period):
IDC T2 = Ipeak T1 (3.6.52)
T2
Ipeak = IDC (3.6.53)
T1
T
where T2 ∼
=T for a half-wave rectier as shown in Figure 3.24 above. Similarly, T2 ∼
= for a
2
full-wave rectier.
• Note that fripple = f for a half-wave rectier as seen from Figure 3.24, and fripple = 2f for a
full-wave rectier as seen from Figure 3.22.
64
Example 3.15: (2004-2005 MI) A power-supply circuit is needed to deliver 0.1 A and an average
of 15 V to a load. The AC source available is 230 Vrms with a frequency of 50 Hz. Assume that
a full-wave rectier circuit is to be used with a smoothing capacitor in parallel with the
load as shown in the gure below. The peak-to-peak ripple voltage is to be 0.4 V. Allow
VD(ON ) = 0.7 V for the forward diode voltage drop.
Find
a) The turns-ratio n = N1 /N2 that is needed,
b) The load resistor RL , and
c) The approximate value of the smoothing capacitor C.
Figure 3.25: Capacitor lter circuit for Example 3.15.
Solution: For a full-wave bridge rectier, DC voltage drop due to the diodes is 2VD(ON ) .
a) As VDC = 15 V and Vr(p-p) = 0.4 V, peak value Vm of the AC voltage at the secondary
terminal of the transformer is given by
Vm = VDC + Vr(p-p) /2 + 2VD(ON ) = 15 + 0.4/2 + 2(0.7) = 16.6 V.
Thus the turns ratio n is given by
√ √
VAC(p) 2VAC(rms) 2(230)
n= = = = 19.6.
Vm Vm 16.6
b) As VDC = 15 V and IDC = 0.1 A, RL is given by
VDC 15
RL = = = 150 Ω.
IDC 0.1
c) As
VDC
= 15 ∼
= 1, then Vr(p-p) ∼
= IDC
. So, capacitor C is given by
VDC +Vr(p) 15.2 fripple C
IDC IDC 0.1

C= = = = 2.5 mF.
fripple Vr(p-p) 2f Vr(p-p) 2(50)(0.4)
65
3.7 Additional RC Filter
Figure 3.26: Additional RC lter stage.
It is possible to further reduce the amount of ripple across a lter capacitor by using an additional
RC lter section as shown in Figure 3.26 above.
The purpose of the added RC section is to pass most of the DC component while attenuating
(reducing) as much of the AC component as possible. Figure 3.27 shows a full-wave rectier
with capacitor lter followed by an RC lter section.
Thus, adding an RC section will further reduce the ripple voltage and decrease the surge current
through the diodes.
Figure 3.27: Center-tapped transformer full-wave rectier and RC lter circuit.
As ripple component of the capacitor lter is much smaller than the DC component, the opera-
tion of the lter circuit can be analysed using superposition for the DC and AC components
of signal.
0
• So, we are going to rst use the DC equivalent circuit (i.e., DC analysis) in order to obtain VDC .
• Then, we are going to use the AC equivalent circuit (i.e., AC analysis) in order to obtain Vr(0 rms) .
66
3.7.1 DC Operation
Figure 3.28: DC equivalent circuit of the additional RC lter stage in Figure 3.26.
DC equivalent circuit, where both capacitors are open-circuit for DC operation, of the additional
RC lter stage is shown in Figure 3.28 above.
Thus, DC output of the RC lter stage is given by
0 RL
VDC = VDC (3.7.54)
R + RL
where VDC is the DC output of the capacitor lter.
3.7.2 AC Operation
Figure 3.29: AC equivalent circuit of the additional RC lter stage in Figure 3.26.
AC equivalent circuit of the additional RC lter stage is shown in Figure 3.29 above.
So, AC output of the RC lter stage is given by

1
Vr(0 rms) = V
R r(rms)
(3.7.55)

1 + 0

Z
67
where Z0 is the parallel impedance of the capacitor C2 and the load RL , i.e.,
Z 0 = ZC ||RL (3.7.56)
RL XC
|Z 0 | = p 2 (3.7.57)
RL + XC2
1
and ZC = −jXC with XC = and ω = 2πfripple .
ωC2
Simplication
• If R L XC , e.g., RL ≥ 5XC , then |Z 0 | ∼
= XC .
Consequently, Vr(0 rms) could be written as
1 XC
Vr(0 rms) ∼
=s Vr(rms) = p Vr(rms) (3.7.58)
R2 R2 + XC2
1+ 2
XC
R2
• Additionally if 1, then the above expression further reduces to
XC2
XC
Vr(0 rms) ≈ Vr(rms) (3.7.59)
R
Example 3.16: Consider the circuit below with fripple = 50 Hz, C2 = 10 µF and RL = 2 kΩ,
and calculate XC2 and |ZC2 ||RL |.
Solution: Let us calculate XC and |Z 0 | where XC = XC2 and Z 0 = ZC2 ||RL

1 1
XC = = = 318 Ω,
2πfripple C2 2π(50)(10µ)
RL XC (2k)(318)
|Z 0 | = p 2 2
=p = 314 Ω.
RL + XC (2k)2 + (318)2
Thus, the assumption |Z 0 | ∼

= XC holds when RL ≥ 5XC .
68
Example 3.17: Consider the circuit in Figure 3.31 below with fmains = 50 Hz.
a) Find the DC and AC voltages over the load,
b) Find the ripple factors, %r and %r0 values,
c) Find the voltage regulation factor %VR.
Solution: As a full-wave rectier is used fripple = 2fmains = 100 Hz.

0
a) Let us nd VDC rst
0 RL 5k
VDC = VDC = 150 = 136.4 V.
R + RL 0.5k + 5k
We see that DC voltage value dropped by 13.6 V.
Now, let us nd XC

1 1
XC = = = 159 Ω
2πfripple C2 2π(100)(10µ)
As RL XC ,
XC 159
Vr(0 rms) = p V
2 r(rms)
=√ 15 = 4.55 V
2
R + XC 5002 + 1592
We see that ripple voltage reduced by a factor of 3.3 times.
b) Ripple factors before %r and after %r0 are given by
Vr(rms) 15
%r = × 100 = × 100 = 10%
VDC 150
0
Vr(0 rms) 4.55
%r = 0
× 100 = × 100 = 3.34%
VDC 136.4
We see that ripple factor reduced by a factor of 3 times.
69
c) Voltage regulation %VR is given by
VN L − VF L 150 − 136.4
%VR = × 100 = × 100 = 9.97%.
VF L 136.4
• If we want the DC voltage drop to be smaller but AC ripple drop to be higher, we can achieve
it by replacing the resistor R with a component such that its DC resistance is small while its
AC resistance is high. Such a component is an inductor.
3.8 π -Filter
Figure 3.32: π -lter stage.
By replacing resistor R in the RC lter with inductor L, we obtain a π -lter as shown in

Figure 3.32 above.
While DC resistance R` of the coil is small and is AC reactance XL is high.
Example 3.18: For the π -lter shown in Figure 3.32, the output DC voltage and current are
given as 200 V and 50 mA. Also VDC(C1 ) = 210 V, Vr(C1 ) = 12 Vrms and the frequency of the
0
ripple voltage fripple = 100 Hz. In order to satisfy r ≤ 2%, determine the values of RL , R` , L
and C2 . Explain any assumptions you make. NOTE: R` denotes the DC resistance of the coil.
Solution: As
0
VDC = 200 V and
0
IDC = 50 mA, the load RL is given by
0 0
RL = VDC /IDC = 200/50m = 4 kΩ.
0 RL
We know that VDC = V , so
R` +RL DC
R` is given by
0 0
R` = (VDC − VDC )RL /VDC = (210 − 200)/200 = 200 Ω.
Let us nd the ripple voltage requirement as Vr(0 rms) ≤ (2%)VDC

0
= (2%)(200) = 4 Vrms
Vr(0 rms) ≤ 4 Vrms.
Let us select XC RL as XC = RL /10 = 4k/10 = 400 Ω.
70
Note that ZL = R` + jXL , and assuming XL R` we will take ZL ∼
= jXL .
XL − XC Vr(rms) 12
We know that ≥ 0 = = 3, so XL is given by
XC Vr(rms) 4
XL ≥ 4XC = (4)(400) = 1.6 kΩ
So, let us select XL = 1.7kΩ and nd the value of inductance L as follows
XL XL 1.7k
L= = = = 2.7 H.
ω 2πfripple 2π(100)
As XC = 400 Ω, we can nd the value of capacitance C as follows
1 1 1
C= = = = 4 µF.
ωXC 2πfripple XC 2π(100)(400)
71
Chapter 4
Bipolar Junction Transistor (BJT)
4.1 Bipolar Junction Transistor

Bipolar junction transistor (BJT) is a three-layer semiconductor device consisting of either
two n- and one p-type layers of material or two p- and one n-type layers of material. The former
is called an npn transistor, and the latter is called a pnp transistor. Both are shown in Figure 4.1
below with the proper DC biasing.
The terminals have been indicated by the capital letters E for emitter, C for collector, and
B for base. Emitter is the source of the majority carriers (electrons in an npn transistor and
holes in a pnp transistor). In simple wording, majority carriers are emitted from the emitter
and collected by the collector.
The term bipolar reects the fact that holes and electrons participate in the current conduction
process.
(a) (b)
Figure 4.1: Types of transistors: (a) pnp, (b) npn.
72
The basic operation of the transistor will now be described using the pnp transistor. The ope-
ration of the npn transistor is exactly the same if the roles played by the electron and hole are
interchanged. In Figure 4.2(a) below pnp transistor has been redrawn by removing the bias of
base-collector junction (keeping base-emitter junction forward-biased). The depletion region has
been reduced in width due to the applied bias, resulting in a heavy ow of majority carriers
from emitter to base (i.e., holes from emitter to base).
Let us now remove the bias of base-emitter junction (keeping base-collector junction reverse-
biased) as shown in Figure 4.2(b) below. Recall that the ow of majority carriers (electrons
from base to collector) is zero, resulting in only a minority-carrier ow (i.e., holes from base
to collector).
(a) (b)
Figure 4.2: Biasing a transistor: (a) base-emitter forward-biased, (b) base-collector reverse-biased.
Once the base-emitter junction is forward-biased, and base-collector junction reverse-

biased at the same time.
Then, most of the holes (majority carriers of the emitter region) coming from emitter region
to the base region are swept away to the collector region as holes are the minority carriers for
the base region and base-collector junction is reverse biased.
This basic transistor operation is shown in Figure 4.3 below as
IE = IC + IB (4.1.1)
where collector current IC is comprised of two components
IC = IC(majority) + ICO(minority) ∼
= IC(majority) (4.1.2)
Here, the minority-current component is called the leakage current with the symbol ICO
(reverse-bias IC current with emitter terminal open). Generally IC is measured in milliamperes
and ICO is measured in microamperes or nanoamperes. ICO , like Is for a reverse-biased diode,
is temperature sensitive and must be examined carefully when applications of wide temperature
ranges are considered.
73
Figure 4.3: Current ow in a properly biased pnp transistor.
4.2 Common-Base Conguration

The common-base terminology is derived from the fact that the base is common to both the
input and output sides of the conguration. In addition, the base is usually the terminal closest
to, or at, ground potential.
On the BJT circuit symbol, an arrow is always drawn at the emitter leg of the transistor
as shown in Figures 4.4(a) and 4.4(b) below in the forward direction of the base-emitter pn
junction like the diode symbol. Hence, from the direction of the arrow we can determine type
of the transistor, i.e., npn or pnp.
74
(a) (b)
Figure 4.4: Notation and symbols used with the common-base conguration: (a) npn transistor, (b)
pnp transistor.
4.2.1 Input and Output Characteristics

To fully describe the behavior of a three-terminal device requires two sets of characteristicsone
for the input parameters and the other for the output side.
The input set for the common-base amplier relates an input current (IE ) to an input voltage
(VBE ) for various levels of output voltage (VCB ) as shown in Figure 4.5(a) below.
The output set relates an output current (IC ) to an output voltage (VCB ) for various levels of
input current (IE ) as shown in Figure 4.5(b) below. The output set of characteristics has three
basic regions of interest, the active, cuto, and saturation regions. The active region is the
region normally employed for linear ampliers.
75
(a) (b)
Figure 4.5: Characteristics of an npn common-base amplier: a) Input characteristics, b) Output

characteristics.
4.2.2 Three Modes of Operation
Figure 4.6: Output characteristics of a common-base amplier.
• Cut-O: The amplier is basically o: IE = 0 A, IC = ICBO ∼

= 0A and IB ∼
= 0 A.
◦ Base-Emitter junction: reverse-biased, i.e., OFF.
◦ Base-Collector junction: reverse-biased, i.e., OFF.
• Active: Operating region of the amplier: IC ∼

= IE and VBE ∼
= VBE(ON ) .
76
◦ Base-Emitter junction: forward-biased, i.e., ON.
◦ Base-Collector junction: reverse-biased, i.e., OFF.
• Saturation: The amplier is saturated: IC = IC(sat) and VCE = VCE(sat) ∼

= 0 V.
◦ Base-Emitter junction: forward-biased, i.e., ON.

◦ Base-Collector junction: forward-biased, i.e., ON.
4.2.3 Currents
• For any mode (or state) of the transistor and for any conguration, emitter current is always
the sum of the base and collector currents, i.e.,
IE = IC + IB (4.2.3)
• Note that, collector current IC is comprised of majority and minority carrier current components
IC = IC(majority) + IC(minority) = IC(majority) + ICO ∼

= IC(majority) (4.2.4)
where ICO is called the reverse saturation current (or leakage current). The notation most
frequently used for ICO in data and specication sheets is ICBO (the collector-to-base current
with the emitter leg open) as shown in Figure 4.7 below.
Figure 4.7: Common-base cuto current (or reverse saturation current), ICBO .
4.2.4 Alpha (α)

• In the active mode the DC levels of IC and IE due to the majority carriers are related by a
quantity called alpha (αDC ), i.e., IC(majority) = αDC IE . However, as ICBO is very small we dene
αDC as
IC
αDC = . (4.2.5)
IE
In the specication sheets, αDC is expressed as hFB which is the static forward current transfer
ratio.
77
• For AC situations where the point of operation moves on the characteristic curve, an AC alpha
(αac ) is dened by

∆IC ∂IC
αac = = (4.2.6)
∆IE VCB = constant ∂IE Q-point
In the specication sheets, αac is expressed as hf b which is the small signal forward current
transfer ratio.
• For most situations the magnitudes of αac and αDC are quite close,permitting the use of the
magnitude of one for the other, i.e.,
α = αac = αDC ∼
= 1. (4.2.7)
Ideally α = 1, but in reality it lies between 0.9 and 0.998.
4.2.5 Simplication (Active Mode)
Figure 4.8: Simplied output characteristics of a common-base amplier.
• As we see from Figure 4.8 above,

IC ∼
= IE (4.2.8)
i.e., α∼
=1
78
Figure 4.9: Simplied input characteristics of a common-base amplier.
• As we see from Figure 4.9 above,
VBE ∼
= VBE(ON ) = 0.7 V. (4.2.9)
4.2.6 AC Amplication
Figure 4.10: AC equivalent circuit of a common-base amplier.
Example 4.1: For Figure 4.10 above, nd output vo and voltage gain Av .
Solution: Let us rst nd ii = ie as,
vi 200 mV
ii = ie = = = 10 mA.
Ri 20 Ω
As αac ∼
= 1, ic ∼
= ie = 10 mA. Thus, io = Ro
i
Ro +R c
= 100k
i
100k+5k c
∼
= ic = 10 mA.
Consequently, output voltage vo and voltage gain Av are given by
vo = io R = (10 mA)(5 kΩ) = 50 V,

vo 50 V
Av = = = 250.
vi 200 mV
79
4.3 Common-Emitter Conguration
The common-emitter terminology is derived from the fact that the emitter is common to both
the input and output sides of the conguration. In addition, the emitter is usually the terminal
closest to, or at, ground potential.
On the BJT circuit symbol, an arrow is always drawn at the emitter leg of the transistor as
shown in Figures 4.11(a) and 4.11(b) below in the forward direction of the base-emitter pn
junction like the diode symbol. Hence, from the direction of the arrow we can determine type
of the transistor, i.e., npn or pnp.
(a) (b)
Figure 4.11: Notation and symbols used with the common-emitter conguration: (a) npn transistor,
(b) pnp transistor.
4.3.1 Input and Output Characteristics

The input set for the common-emitter amplier relates an input current (IB ) to an input voltage
(VBE ) for various levels of output voltage (VBC ) as shown in Figure 4.12(a) below.
The output set relates an output current (IC ) to an output voltage (VCE ) for various levels of
input current (IB ) as shown in Figure 4.12(b) below. The output set of characteristics has three
basic regions of interest, the active, cuto, and saturation regions. The active region is the
region normally employed for linear ampliers.
80
(a) (b)
Figure 4.12: Characteristics of an npn common-emitter amplier: a) Input characteristics, b) Output

characteristics.
4.3.2 Currents
Collector current IC is given by IC = αIE + ICBO where IE = IC + IB . So,
IC = αIE + ICBO (4.3.10)
= α (IC + IB ) + ICBO (4.3.11)
α 1
= IB + ICBO (4.3.12)
1−α 1−α
= βIB + ICEO (4.3.13)
∼
= βIB (4.3.14)
where ICEO is the common-emitter cuto current (or the collector-to-emitter current with the
base leg open) as shown in Figure 4.13 below and dened by

ICBO
ICEO = = (β + 1) ICBO (4.3.15)
1 − α IB =0 A
Figure 4.13: Common-emitter cuto current, ICEO .
81
4.3.3 Beta (β )
• In the active mode, the DC levels of IC and IB are related by a quantity called beta (βDC ).
However, as ICEO is very small, we dene βDC as
IC
βDC = . (4.3.16)
IB
In the specication sheets, βDC is expressed as hFE which is the static forward current gain.
• For AC situations where the point of operation moves on the characteristic curve, an AC beta
(βac ) is dened by

∆IC ∂IC
βac = = (4.3.17)
∆IB VCE = constant ∂IB Q-point
In the specication sheets, βac is expressed as hfe which is the small signal forward current gain.
• For most situations the magnitudes of βac and βDC are quite close,permitting the use of the
magnitude of one for the other, i.e.,
β = βac = βDC (4.3.18)
4.3.3.1 Determining β from a graph
Figure 4.14: Determining βDC and βac from the output characteristics.
Example 4.2: From Figure 4.14 above, determine βDC and βac .
82
Solution: Reading the values at Q-point, i.e., at VCEQ = 7.5 V, from the gure above, βDC and
βac are given by
ICQ 2.7 mA
βDC = = = 108
IBQ 25 µA

∆IC 3.2 mA − 2.2 mA
βac = = = 100
∆IB Q-point 30 µA − 20 µA
We see that βac ∼

= βDC .
4.3.4 Relationship between β and α

• As we derived before, β is given by
α
β= (4.3.19)
1−α
• Similarly, α is given by
β
α= (4.3.20)
β+1
4.3.5 Simplication (Active Mode)

Simplication (Active Mode)
• In the active mode, collector and emitter currents IC and IE are given by
IC = βIB (4.3.21)
IE = (β + 1) IB . . . as IE = IC + IB (4.3.22)
• Base-emitter junction is also ON. So,
VBE ∼
= VBE(ON ) = 0.7 V. (4.3.23)
4.4 Common-Collector Conguration

The common-collector terminology is derived from the fact that the collector is common to
both the input and output sides of the conguration. In addition, the collector is usually the
terminal closest to, or at, ground potential.
Input and output characteristics are similar to those of the common-emitter amplier, except
the output current is the emitter current IE instead of the collector current IC .
83
(a) (b)
Figure 4.15: Notation and symbols used with the common-collector conguration: (a) npn transistor,
(b) pnp transistor.
4.5 Operating Limits
Figure 4.16: Dening the region of operation for a transistor.
The gure above shows the limitations for the linear region of a common-emitter conguration:
84
1. Maximum and minimum CE voltages: BVCEO and VCE(sat) . Maximum collector-to-emitter
voltage is often abbreviated as BVCEO V(BR)CEO in the specication sheets.
or
2. Maximum and minimum collector current: IC(max) and ICEO .

3. Maximum power curve: PC(max) .
• Design operating point (Q-point) to be in the middle of the linear region (white region).
Note that maximum power curves in dierent congurations are given below
a) Common-Base: VCB IC = PC(max) .

b) Common-Emitter: VCE IC = PC(max) .
c) Common-Collector: VCE IE = PC(max) .
• An example BJT packaging is shown in Figure 4.17 below.
Figure 4.17: An example BJT packaging.
4.6 Simplied BJT Model

We can summarize the simplied npn BJT model with its state and circuit behaviour with the table
below and in Figure 4.18.
Simplied npn BJT Model

IB = 0, VBE < VBE(ON ) ,
CUTOFF
IC = 0, IE = 0 VBC < VBC(ON )
VBE = VBE(ON ) , IB ≥ 0,
ACTIVE
IC = βIB VCE > VCE(sat)
VBE = VBE(ON ) , IB ≥ 0,
SATURATION
VCE = VCE(sat) IC < βIB
85
(a) Cuto (b) Active
(c) Saturation
Figure 4.18: States of the simplied npn BJT model: (a) Cuto, (b) Active, (c) Saturation
• For a pnp BJT transistor, the polarities and directions are simply reversed.
For example, the device will be ON (e.g., in ACTIVE mode) when VEB ≥ VBE(ON ) .
86
Chapter 5
DC Biasing of BJTs
5.1 DC Biasing
Biasing refers to the DC voltages applied to the transistor to put it into active mode, so that
it can amplify the AC signal.
The DC input establishes an operating point or quiescent point called the Q-point.
Proper DC biasing should try to set the Q-point towards the middle of active region, e.g., Point
B in Figure 5.1 below.
Figure 5.1: Various operating points within the limits of operation of a BJT transistor.
87
5.2 Three States of Operation
Proper DC biasing sets the BJT transistor into the active state, so that it can amplify the AC
signal. Let us remember the states of the transistor:
• Active: Operating state of the amplier: IC = βIB .

◦ Base-Emitter (BE ) junction: forward-biased (ON).
◦ Base-Collector (BC ) junction: reverse-biased (OFF).
• Cut-O: The amplier is basically o. There is no current, i.e., IC = IB = IE = 0 A.
◦ Base-Emitter (BE ) junction: reverse-biased (OFF).
◦ Base-Collector (BC ) junction: reverse-biased (OFF).
• Saturation: The amplier is saturated. Voltages are xed, e.g., VCE = VCE(sat) ∼
= 0 V. Output
is distorted, i.e., not the same shape as the input waveform.
◦ Base-Emitter (BE ) junction: forward-biased (ON).

◦ Base-Collector (BC ) junction: forward-biased (ON).
5.3 BJT DC Analysis

1. Draw the DC equivalent circuit (signal frequency is zero, i.e., f = 0)
a) Capacitors are open circuit, i.e., XC → ∞.

b) Kill the AC power sources (short-circuit AC voltage sources and open-circuit AC current
sources).
c) Inductors are short circuit or replaced by their DC resistance (winding resistance) if given,
i.e., XL → 0.
2. Write KVL for the loop which contains BE junction
a) Take VBE = VBE(ON ) to ensure the transistor is ON (or not in the cut-o state). Note: For
a pnp transistor, VEB = VBE(ON ) .
b) Determine the base current IBQ (or emitter current IEQ ).
3. Write KVL for the loop which contains CE terminals
a) Assume the transistor is in the active state and take ICQ = βIBQ (or ICQ = αIEQ ).
b) Calculate VCEQ .
c) If VCEQ ≤ VCE(sat) then the transistor is in the saturation (SAT) state (i.e., ICQ 6= βIBQ ),
so take VCEQ = VCE(sat) and recalculate ICQ .
NOTE: Normally, a BJT should not be in the saturation state if it is used as an amplier.
88
5.4 DC Biasing Circuits
Most common four common-emitter biasing circuits are given below
1. Fixed-Bias Circuit
2. Emitter-Stabilized Bias Circuit
3. Voltage Divider Bias Circuit
4. Collector Feedback Bias Circuit
5.4.1 Fixed-Bias Circuit

Fixed-bias circuit is given in Figure 5.2 below
Figure 5.2: Fixed-bias BJT circuit.
Let us start DC analysis by drawing the DC equivalent circuit as shown in Figure 5.3 below
Figure 5.3: DC equivalent circuit of the xed-bias circuit in Figure 5.2.
89
5.4.1.1 Base-Emitter Loop
Let us continue with the BE loop shown in Figure 5.4 below
Figure 5.4: Base-emitter loop of the xed-bias circuit in Figure 5.2.
Writing KVL on the BE loop

VCC − IB RB − VBE = 0 (5.4.1)
and given VBE = VBE(ON ) , we obtain IBQ as
VCC − VBE(ON )
IBQ = (5.4.2)
RB
5.4.1.2 Collector-Emitter Loop

Let us continue with the CE loop shown in Figure 5.5 below
Figure 5.5: Collector-emitter loop of the xed-bias circuit in Figure 5.2.
Writing KVL on the CE loop (i.e., DC load-line equation)
VCC − IC RC − VCE = 0 (5.4.3)
90
and given (assuming BJT is in active state)
ICQ = βIBQ (5.4.4)
we obtain VCEQ as
VCEQ = VCC − ICQ RC (5.4.5)
Thus, we obtained the Q-point (ICQ , VCEQ ), i.e., the operating point.
5.4.1.3 Saturation
The term saturation is applied to any system where levels have reached their maximum values.
A saturated sponge is one that cannot hold another drop of water. For a transistor operating
in the saturation region, the current is a maximum value for the particular design.
Note that it is in a region where the characteristic curves join and the collector-to-emitter
voltage is at or below VCE(sat) . If we approximate the curves of Figure 5.6(a) by those appearing
in Figure 5.6(b), then the saturation voltage VCE(sat) is assumed to be 0 V, i.e,
VCE(sat) ∼
= 0V (5.4.6)
(a) (b)
Figure 5.6: Saturation regions: (a) actual, (b) approximate.
For the xed-bias conguration shown in Figure 5.7 below, the resulting saturation current (i.e.,
maximum current) IC(sat) is given by
VCC − VCE(sat) ∼ VCC

IC(sat) = IC(max) = = (5.4.7)
RC RC
91
Figure 5.7: Determining IC(sat) for the xed-bias conguration.Example 5.0.
Example 5.1: For the gure below, calculate all DC currents and voltages.
Figure 5.8: Fixed-bias circuit for Example 5.1.
Solution: Let us nd IBQ , ICQ and VCEQ as follows
VCC − VBE(ON ) 12 − 0.7

IBQ = = = 47.08 µA,
RB 240k
ICQ = βIBQ = (50)(47.08µ) = 2.35 mA,
VCEQ = VCC − ICQ RC = 12 − (2.35m)(2.2k) = 6.83 V.
As VCEQ > VCE(sat) = 0 V, transistor is in the active state. Let us also prove it by showing
VBCQ < VBC(ON ) = 0.7 V as follows
VBCQ = VBQ − VCQ = VBEQ − VCEQ = 0.7 − 6.83 = −6.13 V < 0.7 V.
5.4.1.4 DC Load Line

DC load line equation comes from KVL equation in the CE loop (i.e., output loop). For the
xed-bias circuit of Figure 5.2 DC load line equation is given by
VCE = VCC − IC RC (5.4.8)
92
Let us draw the load line over output characteristics curve as shown in Figure 5.9 below. The
intersection of the load-line with the output characteristics curve (determined by the base
current IBQ ) is the operating point, i.e., Q-point.
Figure 5.9: Load line of the xed-bias circuit in Figure 5.2.
• The Q-point is the operating point where the value of RB sets the value of IBQ that controls
the values of VCEQ and ICQ .
Fixed-bias load line equation: VCE = VCC − IC RC
The load line end points are the SATURATION and CUTOFF points, i.e.,
• IC(sat) end point (on the current axis):
IC = VCC /RC
VCE = 0 V
• VCE(cutoff ) end point (on the voltage axis):
VCE = VCC
IC = 0 mA
93
The Eect of IB on the Q-Point
Movement of the Q-point with increasing level of IB (or decreasing level of RB ) is shown in
Figure 5.10 below.
Figure 5.10: Movement of the Q-point with increasing level of IB .
The Eect of RC on the Q-Point

Eect of an increasing level of RC on the load line (slope decreases with increasing RC ) and the
Q-point is shown in Figure 5.11 below.
Figure 5.11: Eect of an increasing level of RC on the load line and the Q-point.
94
The Eect of VCC on the Q-Point
Eect of an decreasing level of VCC on the load line (end points gets smaller with decreasing
VCC ) and the Q-point is shown in Figure 5.12 below.
Figure 5.12: Eect of lower values of VCC on the load line and the Q-point.
Example 5.2: For the xed-bias load line below, calculate VCC , RC and RB .
Figure 5.13: Fixed-bias load line for Example 5.2.
Solution: From the gure, IBQ = 25 µA. So, let us nd VCC , RC and RB as follows
VCC = VCE(cutoff ) = 20 V,
VCC 20
RC = = = 2 kΩ,
IC(sat) 10m
VCC − VBE(ON ) 20 − 0.7
RB = = = 772 kΩ.
IBQ 25µ
95
5.4.2 Emitter-Stabilized Bias Circuit
Adding a resistor to the emitter circuit stabilizes the bias circuit, as shown in Figure 5.14 below.
Figure 5.14: Emitter-stabilized bias circuit.
Figure 5.15: DC equivalent circuit of the emitter-stabilized bias circuit in Figure 5.14.

96
(a) (b)
Figure 5.16: Base-emitter loop of the emitter-stabilized bias circuit in Figure 5.14: (a) normal circuit,
(b) equivalent circuit for common base current.
Writing KVL on the BE loop
VCC − IB RB − VBE − IE RE = 0 (5.4.9)
VCC − IB RB − VBE(ON ) − (β + 1)IB RE = 0, . . . as VBE = VBE(ON ) and

IE = (β + 1)IB in active mode (5.4.10)
we obtain IBQ as
VCC − VBE(ON )
IBQ = (5.4.11)
RB + (β + 1)RE
Similarly, we can obtain IEQ directly from Figure 5.17, or dividing the denominator of the IBQ
in (5.4.12) by (β + 1)
Figure 5.17: Equivalent circuit for common emitter current for the base-emitter loop of the emitter-
stabilized bias circuit in Figure 5.14.
as follows
VCC − VBE(ON )
IEQ = (5.4.12)
RB
+ RE
β+1
97
• It is generally better to calculate IEQ directly to reduce the number of calculations, especially
when there is an emitter resistor RE is connected.

Figure 5.18: Collector-emitter loop of the emitter-stabilized bias circuit in Figure 5.14.
Let us write down the KVL equation on the CE loop
VCC − IC RC − VCE − IE RE = 0 (5.4.13)
VCC − IC RC − VCE − IC RE = 0 IC = αIE ∼

. . . as = IE in active mode (5.4.14)
VCC − IC (RC + RE ) − VCE = 0 . . . DC load line equation (5.4.15)
As ICQ = βIBQ ∼
= IEQ in active mode, we obtain VCEQ as
VCEQ = VCC − ICQ (RC + RE ) (5.4.16)
5.4.2.3 DC Load Line

DC load line equation comes from KVL equation in the CE loop (i.e., output loop). For the
emitter-stabilized bias circuit of Figure 5.14 DC load line equation is given by
VCE = VCC − IC (RC + RE ) (5.4.17)
Let us draw the load line over output characteristics curve as shown in Figure 5.19 below.
98
Figure 5.19: Load line of the emitter-stabilized bias circuit in Figure 5.14.
Here, VCE(cutoff ) = VCC and IC(sat) is given by
VCC
IC(sat) = (5.4.18)
RC + RE
• The Q-point is the operating point where the value of RB and RE sets the value of IBQ that
controls the values of VCEQ and ICQ .
5.4.2.4 Improved Biased Stability

Stability refers to a condition in which the currents and voltages remain fairly constant over a
wide range of temperatures and transistor beta (β ) values.
• Adding RE resistor to the emitter improves the stability of a transistor.
Figure 5.20: Emitter-stabilized bias circuit for Example 5.3.
99
Solution: Let us nd IBQ , ICQ and VCEQ as follows
VCC − VBE(ON ) 20 − 0.7

IBQ = = = 40.13 µA,
RB + (β + 1)RE 430k + (50 + 1)(1k)
ICQ = βIBQ = (50)(40.13µ) = 2.01 mA,
VCEQ ∼
= VCC − ICQ (RC + RE ) = 20 − (2.01m)(2k + 1k) = 13.97 V.
As VCEQ > 0 V (VCE(sat) ), transistor is in the active state. Let us also prove it by showing
VBCQ < VBC(ON ) = 0.7 V as follows
VBCQ = VBQ − VCQ = VBEQ − VCEQ = 0.7 − 13.97 = −13.27 V < 0.7 V.
5.4.3 Voltage Divider Bias Circuit

Voltage divider bias circuit is given in Figure 5.21 below
Figure 5.21: Voltage divider bias BJT circuit.
100
Figure 5.22: DC equivalent circuit of the voltage divider bias circuit in Figure 5.21.
5.4.3.1 Base-Emitter Loop (Exact Analysis)

Let us transform the BE loop circuit shown in Figure 5.23(a) below to the Thévenin simplied
circuit in Figure 5.23(b) below
(a) (b)
Figure 5.23: Base-emitter loop of the voltage divider bias circuit in Figure 5.21: (a) normal circuit,
(b) Thévenin equivalent circuit.
where the Thévenin voltage VBB and Thévenin resistance RBB are calculated as follows
R2
VBB = VCC . . . from Figure 5.24(a) below (5.4.19)
R1 + R2
RBB = R1 ||R2 . . . from Figure 5.24(b) below (5.4.20)
101
(a) (b)
Figure 5.24: Thévenin analysis circuits for the circuit in Figure 5.23(a): (a) Open-circuit voltage
calculation, (b) Test-voltage method for Thévenin resistance calculation.
Writing KVL on the Thévenin equivalent BE loop shown in Figure 5.23(b)
VBB − IB RBB − VBE − IE RE = 0 (5.4.21)
VBB − IB RBB − VBE(ON ) − (β + 1)IB RE = 0, . . . as VBE = VBE(ON ) and

IE = (β + 1)IB in active mode (5.4.22)
we obtain IBQ as
VBB − VBE(ON )
IBQ = (5.4.23)
RBB + (β + 1)RE
Similarly, we obtain IEQ as
VBB − VBE(ON )
IEQ = (5.4.24)
RBB
+ RE
β+1
5.4.3.2 Base-Emitter Loop (Approximate Analysis)

RBB
If we look at the IEQ equation in (5.4.24), we see that if RE β+1
, equation simplies to
VBB − VBE(ON )
IEQ = (5.4.25)
RE
R2
where VBB = V .
R1 +R2 CC
• Approximate approach can be used when (β + 1)RE RBB . Approximate analysis condition
can be rewritten as
(β + 1)RE ≥ 10(R1 ||R2 ). (5.4.26)
Assuming R1 > R2 , we know that (R1 ||R2 ) ≤ R2 . So, the condition above can be further
simplied to
βRE ≥ 10R2 . (5.4.27)
• Satisfying this condition means that we can safely ignore the base current IB in the DC equivalent
circuit shown in Figure 5.22 and apply the voltage divider rule between R2 and R1 .
• Finally, if β times the value of RE is at least 10 times the value of R2 , the approximate approach
can be applied with a high degree of accuracy.
102
5.4.3.3 Collector-Emitter Loop and DC Load line
• Analysis on the CE loop (i.e., output loop), is the same as the CE loop analysis of the emitter-
stabilized circuit given in Section 5.4.2.2. So, VCEQ is given by
VCEQ = VCC − ICQ (RC + RE )
where ICQ ∼
= IEQ .
• Similarly, DC load line analysis is also the same as the DC load line of the emitter-stabilized
circuit given in Section 5.4.2.3. So, DC load line equation is given by
VCE = VCC − IC (RC + RE )
Example 5.4: For the gure below, calculate all DC currents and voltages using both exact
and approximate analysis.
Figure 5.25: Voltage-divider bias circuit for Example 5.4.
Solution: Let us rst nd the Thévenin voltage VBB and resistance RBB as follows
R2 3.9k
VBB = VCC = 22 = 2 V,
R1 + R2 39k + 3.9k
RBB = R1 ||R2 = 3.9k||39k = 3.55 kΩ.
Now, let us calculate IBQ , ICQ and VCEQ as follows
VBB − VBE(ON ) 2 − 0.7

IEQ = = = 0.85 mA,
RBB /(β + 1) + RE 3.55k/(140 + 1) + 1.5k
ICQ ∼
= IEQ = 0.85 mA,
VCEQ ∼
= VCC − ICQ (RC + RE ) = 22 − (0.85m)(10k + 1.5k) = 12.23 V.
As βRE ≥ 10R2 210 kΩ ≥ 39 kΩ), we can use the approximate analysis and
(i.e., ignore RBB
and voltage drop across RBB as follows
VBB − VBE(ON ) 2 − 0.7

IEQ = = = 0.87 mA,
RE 1.5k
ICQ ∼= IEQ = 0.87 mA,
VCEQ ∼= VCC − ICQ (RC + RE ) = 22 − (0.87m)(10k + 1.5k) = 12 V.
103
We see that approximate analysis provides close values to the exact analysis. The dierences in
ICQ and VCEQ are only 0.02 mA and 0.23 V, respectively.
5.4.4 Collector Feedback Bias Circuit

Another way to improve the stability of a bias circuit is to add a feedback path from collector
to base as shown in Figure 5.26 below
Figure 5.26: Collector feedback bias circuit.
Figure 5.27: DC equivalent circuit of the collector feedback circuit in Figure 5.26.

104
Figure 5.28: Base-emitter loop of the collector feedback circuit in Figure 5.26.
We can write KVL equation on the BE loop noting that IC0 = IC + IB = IE
VCC − IC0 RC − IB RF − VBE − IE RE = 0 (5.4.28)
IE
VCC − IE RC − RF − VBE(ON ) − IE RE = 0, . . . as VBE = VBE(ON ) and
β+1
IE
IB = in active mode (5.4.29)
β+1
and we obtain IEQ as
VCC − VBE(ON )
IEQ = (5.4.30)
RF
+ (RC + RE )
β+1

Figure 5.29: Collector-emitter loop of the collector feedback circuit in Figure 5.26.
105
Let us write down the KVL equation on the CE loop noting that IC0 = IC + IB
VCC − IC0 RC − VCE − IE RE = 0 (5.4.31)
VCC − IC RC − VCE − IC RE = 0 . . . as IC ∼
= IE and IC ∼
= IC0 in active mode (5.4.32)
VCC − IC (RC + RE ) − VCE = 0 . . . DC load line equation (5.4.33)
As ICQ ∼
= IEQ in active mode, we obtain VCEQ as
VCEQ = VCC − ICQ (RC + RE ) (5.4.34)
5.4.4.3 DC Load line

• Note that IC0 = IE , and
IC ∼
= IE
in active mode (and β is high).
• So, DC load line analysis is the same as the DC load line of the emitter-stabilized circuit given
in Section 5.4.2.3. So, DC load line equation is given by
VCE = VCC − IC (RC + RE )
5.4.5 Various Dierent Bias Circuits

Figure 5.30: Common-collector bias circuit for Example 5.5.
Solution: Let us nd IEQ , ICQ and VCEQ as follows
0 − VBE(ON ) − VEE 20 − 0.7

IEQ = = = 4.16 mA,
RB /(β + 1) + RE 240k/(90 + 1) + 2k
ICQ ∼
= IEQ = 4.16 mA,
VCEQ = 0 − IEQ RE − VEE = 20 − (4.16m)(2k) = 11.68 V.
As VCEQ > VCE(sat) = 0 V, transistor is in the active state.
106
5.4.6 pnp Transistors
The analysis for pnp bias transistor circuits is the same as that for npn transistor circuits.
The only dierences are that
1. Currents are owing in the opposite direction.
2. Voltages have opposite polarity, e.g., VEB = VBE(ON ) = 0.7 V in the active mode.
Figure 5.31: pnp transistor in a voltage-divider bias conguration Example 5.6.
Solution: As βRE ≥ 10R2 , 132 kΩ ≥ 100 kΩ, we can ignore RBB

i.e., and use the approximate
approach. Thus, we can nd VBB , IEQ , ICQ and VECQ as follows
R2 10k
VB ∼
= VCC = (−18) = −3.16 V
R1 + R2 47k + 10k
∼ 0 − VEB − VB 0 − 0.7 − (−3.16) 2.46
IEQ = = = = 2.24 mA,
RE 1.1k 1.1k
ICQ ∼
= IEQ = 2.24 mA,
VECQ = 0 − ICQ (RC + RE ) − VCC = −(2.24m)(2.4k + 1.1k) − (−18) = 10.16 V.
As VECQ > VCE(sat) = 0 V, transistor is in the active state.
5.5 Bias Stabilization

Variation of three BJT (Si) parameters (ICO , β and VBE(ON ) ) with temperature are summarized
below
T ↑ ICO ↑ β↑ VBE(ON ) ↓ (5.5.35)
◦ ICO (reverse saturation current)
107
− doubles in value for every 10 ◦ C
◦ β (transistor current gain)
− increases with increasing temperature
◦ VBE(ON ) (forward bias potential of the base-emitter junction)
− decreases about 2.5 mV per 1 ◦C increase in temperature
Variation of the transistor parameters with temperature causes a shift in the operating point
(i.e., Q-point).
Figures below (at 25 ◦ C on the left and at 100 ◦ C on the right) show the shift of the Q-point (or
DC bias point) due to temperature change for a xed-bias circuit.
(a) (b)
Figure 5.32: Shift in operating point (Q-point) due to change in temperature: (a) 25 ◦ C, (b) 100 ◦ C.
5.5.1 Stability Factors

Stability of the collector current IC depends on the stability of several parameters like ICO , β ,
VBE(ON ) , VCC , RB , RC , etc.
A stability factor S is dened for each of the parameters aecting bias stability as follows:

∂IC ∆IC
SICO = = (5.5.36)
∂ICO ∆ICO β,VBE(ON ) ,... constant

∂IC ∆IC
Sβ = = (5.5.37)
∂β ∆β ICO ,VBE(ON ) ,... constant

∂IC ∆IC
SVBE(ON ) = = (5.5.38)
∂VBE(ON ) ∆VBE(ON ) ICO ,β,... constant
108
We know that dierential dIC is given by the linear map of parameter dierentials as follows
∂IC ∂IC ∂IC

dIC = dICO + dβ + dVBE(ON ) + · · · (5.5.39)
∂ICO ∂β ∂VBE(ON )
• Thus, we obtain the collector-current change ∆IC using the stability factors as follows
∆IC ∼
= SICO ∆ICO + Sβ ∆β + SVBE(ON ) ∆VBE(ON ) (5.5.40)
5.5.1.1 Derivation of Stability Factors (Voltage-Divider Bias Circuit)
Figure 5.33: Equivalent circuit for the voltage-divider conguration.
Let us write down the active mode collector current and BE -loop KVL equations for the circuit
shown in Figure 5.33 above,
IC = βIB + (β + 1) ICO (5.5.41)
VBB = IB RBB + VBE(ON ) + (IB + IC )RE (5.5.42)
Combining the two equations (5.5.41) and (5.5.42) above, we obtain the expression for IC as
β (β + 1) (RBB + RE )
IC = VBB − VBE(ON ) + ICO (5.5.43)
RBB + (β + 1) RE RBB + (β + 1) RE
∂IC
1. From equation (5.5.43), let us derive SICO = ∂ICO
as
RBB + RE
SICO = (β + 1) (5.5.44)
RBB + (β + 1) RE
∂IC
2. From equation (5.5.43), let us derive SVBE(ON ) = ∂VBE(ON )
as
−β
SVBE(ON ) = (5.5.45)
RBB + (β + 1) RE
109
3. In order to derive Sβ = ∂IC
∂β
, let us rst simplify (5.5.43) by letting ICO ∼
=0
β
IC ∼

= VBB − VBE(ON ) (5.5.46)
RBB + (β + 1) RE
Using the simplied IC equation (5.5.46) we can express IC1 and IC2 as follows
β1
IC1 ∼

= VBB − VBE(ON ) (5.5.47)
RBB + (β1 + 1) RE
∼ β2
IC2 = VBB − VBE(ON ) (5.5.48)
RBB + (β2 + 1) RE
IC2 −IC1
Thus, using (5.5.47) and (5.5.48), let us obrain the ratio as
IC1
IC2 − IC1 β2 − β1 RBB + RE

= (5.5.49)
IC1 β1 RBB + (β2 + 1) RE
∆IC
From equation (5.5.50), we can obtain the ratio
∆β
by using ∆IC = IC2 − IC1 and ∆β = β2 − β1
as
∆IC IC RBB + RE
= 1 (5.5.50)
∆β β1 RBB + (β2 + 1) RE
Thus, as Sβ = ∂IC ∼
= ∆IC
∂β ∆β
IC1 RBB + RE
Sβ = (5.5.51)
β1 RBB + (β2 + 1) RE
5.5.1.2 Stability Factors for Other Bias Circuits

A. For the xed-bias circuit, i.e., by substituting RE =0 and RBB = RB into (5.5.44), (5.5.45)
and (5.5.51), the stability factors are given by
SICO = β + 1 (5.5.52)
−β
SVBE(ON ) = (5.5.53)
RB
IC
Sβ = 1 (5.5.54)
β1
B. For the emitter-stabilized bias circuit, i.e., RBB = RB and RB RE , the stability factors
are given by
RB + RE ∼ β+1
SICO = (β + 1) = (5.5.55)
RB + (β + 1) RE (β + 1) RE
1+
RB
−β
SVBE(ON ) = (5.5.56)
RB + (β + 1) RE
IC RB + RE ∼ IC 1
Sβ = 1 = 1 (5.5.57)
β1 RB + (β2 + 1) RE β1 (β2 + 1) RE
1+
RB
110
C. For the voltage-divider bias circuit with (β + 1)RE ≥ 10RBB , the stability factors are given
by
RBB + RE ∼ RBB
SICO = (β + 1) =1+ (5.5.58)
RBB + (β + 1) RE RE
−β ∼ −1
SVBE(ON ) = = (5.5.59)
RBB + (β + 1) RE RE

IC1 RBB + RE ∼ IC 1 R BB
Sβ = = 1+ (5.5.60)
β1 RBB + (β2 + 1) RE β1 β2 RE
D. For the collector feedback bias circuit, i.e., RBB = RF , replacing RE with RCE = RC + RE
and RF RCE , the stability factors are given by
RF + RCE ∼ β+1
SICO = (β + 1) = (5.5.61)
RF + (β + 1) RCE (β + 1) RCE
1+
RF
−β
SVBE(ON ) = (5.5.62)
RF + (β + 1) RCE
IC1 RF + RCE ∼ IC 1
Sβ = = 1 (5.5.63)
β1 RF + (β2 + 1) RCE β1 (β2 + 1) RCE
1+
RF
Example 5.7: Find and compare the collector current change ∆IC when the temperature
rises from 25 ◦ C to 100 ◦ C for the transistor dened by the table below for the following bias
arrangements.
a. Fixed-bias with RB = 240 kΩ and IC1 = 2 mA,

b. Voltage-divider bias with RE = 4.7 kΩ, RBB /RE = 2 and IC1 = 2 mA.
Temperature ICO β VBE(ON )

−65 ◦ C 0.02 nA 20 0.85 V
25 ◦ C 0.1 nA 50 0.65 V
100 ◦ C 20 nA 80 0.48 V
175 ◦ C 3.3 µA 120 0.30 V
Solution: From the table above, let us rst calculate ∆ICO , ∆β and ∆VBE(ON )
∆ICO = ICO2 − ICO1 = 20n − 0.1n = 19.9 nA
∆β = β2 − β1 = 80 − 50 = 30
∆VBE(ON ) = VBE(ON )2 − VBE(ON )1 = 0.48 − 0.65 = −0.17 V
We are goiung to calculate ∆IC using
∆IC ∼
= SICO ∆ICO + Sβ ∆β + SVBE(ON ) ∆VBE(ON )
111
a. Let us calculate the stability factors for the xed-bias circuit using (5.5.52), (5.5.54) and (5.5.53)
SICO = β + 1 = 51
IC 2m
Sβ = 1 = = 0.04 mA
β1 50
−β −50
SVBE(ON ) = = = −0.21 mΩ−1
RB 240k
Thus, ∆IC is given by
∆IC ∼
= (51)(19.9n) + (0.04m)(30) + (−0.21m)(−0.17)
= 1.02µ + 1.2m + 0.036m
= 1.236 mA
That means, for the xed-bias circuit IC increases to 3.236 mA at 100 ◦ C from 2 mA.
b. Let us calculate the stability factors for the voltage-divider bias circuit using (5.5.58), (5.5.60)
and (5.5.59)
RBB
SICO ∼ =1+ =1+2=3
RE

∼ IC1 RBB 2m
Sβ = 1+ = (1 + 2) = 1.5 µA
β1 β2 RE (50)(80)
−1 −1
SVBE(ON ) = = = −0.21 mΩ−1
RE 4.7k
Thus, ∆IC is given by
∆IC ∼
= (3)(19.9n) + (1.5µ)(30) + (−0.21m)(−0.17)
= 0.060µ + 0.045m + 0.036m
= 0.081 mA
That means, for the voltage-divider bias circuit IC increases to 2.08 mA at 100 ◦ C from 2 mA.
Most of the improvement comes from the reduction in Sβ .
• These two results show that voltage-divider bias circuit is much more stable than the xed-bias
circuit. In other words, adding RE resistor to the emitter leg of the transistor stabilizes the bias
circuit.
5.5.2 Stability of Transistor Circuits with Active Components

• VBE compensation
− by using a reverse-biased diode at the emitter
112
Figure 5.34: Active VBE compensation using a reverse-biased diode at the emitter.
• ICO compensation
− by replacing R2 with a reverse-biased diode
Figure 5.35: Active ICO compensation replacing R2 with a reverse-biased diode.
• IC compensation (without RE )
− by using a current mirror
Figure 5.36: Active IC compensation using a current mirror.
113
5.6 Practical Applications
5.6.1 Relay Driver
Figure 5.37: Relay driver in the absence of protective device.
When the transistor turns OFF, a high voltage (given by vL = L (diL /dt)) is induced across
the coil as shown in Figure 5.38 above. If its magnitude exceeds the maximum ratings of the
transistor, then the semiconductor device will be permanently damaged.
This destructive action can be subdued by placing a diode across the coil as shown in Figure 5.38
below. During the ON state of the transistor, the diode is reverse-biased (i.e., open circuit) and
doesn't aect a thing. However, when the transistor turns o, the voltage across the coil will
reverse and will forward-bias the diode, placing the diode in its ON state (hence protecting the
transistor).
Figure 5.38: Relay driver protected with a diode across the relay coil.
5.6.2 Transistor Switch

A transistor can be used as a switch to control the ON and OFF states of the light-bulb in the
collector branch of the circuit as shown in Figure 5.39 below.
114
Figure 5.39: Using the BJT as a switch to control the onâo states of a bulb with a limiting resistor.
5.6.3 Transistor Switching Networks
Figure 5.40: A BJT inverter circuit and its operation.
The application of transistors is not limited solely to the amplication of signals. Through
proper design, transistors can also be used as switches for computer and control applications.
The circuit shown in Figure 5.40 above can be employed an inverter in computer logic circuitry.
Inversion process requires that the Q-point switch from cuto (Vo = VCE(cutoff ) = 5 V) to sa-
turation (Vo = VCE(sat) = 0 V) along the load line depicted in Figure 5.41 below.
115
Figure 5.41: Load-line of the inverter circuit in Figure 5.40.
The total time required for the transistor to switch from the OFF to the ON state is designated
as ton , and he total time required for a transistor to switch from the ON to the OFF state is
referred to as toff as shown in Figure 5.42 below. ton and toff are dened by
ton = tr + td (5.6.64)
toff = ts + tf (5.6.65)
where tr is the rise time from 10% to 90% of the output, td is the delay time between the
changing state of the input and the beginning of a response at the output, ts is the storage time
and and tf the fall time from 90% to 10% of the output.
Figure 5.42: Dening the time intervals of a pulse waveform.
116
5.6.4 Logic Gates
Figure 5.43: BJT logic OR gate.
Figure 5.43 above shows a BJT logic OR gate, and similarly Figure 5.44 below shows a BJT
logic AND gate.
Figure 5.44: BJT logic AND gate.
5.6.5 Current Mirror

The current mirror shown in Figure 5.45 below is a DC circuit in which the current through
a load is controlled by a current at another point in the circuit. That is, the current through
the load is indepedent of the load.
117
Figure 5.45: BJT logic OR gate.
Homework 5.1: For Figure 5.45 above, show that the load current is equal to the load control
current and given by
VCC − VBE(ON )
IL ∼
= Icontrol = (5.6.66)
R
where the transistors are identical (Q1 ≡ Q2 ), i.e., VBE1 (ON ) = VBE2 (ON ) = VBE(ON ) and β1 =
β2 = β , and current gain β is high, e.g., β ≥ 100.
5.6.6 Voltage Level Indicator

The voltage level indicator circuit uses a green LED to indicate when the source voltage is close
to its monitoring level of 9 V. The potentiometer is set to establish 5.4 V at the point indicated
in Figure 5.46 below. The result is sucient voltage to turn on both the 4.7 V Zener and the
transistor and establish a collector current through the LED sucient in magnitude to turn
on the green LED. The LED will immediately turn o, revealing that the supply voltage has
dropped below 9V or that the power source has been disconnected (i.e., when the voltage set
up by the voltage divider circuit drops below 5.4 V).
Figure 5.46: Voltage level indicator.
118
Chapter 6
AC-DC Load Lines of BJT Circuits
6.1 BJT AC Analysis

1. Draw the AC equivalent circuit (signal frequency is innity, i.e., f = ∞)
a) Capacitors are short circuit, i.e., XC → 0.

b) Kill the DC power sources (short-circuit DC voltage sources and open-circuit DC current
sources).
2. Write KVL for the loop which contains CE terminals
a) Develop AC load-line equation.
3. Draw AC-DC load lines
a) Find available swings for a given input or nd maximum undistorted swings.
Figure 6.1: A voltage-divider common-emitter BJT circuit.
119
Consider the common-emitter BJT circuit shown in Figure 6.1 above where vi = Vm sin(ωt). Its
DC and AC equivalent circuits are shown in Figure 6.2 below.
(b)
(a)
Figure 6.2: DC and AC equivalent circuits of the common-emitter circuit in Figure 6.1: (a) DC
equivalent circuit (b) AC equivalent circuit.
6.1.1 DC Load Line
Figure 6.3: DC equivalent circuit of Figure 6.1.
DC equivalent circuit shown in Figure 6.3 above, let us rst dene the equivalent output-loop
(CE -loop) DC resistance RDC and VCE as follows
RDC = RC + RE (6.1.1)
VCE = VCC − IC RDC (6.1.2)
Thus, the rearranged DC load line equation (DC output equation) is given by
−1 VCC
IC = VCE + (6.1.3)
RDC RDC
120
Note that, AC swings are around the Q-points. Here, input swing vbe = vi in Figure 6.4(a) below
is around the input Q-point (IBQ , VBEQ ), and output swing vo = vce in Figure 6.4(b) below is
around the output Q-point (ICQ , VCEQ ).
(b)
(a)
Figure 6.4: Input and output swings around the Q-points: (a) input swing (b) output swing.
6.1.2 Distortion
If the Q-point is incorrect as shown in Figure 6.5(a) below, or if the input is too high as shown
in Figure 6.5(b) below, then the output swings (for a sinusoidal input) as shown in the gures
below will be distorted, i.e., not the same shape as the input waveform.
NOTE: Load-lines shown in the gures below are the AC load-lines which we will derive in the
next section.
121
(a) (b)
Figure 6.5: Distorted output swings: (a) incorrect Q-point (b) incorrect input (i.e., high input).
6.1.3 AC Load Line
Figure 6.6: AC-equivalent circuit of Figure 6.1.
AC equivalent circuit shown in Figure 6.6 above, let us rst dene the equivalent output-loop
(CE -loop) AC resistance Rac and output vo as follows
Rac = RC ||RL (6.1.4)
vo = vce = −ic Rac (6.1.5)
Let us now dene the AC+DC output signals iC and vCE as follows
iC = ic + ICQ (6.1.6)
vCE = vce + VCEQ (6.1.7)
122
Now let us express the AC output equation vce = −ic Rac in terms of vCE and iC so that we can
draw this equation over the output characteristics curve as the AC load line equation.
vce = −ic Rac (6.1.8)
vCE − VCEQ = −(iC − ICQ )Rac (6.1.9)
vCE = −iC Rac + VCEQ + ICQ Rac (6.1.10)
Thus, the rearranged AC load line equation (AC output equation) is given by
−1 VCEQ
iC = vCE + ICQ + (6.1.11)
Rac Rac
6.1.4 AC-DC Load Lines

Let us draw DC (VCE = vce + VCEQ ) and AC (vCE = −iC Rac + VCEQ + ICQ Rac ) load lines
together as shown in Figure 6.7 below.
Figure 6.7: AC-DC load lines.
Output swings are dened with respect to the Q-point (ICQ , VCEQ ) and the AC load line
end points on the axes.
Homework 6.1: Show that AC and DC load lines are the same if RDC = Rac .
Once the Q-point is known, i.e., the resistor values are given, peak values of the maximum
undistorted voltage and current swings vce(p)(max) and ic(p)(max) are given by
vce(p)(max) = min (VCEQ , ICQ Rac ) (6.1.12)
and
VCEQ
ic(p)(max) = min ICQ , (6.1.13)
Rac
respectively
123
6.1.4.1 Maximum Symmetric Undistorted Swing Design
If we want design our circuit (i.e., select appropriate values for the resistors) in order to obtain
the maximum available undistorted swing, i.e., to obtain max (min (VCEQ , ICQ Rac )), then we
obtain the following condition
VCEQ = ICQ Rac (6.1.14)
Thus, Q-point must be in the middle of the AC load line. In other words, maximum available
negative and positive swings are symmetric.
Combining this AC load line requirement in (6.1.14) with the DC load-line equation given in
(6.1.2), we nd that we have to select the Q-point collector current as
VCC
ICQ = (6.1.15)
RDC + Rac
In order to attain this Q-point, we need to select appropriate values for the resistors in the BE
ICQ
loop to obtain IBQ = β
.
Once we obtained the desired Q-point in the middle of the AC load line, then the maximum
available undistorted output swings will be obtained as shown in Figure 6.8 below.
Figure 6.8: Maximum undistorted swing design with Q-point in the middle of the AC load line.
124
6.1.4.2 Other Amplier Congurations
We developed and plotted AC-DC load lines for the common-emitter conguration. Now, let us look
at other congurations.
• Common-base (CB) conguration
1. Obtain Rac from the CB loop.
2. Obtain RDC from the CE loop.
3. Draw the AC-DC load lines iC vs. vCE as before.
NOTE: You can also draw the AC-DC load lines as iC vs. vCB by shifting the voltage axis
by VBE(ON ) volts to the left as VCBQ = VCEQ − VBE(ON ) . Thus, current axis will be drawn
at VCB(sat) = VCE(sat) − VBE(ON ) = 0 − VBE(ON ) = −VBE(ON ) volts not at 0 V.
• Common-collector (CC) conguration (also known as emitter-follower)
1. Obtain Rac and RDC from the CE loop as before.
2. Draw the AC-DC load lines iE vs. vCE .

NOTE: As iE ∼
= iC , it will be the same as drawing iC vs. vCE .
• For pnp transistors, we express the currents in the reverse direction (i.e., having positive current
values) and reverse the polarity of the terminal voltages (i.e., having positive voltage values),
and then draw the AC-DC load lines, e.g., iC vs. vEC .
125
Example 6.1: Consider the circuit below with IBQ = 50 µA, ICQ = 13 mA and α∼
= 1.
a) If ii = 50 µA sin(ωt), nd iC and vCE .
b) Plot AC and DC load lines together with the output voltage and current swings.
Figure 6.9: BJT amplier circuit for Example 6.1.
Solution: CQ
βac = βDC = β = IBQ
Here = 13m
50µ
I
= 260, RDC = RC + RE = 1k + 0.47k = 1.47 kΩ
and Rac = RC ||RL = 1k||1k = 0.5 kΩ. So, we can nd VCEQ as
VCEQ = VCC − ICQ RDC = 30 − (13m)(1.47k) = 10.89 V sin(ωt).
As ib ∼
= ii , we can nd ic and vce as
ic = βac ib ∼
= βii = (260)(50µ) = 13 mA sin(ωt)
vce = −ic Rac = −(13m)(0.5k) = −6.5 V sin(ωt)).
We nd iC and vCE as
iC = ICQ + ic = 13 mA + 13 mA sin(ωt)
vCE = VCEQ + vce = 10.89 V − 6.5 V sin(ωt)
Thus, the AC-DC load-lines are shown in Figure 6.10 below
126
Figure 6.10: AC-DC load-lines for Example 6.1.
Example 6.2: Consider the circuit below with α∼

= 1.
a) Determine the Q-point in order to obtain maximum undistorted current swing.
b) Draw AC and DC load lines.
Solution: We can design this circuit to have maximum symmetric undistorted output swing and
select R1 and R2 values accordingly. So, from the gure RDC = RC + RE = 1k + 0.5k = 1.5 kΩ
and Rac = RC = 1 kΩ. Thus,
VCC 15
ICQ = = = 6 mA
RDC + Rac 1.5k + 1k
VCEQ = VCC − ICQ RDC = 15 − (6m)(1.5k) = 6 V
127
Maximum available swings ic and vce are given as
ic = 6 mA sin(ωt)
vce = −6 V sin(ωt)
Consequently, the AC-DC load-lines are shown in Figure 6.12 below
128
Example 6.3: (2004-2005 MI) Consider the common-emitter BJT amplier in the gure below.
a) Explain briey the eects of the capacitors C1 , C2 and C3 on DC biasing and AC operation.
b) Design the DC bias (ICQ and VCEQ ) for the maximum undistorted output swing and
then nd the values of R1 and R2 which satises this condition. Take βRE ≥ 10(R1 ||R2 ),
VBE(ON ) = 0.7 V and β = 100.
c) Draw the DC and AC load lines for this circuit and show the maximum voltage and current
swings on the graph. Also, express these current and voltage swings in written form with
their AC and DC components.
Solution: a. Capacitors are open-circuit in DC operation. Thus, C1 and C2 are called the
coupling capacitors for the protection of the Q-point of the amplier from the input and output
circuitries by preventing the circulation/leakage of DC signals and enabling only AC signals
in and out. C3 is called the emitter bypass capacitor ensuring the stability of the Q-point by
enabling the emitter resistor to be in eect in DC operation and increasing the AC gain by
bypassing the emitter resistor in AC operation.
b. We can design this circuit to have maximum symmetric undistorted output swing and select
R1 and R2 values accordingly. So, from the gure RDC = RC + RE = 1k + 0.5k = 1.5 kΩ and
Rac = RC ||RL = 1k||1k = 0.5 kΩ. Thus,
VCC 18
ICQ = = = 9 mA
RDC + Rac 1.5k + 0.5k
VCEQ = VCC − ICQ RDC = 18 − (9m)(1.5k) = 4.5 V
As IEQ ∼
= ICQ = 9 mA, base voltage VBQ is given by
VBQ = VBE(ON ) + IEQ RE = 0.7 + (9m)(0.5k) = 5.2 V.
129
By making the assumption βRE ≥ 10(R1 ||R2 ), we can ignore the base current IBQ and directly
apply the voltage divider rule as
R2 ∼
VCC = VBQ
R1 + R2
R1 + R2 VCC
=
R2 VBQ
R1 VCC 18
= −1= − 1 = 2.46.
R2 VBQ 5.2
Let us take the highest value of RBB = R1 ||R2 in order to reduce the currents through R1 and
R2 as
RBB = R1 ||R2 = βRE /10 = 100 × 0.5k/10 = 5 kΩ
R1 a
If we take a= R2
= 2.46, then RBB = R . So,
a+1 2
R2 is given by
a+1 2.46 + 1
R2 = RBB = 5k = 7.03 kΩ
a 2.46
Thus, R1 is given by
R1 = aR2 = (2.46)(7.03k) = 17.29 kΩ
c. AC+DC output current iC and output voltage vCE are given by
iC = ICQ + ic = 9 mA + 9 mA sin(ωt)
vCE = VCEQ + vce = 4.5 V − 4.5 V sin(ωt)
Consequently, the AC-DC load-lines are shown in Figure 6.14 below
130
Chapter 7
Field Eect Transistors (FETs)
7.1 Similarities and Dierences with BJTs

Field-eect transistors (FETs) are three-terminal devices used for a variety of applications that match,
to a large extent, those of the BJTs.
Similarities:
• Ampliers
• Switching devices
• Impedance matching circuits
Dierences:
• FETs are voltage controlled devices whereas BJTs are current controlled devices
• FETs also have a higher input impedance, but BJTs have higher gains
• FETs are less sensitive to temperature variations and because of their construction they are
more easily integrated on ICs
• FETs are also generally more static sensitive than BJTs
• FETs have a poorer frequency response (i.e., lower gain-bandwidth product) than BJTs
• FETs have a higher output impedance than BJTs
BJT is a current-controlled device as depicted in Figure 7.1(a) below, whereas FET is a voltage-
controlled device as shown in Figure 7.1(b) below.
131
(a) (b)
Figure 7.1: BJT (npn) and FET (n-channel) comparison: (a) current-controlled device (BJT), (b)
voltage-controlled device (FET).
7.2 FET Types

We are going to cover three types (JFET, DMOSFET and EMOSFET) of eld eect transistors
(FETs)
• JFET: Junction Field-Eect Transistor

• MOSFET: Metal-Oxide-Semiconductor Field-Eect Transistor
◦ DMOSFET: Depletion-type MOSFET
◦ EMOSFET: Enhancement-type MOSFET
7.3 FET Operation

FET operation can be compared to a water spigot shown in Figure 7.2 below. Water ow signies the
charge ow. In n-channel FETs charge ow is the electron ow, and in p-channel FETs charge ow is
the hole ow.
Figure 7.2: Water analogy for the FET control mechanism.
132
• The source of water pressure can be likened to the applied voltage from drain to source, which
establishes a ow of water (charge) from the spigot (source) to the drain.
• The valve (gate), controls the ow of water (charge) to the drain by adjusting the width of
the pipe (channel). In a FET, gate adjusts the width of the channel via the applied potential
between gate and the source terminals.
7.4 Junction Field-Eect Transistor (JFET)

7.4.1 Construction
There are two types of JFETs: n-channel and p-channel. The n-channel whose construction is shown
in Figure 7.3 below is more widely used. There are three terminals: Drain, Source and Gate.
Figure 7.3: n-channel junction eld-eect transistor (JFET) construction.
Here,
• Drain (D ) and Source (S ) are connected to n-channel.

• Gate (G) is connected to the p-type material.
• For correct operation, gate-channel pn junction must be reverse-biased, i.e., VGS ≤ 0.
7.4.2 Operating Characteristics

There are three basic operating conditions for a JFET:
A. VGS = 0 and VDS > 0

B. VGS < 0 and VDS > 0
C. Voltage-controlled resistor
133
7.4.2.1 VGS = 0 and VDS > 0
A positive voltage VDS is applied across the channel and the gate is connected directly to the
source to establish the condition VGS = 0 V as shown in Figure 7.4(a) below. Under these
conditions the ow of charge is relatively uninhibited and is limited solely by the resistance of
the n-channel between drain and source.
(b)
(a)
Figure 7.4: JFET at VGS = 0 V and VDS > 0 V: (a) DC biasing, (b) variation of the gate-channel
junction reverse-bias voltages through the channel.
It is important to note that the depletion region is wider near the top of both p-type mate-
rials. The reason for the change in width of the region is best described through the help of
Figure 7.4(b) above. The result is that the upper region of the p-type material will be reverse-
biased by around 1.5 V, with the lower region only reverse-biased by 0.5 V.
Pinch-o
Figure 7.5: Pinch-o (VGS = 0 V, VDS = −VP ).
134
If VGS = 0 and VDS is further increased to a more positive voltage, then the depletion zone gets
so large that it pinches o the n-channel as shown in Figure 7.5 above.
The level of VDS that establishes this condition is referred to as the pinch-o voltage and is
denoted by −VP .
At pinch-o, ID maintains a saturation level dened as IDSS .

As VDS is increased beyond −VP , the region of close encounter between the two depletion regions
increases in length along the channel, but the level of ID remains essentially the same.
Output characteristics for VGS = 0

The resultant output characteristics curve for VGS = 0 V is shown in Figure 7.6 below.
Figure 7.6: Output characteristics, i.e., ID versus VDS , for VGS = 0 V.
7.4.2.2 VGS < 0 and VDS > 0

As VGS is negative the depletion regions are larger from the beginning, thus channel is narrower
from the beginning. So, the pinch-o will occur at lower voltage of VDS(sat) = VGS − VP , and the
saturation current will be smaller than IDSS . Once VGS = VP , the channel is blocked from the
start, and no current ows, i.e., ID = 0.
Consequently, when we draw the corresponding IV curves for each VGS , we obtain the complete
output characteristics shown in Figure 7.7 below.
135
Figure 7.7: Output characteristics of an n-Channel JFET with IDSS = 8 mA and VP = −4 V.
The region to the right of the pinch-o point of Figure 7.7 is the region employed in ampliers
and is commonly referred to as the constant-current, saturation, or linear amplication
region.
The region to the left of the locus (curve) of pinch-o values of Figure 7.7 is called the ohmic
or linear region.
On most specication sheets the pinch-o voltage is specied as VGS(off ) rather than VP .
The saturation current values (constant current values after pinch-o ) Figure 7.7 can be expres-
sed in terms of the control voltage VGS as
2
VGS
ID = IDSS 1 − (7.4.1)
VP
This equation is called the transfer characteristics equation and will be investigated in detail
later in the transfer characteristics section.
7.4.2.3 Voltage-Controlled Resistor (Ohmic Region)

The region to the left of the locus (curve) of pinch-o values of Figure 7.7 is called the ohmic
or linear region.
In this region, JFET can be used as a variable resistor, where VGS controls the drain-source
resistance (rd )
136
As VGS becomes more negative, the resistance (rd ) increases.
r0
rd = 2 (7.4.2)
VGS
1− VP
where r0 is the resistance with VGS = 0 V given in the specication sheets.
7.4.3 p-channel JFET

p-channel JFET acts the same as the n-channel JFET, except the polarities and currents are
reversed as shown in Figure 7.8 below.
Figure 7.8: p-Channel JFET biasing.
7.4.3.1 Characteristics
Output characteristics of a p-channel JFET is shown in Figure 7.9 below. Note that Also at
high levels of VDS the JFET reaches a breakdown situation where ID increases uncontrollably if
VDS > VDS(max) . Although we have not shown before breakdown region also exists in n-channel
JFETs.
137
Figure 7.9: Output characteristics of an p-Channel JFET with IDSS = 6 mA and VP = +6 V.
7.4.4 Circuit Symbol

The graphic symbols for the n-channel and p-channel JFETs are provided in Figure 7.10 below.
Note that the arrow at the gate terminal is pointing in for the n-channel device in Figure 7.10(a)
to represent the direction in which IG would ow if the pn junction was forward-biased.
For the p-channel device in Figure 7.10(b) the arrow at the gate terminal is pointing out.
(a) (b)
Figure 7.10: JFET circuit symbols: (a) n-channel, (b) p-channel.
7.4.5 Transfer Characteristics

The saturation current is determined by the control voltage VGS as follows
2
VGS
ID = IDSS 1 − (7.4.3)
VP
138
This equation is called the transfer characteristics (transfer from input to output, i.e., from
VGS to ID ) and can be plotted on a graph as shown in Figure 7.11 below
Figure 7.11: Transfer and output characteristics curves together for an n-channel JFET.
ID V
We can also plot this transfer characteristics as the ratios of
IDSS
and aG = GS without
aD = VP
needing the actual values of IDSS and VP as shown in Figure 7.12 below. The scaled transfer
characteristics is obtained as
aD = (1 − aG )2 (7.4.4)
where 0 ≤ aG ≤ 1 (note that also 0 ≤ aD ≤ 1). For aD = 0.5, we obtain aG ∼

= 0.3. So,
(0.3, 0.5)-point can be also used in plot generation. With the values of IDSS and VP , we know
that
VGS = aG VP (7.4.5)
ID = aD IDSS (7.4.6)
Figure 7.12: Scaled transfer characteristics curve.
139
7.5 Metal-Oxide-Semiconductor Field-Eect Transistors (MOS-
FETs)
MOSFETs have characteristics similar to JFETs and additional characteristics that make them
very useful.
There are two types of MOSFETs:
◦ Depletion-type MOSFET (DMOSFET)
◦ Enhancement-type MOSFET (EMOSFET)
The terms depletion and enhancement dene their basic mode of operation.
7.5.1 Depletion-Type MOSFET (DMOSFET)

7.5.1.1 Construction
There are two types of DMOSFETs: n-channel and p-channel. The n-channel whose construction
is shown in Figure 7.13 below is more widely used.
Figure 7.13: n-channel depletion-type MOSFET construction.
• A slab of p-type material is formed from a silicon base and is referred to as the substrate.
• For correct operation, substrate-channel pn reverse-biased.
junction must be
In this course, we will only consider the cases where the substrate (SS ) terminal is connected
(shorted) to the source (S ) terminal.
• Drain (D ) and Source (S ) are connected to n-channel via metal contacts.
• Gate (G) is connected to a metal contact surface but remains insulated from the n-channel
by a very thin silicon dioxide (SiO2 ) layer.
140
7.5.1.2 Operating Characteristics
In a DMOSFET, the channel is already present under no-bias conditions or VGS = 0 V.
Here, VGS controls the initial channel width (and value of the saturation current).
When VGS is xed, for a positive value of VDS the width of the channel gets narrower towards
the top of the channel as the voltage across the channel increases towards the top as shown in
Figure 7.14 below.
Eventually, when we increase the value of VDS , the channel will be pinched-o at some value of
VDS and the device will go into the saturation mode.
Figure 7.14: Change in channel width (and depletion region) for a xed value of VGS (VGS determines
the initial channel width) with VDS > 0.
• VGS controls the initial channel width by attracting or repelling electrons.

A negative value of VGS repels electrons (and attracts holes), so the channel gets narrower.
This mode is exactly like a JFET, and it is called the depletion mode.
A positive value of VGS attracts electrons (and repels holes), so the channel gets wider as shown
in Figure 7.15 below. Thus unlike JFETs, the channel width can be increased in DMOSFETs.
This mode is called the enhancement mode.
141
Figure 7.15: Increase (or enhancement) in initial channel width when VGS > 0.
7.5.1.3 Transfer Characteristics

Similar to JFET, DMOSFET transfer characteristics equation is given by
2
VGS
ID = IDSS 1 − (7.5.7)
VP
where VGS is allowed to be opposite polarity of VP (i.e., VGS > 0 allowed for n-channel DMOS-
FETs) as shown in Figure 7.16
Figure 7.16: Transfer and output characteristics curves together for an n-channel DMOSFET.
142
7.5.1.4 p-channel DMOSFET
The p-channel DMOSFET is similar to the n-channel, except that the voltage polarities and
current directions are reversed. Its construction (a), transfer characteristics (b) and output
characteristics (c) are shown in Figure 7.17 below.
Figure 7.17: p-channel DMOSFET with IDSS = 6 mA and VP = +6 V: (a) construction, (b) transfer
characteristics, (c) output characteristics.

The graphic symbols for the n-channel and p-channel DMOSFETs are provided in Figure 7.18
below. Notice that there is a gap between the gate and the channel representing the insulation
(SiO2 ) layer between the gate and the channel.
Note that the arrow at the substrate (SS ) terminal is pointing in for the n-channel device in
Figure 7.18(a) to represent the direction of substrate-channel pn junction.
For the p-channel device in Figure 7.18(b) the arrow at the substrate terminal is pointing out.
143
(a) (b)
Figure 7.18: DMOSFET circuit symbols: (a) n-channel, (b) p-channel.
7.5.3 Enhancement-Type MOSFET (EMOSFET)

7.5.3.1 Construction
There are two types of EMOSFETs: n-channel and p-channel. The n-channel whose construction
is shown in Figure 7.19 below is more widely used.
Figure 7.19: n-channel enhancement-type MOSFET construction.
• In an EMOSFET, no channel is present under no-bias conditions. We need to provide a positive

gate-to-source voltagegreater than a threshold voltage to initially form a channel between
drain and source terminals, i.e., VGS ≥ VGS(T h) .
• Thus, EMOSFET always works in the enhancement mode.

144
• Once VGS is xed and a channel is formed, it operates like a normal FET.
7.5.3.2 Transfer Characteristics

EMOSFET transfer characteristics equation plotted in shown in Figure 7.20 below is given by
2
ID = k VGS − VGS(T h) (7.5.8)
where k and VGS(T h) are device constants given in the specications sheets.
If k is not given, it can also be determined from a particular point (VGS0 , ID0 ) on the transfer
characteristics curve of the device as follows
ID0
k= 2 (7.5.9)
VGS0 − VGS(T h)
Figure 7.20: Transfer and output characteristics curves together for an n-channel EMOSFET.
Drain-to-source pinch-o (saturation) voltage VDS(sat) is also given by
VDS(sat) = VGS − VGS(T h) (7.5.10)
• EMOSFET transfer characteristics equation below can also be used for DMOSFETS
2
ID = k VGS − VGS(T h)
where
VGS(T h) = VP (7.5.11)
IDSS
k= (7.5.12)
VP2
Homework 7.1: Show that results (7.5.11) and (7.5.12) above are correct.
145
7.5.3.3 p-channel EMOSFET
The p-channel DMOSFET is similar to the n-channel, except that the voltage polarities and
current directions are reversed. Its construction (a), transfer characteristics (b) and output
characteristics (c) are shown in Figure 7.21 below.
Figure 7.21: p-channel EMOSFET with VGS(T h) = 2 V and k = 0.5 mA/V2 : (a) construction, (b)
transfer characteristics, (c) output characteristics.

The graphic symbols for the n-channel and p-channel EMOSFETs are provided in Figure 7.22
below. Notice that channel is represented as dashed line to reect the fact that a channel does
not exist under no-bias conditions.
Note that the arrow at the substrate (SS ) terminal is pointing in for the n-channel device in
Figure 7.22(a) to represent the direction of substrate-channel pn junction.
For the p-channel device in Figure 7.22(b) the arrow at the substrate terminal is pointing out.
146
(a) (b)
Figure 7.22: EMOSFET circuit symbols: (a) n-channel, (b) p-channel.
7.5.5 MOSFET Handling

MOSFETs are very static sensitive. Because of the very thin SiO2 layer between the external
terminals and the layers of the device, any small electrical discharge can establish an unwanted
conduction.
Protection:
◦ Always transport in a static sensitive bag
◦ Always wear a static strap when handling MOSFETs
◦ Apply voltage limiting devices between the Gate and Source, such as back-to-back Zeners
to limit any transient voltage.
7.6 Summary
The transfer curves and some important characteristics of the n-channel FETs are displayed in
Figure 7.23 below. A clear understanding of all the curves and parameters of the table will
provide a sucient background for the DC and AC analyses.
147
Figure 7.23: n-channel FET summary.
We can summarize the n-channel FET model with its state and circuit behaviour with the table below.
n-channel
FET Model
ID = 0, VGS < VGS(T h)
CUTOFF
IS = 0, IG = 0
2
ID = k VGS − VGS(T h) , VGS ≥ VGS(T h) ,
SATURATION
IS = ID , IG = 0 VDS ≥ VDS(sat)
OHMIC ID = not covered in this course, VGS ≥ VGS(T h) ,
(LINEAR) IS = ID , IG = 0 VDS < VDS(sat) , ID < ID(sat)
IDSS
• NOTE 1: For JFET and DMOSFETs, take VGS(T h) = VP and k=
VP2
• NOTE 2: For JFETs, make sure VP ≤ VGS ≤ 0.
148
• NOTE 3: VT h , VT and VTN (or VTP ) notations are also used in place of VGS(T h) .
We can show the circuit behaviour for the CUTOFF and SATURATION modes of the n-channel
FETs in Figure 7.24 below.
(b)
(a)
Figure 7.24: Circuit behaviour of the n-channel FET model: (a) Cuto state, (b) Saturation state
• For a p-channel FET transistor, the polarities and directions are simply reversed.
For example, the a p-channel FET will be ON (i.e., in SATURATION mode) when VSG ≥ VSG(T h)
(i.e., when VGS ≤ VGS(T h) ).
149
Chapter 8
DC Biasing of FETs
8.1 DC Biasing
8.2 FET DC Analysis
1. Draw the DC equivalent circuit (signal frequency is zero, i.e., f = 0)
a) Capacitors are open circuit, i.e., XC → ∞.

b) Kill the AC power sources (short-circuit AC voltage sources and open-circuit AC current
sources).
2. Write KVL for the GS -loop (i.e., GS -loop load line (or transfer load line) equation)
a) Draw the transfer characteristics curve using the appropriate transfer characteristics equa-
tion.
b) Draw the GS -loop load line over the transfer characteristics curve
c) The intersection gives us IDQ and VGSQ .

NOTE: You can also solve two equations simultaneously and obtain the result analytically
by solving the resultant quadratic equation. However, graphical way is less error-prone if
the graph has a ne resolution.
3. Write KVL for the DS -loop (i.e., DS -loop load line (or output load line) load line equation)
a) Calculate VDSQ using IDQ value from Step 2c.
8.3 DC Biasing Circuits

Most common four common-source biasing circuits are given below
JFET Biasing Circuits
150
− Fixed-Bias
− Self-Bias
− Voltage-Divider
DMOSFET Biasing Circuits

− Self-Bias
− Voltage-Divider
EMOSFET Biasing Circuits

− Voltage-Feedback
− Voltage-Divider
8.3.1 Fixed-Bias Conguration

A xed-bias JFET circuit is given in Figure 8.1 below
Figure 8.1: Fixed-bias JFET circuit.
151
Figure 8.2: DC equivalent circuit (with IG = 0) of the xed-bias conguration in Figure 8.1.
Note that RG is ignored as IG = 0.
8.3.1.1 Gate-Source Loop

We can write KVL equation on the GS -loop
VGS = −VGG . (8.3.1)
Then, we obtain VGSQ and IDSQ by solving the following two equations simultaneously
VGS = −VGG . . . transfer load-line (8.3.2)

2
VGS
ID = IDSS 1 − . . . transfer characteristics (8.3.3)
VP
The solution is trivial in this case and we obtain the result as
VGSQ = −VGG (8.3.4)

2
VGSQ
IDQ = IDSS 1 − (8.3.5)
VP
We can also obtain the result graphically by plotting equations (8.3.2) and (8.3.3) on the same
graph as shown in Figure 8.3 below.
152
Figure 8.3: Graphical solution (for transfer load-line and transfer characteristics equations) for the
xed-bias conguration in Figure 8.1.
8.3.1.2 Drain-Source Loop

Let us write down the KVL equation on the DS -loop
VDD − ID RD − VDS = 0 (8.3.6)
VDS = VDD − ID RD . . . DC load-line equation (8.3.7)
As we already obtained IDQ in Figure 8.3 we nd VDSQ as
VDSQ = VDD − IDQ RD (8.3.8)
Thus, we obtained the Q-point (IDQ , VDSQ ), i.e., the operating point.
8.3.2 Self-Bias Conguration

A xed-bias JFET circuit is given in Figure 8.4 below
153
Figure 8.4: Self-bias JFET circuit.
Figure 8.5: DC equivalent circuit (with IG = 0) of the self-bias conguration in Figure 8.4.

−VGS − IS RS = 0 (8.3.9)
VGS = −ID RS . . . as IS = ID . (8.3.10)
154
VGS = −ID RS . . . transfer load-line (8.3.11)

2
VGS
VP
It is better to obtain the result graphically by plotting equations (8.3.11) and (8.3.12) on the
same graph as shown in Figure 8.6 below.
self-bias conguration in Figure 8.4.
The graphically obtained current value IDQ may be rened using equations (8.3.11) and (8.3.12)
in an iteration loop as follows
1. Insert graphically obtained ID into (8.3.11) and obtain a VGS value
2. Insert VGS obtained in Step 1 into (8.3.12) and obtain a new ID value to be used in Step 1.
3. Repeat Step 1 and Step 2 until ∆ID , the dierence between the old ID used in Step 1 and
new ID obtained in Step 2, is small enough.

VDD − ID RD − VDS − IS RS = 0 (8.3.13)
VDD − ID RD − VDS − ID RS = 0 . . . as IS = ID (8.3.14)
VDD − ID (RD + RS ) − VDS = 0 . . . DC load-line equation (8.3.15)
155
VDSQ = VDD − IDQ (RD + RS ) (8.3.16)
Figure 8.7: Self-bias JFET circuit for Example 8.1.
Solution: Let us express VGS using the KVL equation of GS -loop and ID from the transfer
characteristics equation
VGS = −ID RS = −1k ID

2 2
VGS VGS
ID = IDSS 1 − = (8m) 1 +
VP 6
where −6 ≤ VGS ≤ 0.
We obtain IDQ and VGSQ by drawing these two equations on the same graph as shown in
Figure 8.8 below
156
Figure 8.8: Obtaining IDQ graphically for the circuit in Figure 8.7.
Finally, we obtain VDSQ from the DS -loop as
VDSQ = VDD − IDQ (RD + RS ) = 20 − (2.6m) (3.3k + 1k) = 8.82 V.
8.3.3 Voltage-Divider Bias Conguration

A voltage-divider bias JFET circuit is given in Figure 8.9 below
Figure 8.9: Voltage-divider bias JFET circuit.
157
Figure 8.10: DC equivalent circuit of the voltage-divider conguration in Figure 8.9.

R2
VG − VGS − IS RS = 0 . . . where VG = VDD (8.3.17)
R1 + R2
VGS = VG − ID RS . . . as IS = ID . (8.3.18)
VGS = VG − ID RS . . . transfer load-line (8.3.19)

2
VGS
VP
voltage-divider conguration in Figure 8.9.
158

VDD − ID RD − VDS − IS RS = 0 (8.3.21)
VDD − ID RD − VDS − ID RS = 0 . . . as IS = ID (8.3.22)
VDD − ID (RD + RS ) − VDS = 0 . . . DC load-line equation (8.3.23)
VDSQ = VDD − IDQ (RD + RS ) (8.3.24)
Figure 8.12: Voltage-divider bias JFET circuit for Example 8.2.
Solution: Let us nd VG , and express VGS using the KVL equation of GS -loop and ID from
the transfer characteristics equation
R2 0.27M
VG = VDD = 16 = 1.82 V.
R1 + R2 2.1M + 0.27M
VGS = VG − ID RS = 1.82 − 1.5k ID
2 2
VGS VGS
ID = IDSS 1 − = (8m) 1 +
VP 4
159
Figure 8.13 below
VDSQ = VDD − IDQ (RD + RS ) = 16 − (2.4m) (2.4k + 1.5k) = 6.64 V.
Example 8.3: For the gure below, calculate Q-point. Repeat for RS = 150 Ω.
Figure 8.14: Voltage-divider bias DMOSFET circuit for Example 8.3.
160
R2 10M
VG = VDD = 18 = 1.5 V.
R1 + R2 110M + 10M
VGS = VG − ID RS = 1.5 − 0.75k ID
2 2
VGS VGS
ID = IDSS 1 − = (6m) 1 +
VP 3
where VGS ≥ −3 V.
Figure 8.15 below
Figure 8.15: Obtaining IDQ graphically for the circuit in Figure 8.14 with RS = 750 Ω.
Let us repeat the calculations for RS = 150 Ω. Transfer load-line equation (GS -loop equation)
changes as below
VGS = VG − ID RS = 1.5 − 0.15k ID
We reobtain IDQ and VGSQ by redrawing the transfer load-line and transfer characteristics equa-
tions on the same graph as shown in Figure 8.16 below
161
Figure 8.16: Obtaining IDQ graphically for the circuit in Figure 8.14 with RS = 150 Ω.
Finally, VDSQ is recalculated from the DS -loop as
Figure 8.17: Voltage-divider bias EMOSFET circuit for Example 8.4.
162
R2 18M
VG = VDD = 40 = 18 V.
R1 + R2 22M + 18M
VGS = VG − ID RS = 18 − 0.82k ID
2
ID = k VGS − VGS(T h) = (0.12m) (VGS − 5)2
where VGS ≥ 5 V .
Figure 8.18 below
VDSQ = VDD − IDQ (RD + RS ) = 40 − (6.7m) (3k + 0.82k) = 14.4 V.
8.3.4 Voltage-Feedback Bias Conguration

A voltage-feedback bias EMOSFET circuit is given in Figure 8.19 below
Figure 8.19: Voltage-feedback bias EMOSFET circuit.
163
Figure 8.20: DC equivalent circuit (with IG = 0) of the voltage-feedback conguration in Figure 8.19.

VDD − VGS − ID RD = 0 (8.3.25)
VGS = VG − ID RD (8.3.26)
VGS = VDD − ID RD . . . transfer load-line (8.3.27)

2
ID = k VGS − VGS(T h) . . . transfer characteristics (8.3.28)
voltage-feedback conguration in Figure 8.19.
164

VDD − ID RD − VDS = 0 . . . DC load-line equation (8.3.29)
VDSQ = VDD − IDQ RD (8.3.30)
Note that, here VDSQ = VGSQ .
Figure 8.22: Voltage-feedback bias EMOSFET circuit for Example 8.5.
VGS = VDD − ID RD = 12 − 2k ID
2
ID = k VGS − VGS(T h) = (0.24m) (VGS − 3)2
165
where VGS ≥ 3 V.
Figure 8.23 below
VDSQ = VDD − IDQ RD = 12 − (2.75m)(2k) = 6.4 V.
8.3.5 p-channel FETs

The analysis for p-channel FET circuits is the same as that for n-channel FET circuits.
The only dierences are that
1. Currents are owing in the opposite direction.
2. Voltages have opposite polarity, e.g., VSG ≥ VSG(T h) (i.e., VGS ≤ VGS(T h) ) is needed to turn
on a p-channel FET.
3. If properly biased, then VS > VD , i.e., VSD > 0.
166
Figure 8.24: Voltage-divider bias JFET circuit for Example 8.6.
R2 20k
VG = VDD = (−20) = −4.55 V.
R1 + R2 68k + 20k
VGS = VG + ID RS = −4.55 + 1.8k ID
2 2
VGS VGS
ID = IDSS 1 − = (8m) 1 −
VP 4
Figure 8.25 below
167
VDSQ = VDD + IDQ (RD + RS ) = (−20) + (3.4m) (2.7k + 1.8k) = −4.7 V.
Thus, VSDQ = 4.7 V.
8.4 Practical Applications

Some practical FET applications are listed below:
• Voltage-controlled resistor
• JFET voltmeter
• Timer network
• Fiber optic circuitry
• MOSFET relay driver
8.5 Summary
Summary of n-channel JFET and MOSFET bias circuits are given in Figure 8.26 and Figure 8.27,
respectively.
Figure 8.26: n-channel JFET bias circuits.
168
Figure 8.27: n-channel MOSFET bias circuits.
169
Chapter 9
AC-DC Load Lines of FET Circuits
9.1 FET AC Analysis

1. Draw the AC equivalent circuit (signal frequency is innity, i.e., f = ∞)
a) Capacitors are short circuit, i.e., XC → 0.

b) Kill the DC power sources (short-circuit DC voltage sources and open-circuit DC current
sources).
2. Write KVL for the loop which contains DS terminals
a) Develop AC load-line equation.
3. Draw AC-DC load lines
a) Find available swings for a given input or nd maximum undistorted swings.
9.1.1 AC and DC Load Lines

• AC and DC load line equations of FETs are similar to the AC and DC load line equations of
BJTs where gate (G), drain (D ) and source (S ) replace base (B ), collector (C ) and emitter (E ),
respectively, in the subscripts of the equations.
• Thus, FET DC load line equation is given by
VDS = VDD − ID RDC (9.1.1)
where RDC is the equivalent output-loop (DS -loop) DC resistance. Hence, the rearranged DC
load line equation (DC output equation) is given by
−1 VDD
ID = VDS + (9.1.2)
RDC RDC
170
• Similarly, FET AC load line equation is given by
vDS = −iD Rac + VDSQ + IDQ Rac (9.1.3)
where Rac is the equivalent output-loop (DS -loop) AC resistance, vDS = VDSQ + vds and iD =
IDQ + id . Hence, the rearranged AC load line equation (AC output equation) is given by
−1 VDSQ
iD = vDS + IDQ + (9.1.4)
Rac Rac
Let us draw DC and AC load lines together as shown in Figure 9.1 below.
Figure 9.1: AC-DC load lines for FETs.
Once the Q-point is known, peak values of the maximum undistorted voltage and current
swings vds(p)(max) and id(p)(max) are given by
vds(p)(max) = min (VDSQ , IDQ Rac ) (9.1.5)
and
VDSQ
id(p)(max) = min IDQ , (9.1.6)
Rac
respectively
9.1.2 Maximum Symmetric Undistorted Swing Design

Once we obtained the desired Q-point in the middle of the AC load line, i.e.,
VDD
IDQ = (9.1.7)
RDC + Rac
171
then the maximum available undistorted output swings will be obtained as shown in Figure 9.2
below.
Figure 9.2: Maximum undistorted swing design for FETs with Q-point in the middle of the AC load
line.
9.1.3 Other Amplier Congurations

We developed and plotted AC-DC load lines for the common-source conguration. Now, let us look
at other congurations.
• Common-gate (CG) conguration
1. Obtain Rac from the DG loop.
2. Obtain RDC from the DS loop.
3. Draw the AC-DC load lines iD vs. vDS as before.
NOTE: You can also draw the AC-DC load lines as iD vs. vDG by shifting the voltage axis
byVGSQ volts to the left as VDGQ = VDSQ − VGSQ . Thus, current axis will be drawn at
VDG |ID =0 = −VGSQ volts not at 0 V.
• Common-drain (CD) conguration (also known as source-follower)
1. Obtain Rac and RDC from the DS loop as before.
2. Draw the AC-DC load lines iS vs. vDS where iS = iD .

• For p-channel FETs, we express the currents in the reverse direction (i.e., having positive current
values) and reverse the polarity of the terminal voltages (i.e., having positive voltage values),
and then draw the AC-DC load lines, e.g., iD vs. vSD .
172
Chapter 10
BJT Small-Signal Analysis
10.1 Purpose of SSAC Analysis

The purpose of small-signal AC (SSAC) analysis to determine the three parameters of an am-
plier input resistance, output resistance and gain. In this course, we are mostly interested
in the two-port voltage-gain amplier model shown in Figure 10.1 below.
Figure 10.1: Two-port voltage-gain amplier model.
• Input resistance Ri is dened by the no-load input voltage of the amplier divided by the no-load
input current to the amplier, i.e.,

vi
Ri = (10.1.1)
ii RL =∞
NOTE: Input resistance cannot include the source resistance Rs .

• Output resistance Ro is obtained by the test-voltage method, i.e., by dividing the test voltage
value with the measured test current value. In the test-voltage method, load is replaced with a
test voltage vtest and the independent power sources (vs or is ) are killed, i.e., vs = 0 or is = 0.
Thus, output resistance Ro is given by

vtest
Ro = (10.1.2)
itest vs =0,RL =vtest
173
NOTE: Output resistance cannot include the load resistance RL .
• No-load voltage gain Av (or AVNL ) is dened by

vo
Av = (10.1.3)
vi RL =∞
• When load is connected, the voltage gain will decrease due to the voltage-divider consisting of
RL and Ro . So, voltage gain with load, AV , is given by

vo vo Av vi RL
AV = = = Av (10.1.4)
vi A v vi vi Ro + RL
• Current gain Ai is dened by the output current versus the input current, i.e.,
io vo /RL Ri Ri
Ai = = = AV = Av (10.1.5)
ii vi /Ri RL Ro + RL
• Finally, overall voltage gain AVs is given by
vo RL Ri
AVs = = Av (10.1.6)
vs Ro + RL Rs + Ri
10.1.1 BJT SSAC Analysis Steps

1. Draw the SSAC equivalent circuit
a) Draw the AC equivalent circuit (signal frequency is innity, i.e., f = ∞)

i. Capacitors are short circuit, i.e., XC → 0.
ii. Kill the DC power sources (i.e., AC value of DC sources is zero).
b) Replace BJT with its small-signal equivalent model (e.g., hybrid equivalent model or re
model).
2. Calculate the three amplier parameters: Ri , Ro and Av

a) Calculate no-load input resistance, Ri = viii .

RL =∞
b) Calculate output resistance, Ro .

vo
c) Calculate no-load voltage gain, Av = vi
.
RL =∞
174
10.2 BJT Small-Signal Models
A small-signal model is an equivalent circuit that represents the SSAC characteristics of the transistor.
It uses circuit elements that approximate the behavior of the transistor.
Two commonly used models used in SSAC analysis of BJTs are given below:
• hybrid equivalent model
• re model
Mostly, we are going to use the hybrid equivalent model. But, we are going to introduce and
provide results for the re model as well.
NOTE: Small-signal equivalent model and its analysis are the same for both npn and pnp transistors.
10.2.1 Hybrid Equivalent Model

Parameters of the hybrid equivalent circuit provide the entire set on the specication sheet of a
BJT and cover all operating conditions. Generalized hybrid equivalent circuit for any transistor
conguration is provided in Figure 10.2 below.
Figure 10.2: Complete hybrid equivalent circuit.
Here,
• hi : input resistance
• hr : reverse transfer voltage ratio (vi /vo )
• hf : forward transfer current ratio (io /ii )
• ho : output conductance
For a specic conguration, the model parameters modied with the label of the common-mode
terminal in their subscript. So, common-emitter and common-base congurations and their hybrid
equivalent models are shown in Figure 10.3 and Figure 10.4 below, respectively.
175
Figure 10.3: Common-emitter conguration and its complete hybrid equivalent circuit.
Figure 10.4: Common-base conguration and its complete hybrid equivalent circuit.
• For the common-collector conguration, we always use the common-emitter hybrid equivalent
model.
10.2.1.1 Simplied Hybrid Equivalent Model

Because hr is normally a relatively small quantity, its removal is approximated by hr ≈ 0 and hr vo = 0,
resulting in the simplied hybrid equivalent circuit shown in Figure 10.5 below. In this course, we are
going to use the simplied hybrid equivalent model.
Figure 10.5: Simplied hybrid equivalent circuit.
176
This circuit, can be further simplied if a value for the parameter ho or 1/ho is not provided. In that
case, we can safely assume that ho = 0 or 1/ho = ∞ resulting in the approximate hybrid equivalent
circuit shown in Figure 10.6 below.
Figure 10.6: Approximate hybrid equivalent circuit.
10.2.1.2 Common-Emitter Hybrid Equivalent Model

Common-emitter simplied hybrid equivalent circuit is shown in Figure 10.7 below.
Figure 10.7: Common-emitter simplied hybrid equivalent circuit.
Here, the h-parameters are dened as below

∂VBE γ
hie = = . . . see diode dynamic resistance in Section 1.3.11 (10.2.7)
∂IB Q-point IBQ

∂IC
hf e = = βac (10.2.8)
∂IB Q-point

∂VCE VA + VCEQ
1/hoe = = . . . VA is the early voltage and VA VCEQ (10.2.9)
∂IC Q-point ICQ
Typical values of hf e run from 50 to 200, hie run from 500 Ω to 7 kΩ, and 1/hoe run from 40 kΩ to
100 kΩ.
Note that, as ICQ = βIBQ and IEQ = (β + 1) IBQ , we can also express hie in terms of ICQ or IEQ as
follows
177
γ
hie = (10.2.10)
IBQ
γ
= hf e (10.2.11)
ICQ
γ
= (hf e + 1) (10.2.12)
IEQ
where γ = kT /q is the thermal voltage and have xed values for a given temperature, e.g., γ = 26 mV
at room temperature T = 300 K.
10.2.1.3 Common-Emitter re Model

Common-emitter re model is shown in Figure 10.8 below.
Figure 10.8: Common-emitter re model.
One-to-one correspondence with the h-parameters are given below,
hf e = β (10.2.13)
hie = (β + 1) re ∼
= βre (10.2.14)
1/hoe = ro . (10.2.15)
Thus, β = hf e , βre = hie and ro = 1/hoe .
10.2.1.4 Common-Base Hybrid Equivalent Model

Common-base simplied hybrid equivalent circuit is shown in Figure 10.9 below.
178
Figure 10.9: Common-base simplied hybrid equivalent circuit.
Here, the h-parameters are dened as below,

∂VBE γ
hib = = . . . see diode dynamic resistance in Section 1.3.11 (10.2.16)
∂IE Q-point IEQ

∂IC
hf b = − = −αac ∼
= −1 (10.2.17)
∂IE Q-point

∂VCB
1/hob = ≈∞ (10.2.18)
∂IC Q-point
Typically,hf b = −1, and hib run from 5Ω to 50 Ω, and 1/hob is in the megohm range. Thus,
1/hob 1/hoe .
Note that, the relationship between hib and hie is given below
hie = (hf e + 1) hib (10.2.19)
hie
or hib = .
hf e + 1
10.2.1.5 Common-Base re Model

Common-base re model is shown in Figure 10.10 below.
179
Figure 10.10: Common-base re model.
One-to-one correspondence with the h-parameters are given below
hf b = −α (10.2.20)
hib = re (10.2.21)
1/hob = ro . (10.2.22)
Thus, α = −hf b ∼
= 1, re = hib and ro = 1/hob ∼
= ∞. Note that, minus sign is due to the direction of
the current source.
10.2.1.6 Phase Relationship

The phase relationship between input and output depends on the amplier conguration circuit as
listed below.
• Common-Emitter: 180 degrees
• Common-Base: 0 degrees
• Common-Collector: 0 degrees (Emitter-Follower)
10.3 Common-Emitter Fixed-Bias Conguration

Common-emitter xed-bias conguration is given in Figure 10.11 below
180
Figure 10.11: Common-emitter xed-bias conguration.
Let us start SSAC analysis by drawing the AC equivalent circuit as shown in Figure 10.12 below
Figure 10.12: AC equivalent circuit of the xed-bias circuit in Figure 10.11.
Then, we are going to replace BJT with its common-emitter hybrid equivalent model as shown
in Figure 10.13 below
Figure 10.13: Small-signal equivalent circuit of the xed-bias circuit in Figure 10.11.
181
• Obtain hf e and 1/hoe from the specication sheet of the transistor or by testing the transistor
26 mV 26 mV
using a curve tracer. Calculate hie using the DC analysis values as hie = = hf e .
IBQ ICQ
10.3.1 Input Resistance

Input resistance Ri is given as

vi
Ri = = RB ||hie (10.3.23)
ii RL =∞
• If RB ≥ 10hie , then Ri simplies to Ri = hie .

• Input resistance Ri according to the re model is given by
Ri = RB ||βre (10.3.24)
10.3.2 Voltage Gain

No-load voltage gain Av is given by

vo vo hf e ib ib
Av = =
vi RL =∞ hf e ib ib vi

1
= (−RC ||1/hoe ) (hf e )
hie
hf e (RC ||1/hoe )
=−
hie
As a result, Av is given by

vo hf e (RC ||1/hoe )
Av = =− (10.3.25)
vi RL =∞ hie
• No-load voltage gain Av according to the re model is given by

RC ||ro
Av = − (10.3.26)
re
• If 1/hoe ≥ 10RC , no-load voltage gain Av reduces to
hf e RC RC
Av = − . . . re model: Av = − (10.3.27)
hie re
• For the circuit in Figure 10.13, we can obtain the current gain Ai as follows
io vo /RC Ri vo
Ai = = =
ii vi /Ri RC vi
Ri
= Av (10.3.28)
RC
• If 1/hoe ≥ 10RC and RB ≥ 10hie , current gain Ai reduces to
Ai = −hf e . . . re model: Ai = −β (10.3.29)
182
10.3.3 Output Resistance
Figure 10.14: Test voltage circuit of Figure 10.13 in order to calculate the output resistance Ro .
Output resistance, i.e., Thévenin equivalent resistance, Ro is calculated using the test voltage
circuit in Figure 10.14 above. Note that in the circuit ib = 0, so hf e ib = 0 as well.

vtest
Ro = = RC ||1/hoe (10.3.30)
• If 1/hoe ≥ 10RC , then Ro simplies to Ro = RC .

• Output resistance Ro according to the re model is given by
Ro = RC ||ro (10.3.31)
10.3.4 Phase Relationship
Figure 10.15: Demonstrating the 180◦ phase shift between input and output waveforms.
• The phase relationship between input and output is 180 degrees as shown in Figure 10.15 above.
• The negative sign used in the voltage gain formulas indicates the inversion.
183
10.4 Common-Emitter Voltage-Divider Bias Conguration
Common-emitter voltage-divider bias conguration is given in Figure 10.16 below
Figure 10.16: Common-emitter voltage-divider bias conguration.
Corresponding SSAC equivalent circuit is shown in Figure 10.17 below
Figure 10.17: Small-signal equivalent circuit of the voltage-divider bias circuit in Figure 10.16.


vi
Ri = = R1 ||R2 ||hie (10.4.32)
ii RL =∞

Ri = R1 ||R2 ||βre (10.4.33)
184
10.4.2 Voltage Gain

vo vo hf e ib ib
Av = =

1
= (−RC ||1/hoe ) (hf e )
hie
hf e (RC ||1/hoe )
=−
hie

vo hf e (RC ||1/hoe )
Av = =− (10.4.34)
vi RL =∞ hie

RC ||ro
Av = − (10.4.35)
re
• If 1/hoe ≥ 10RC , no-load voltage gain Av reduces to
hf e RC RC
Av = − . . . re model: Av = − (10.4.36)
hie re
io vo /RC Ri vo
Ai = = =
ii vi /Ri RC vi
Ri
= Av (10.4.37)
RC
• If 1/hoe ≥ 10, and given R0 = R1 ||R2 , current gain Ai reduces to
R0 R0
Ai = −hf e . . . re model: Ai = − (10.4.38)
R0 + hie R0 /β + re
185

vtest
Ro = = RC ||1/hoe (10.4.39)
• If 1/hoe ≥ 10RC , then Ro simplies to Ro = RC .

Ro = RC ||ro (10.4.40)

• Phase relationship between input and output of a common-emitter amplier conguration if
always 180 degrees. This is independent of the type of the bias-conguration.
10.5 Common-Emitter Unbypassed-Emitter Bias Conguration

Common-emitter unbypassed-emitter bias conguration is given in Figure 10.19 below
Figure 10.19: Common-emitter unbypassed-emitter bias conguration.
186
Figure 10.20: Small-signal equivalent circuit of the unbypassed-emitter bias circuit in Figure 10.19.
• When RE is not bypassed, we normally assume 1/hoe = ∞ in order to reduce the calculation
complexity. Because of the feedback, even 1/hoe 6= ∞ the results do not really change at all.


vi
Ri = = RB ||Rb . . . Rb = hie + (hf e + 1) RE
ii RL =∞
= RB || [hie + (hf e + 1) RE ]
As a result, Ri is given by

vi
Ri = = RB || [hie + (hf e + 1) RE ] (10.5.41)
ii RL =∞

Ri = RB || (β + 1) (re + RE ) ∼
= RB ||β (re + RE ) (10.5.42)
10.5.2 Voltage Gain


vo vo hf e ib ib
Av = =

1
= (−RC ) (hf e )
Rb
hf e RC
=−
hie + (hf e + 1) RE
187

vo hf e RC
Av = =− (10.5.43)
vi RL =∞ hie + (hf e + 1) RE

RC
Av = − (10.5.44)
re + RE
• If (hf e + 1) RE ≥ 10hie , no-load voltage gain Av reduces to
RC RC
Av = − . . . re model: Av = − (10.5.45)
RE RE
io vo /RC Ri vo
Ai = = =
ii vi /Ri RC vi
Ri
= Av (10.5.46)
RC
• Resultant current gain Ai is given by
RB RB
Ai = −hf e . . . re model: Ai = − (10.5.47)
RB + Rb RB /β + re + RE

vtest
Ro = = RC (10.5.48)
188
Ro = RC (10.5.49)

10.6 Emitter-Follower Conguration

Emitter-follower (common-collector) conguration is given in Figure 10.22 below
Figure 10.22: Emitter-follower conguration.
189
Figure 10.23: Small-signal equivalent circuit of the emitter-follower circuit in Figure 10.22.
• When RE is not bypassed, we normally assume 1/hoe = ∞ in order to reduce the calculation
complexity.


vi
Ri = = RB ||Rb . . . Rb = hie + (hf e + 1) RE
ii RL =∞
= RB || [hie + (hf e + 1) RE ]

vi
Ri = = RB || [hie + (hf e + 1) RE ] (10.6.50)
ii RL =∞

Ri = RB || (β + 1) (re + RE ) ∼
= RB ||β (re + RE ) (10.6.51)
10.6.2 Voltage Gain


vo vo ib
Av = =
vi RL =∞ ib vi

1
= [(hf e + 1) RE ] . . . Rb = hie + (hf e + 1) RE
Rb
(hf e + 1) RE ∼
= =1
hie + (hf e + 1) RE
190

vo (hf e + 1) RE ∼
Av = = =1 (10.6.52)
vi RL =∞ hie + (hf e + 1) RE

RE ∼
Av = =1 (10.6.53)
re + RE
io vo /RE Ri vo
Ai = = =
ii vi /Ri RE vi
Ri
= Av (10.6.54)
RE
• Resultant current gain Ai is given by,
RB RB
Ai = (hf e + 1) . . . re model: Ai = (10.6.55)
RB + Rb RB / (β + 1) + re + RE
circuit in Figure 10.24 above.

vtest hie
Ro = = RE || (10.6.56)
hf e + 1
191
Ro = RE ||re (10.6.57)
• If 1/hoe 6= ∞, then replace RE with (RE ||1/hoe ) in Ri , Av and Ro calculations.
• If a voltage source with source resistance Rs is connected to the input, replace hie with (hie + RB ||Rs )
in Ro calculations.

• Emitter-follower (common-collector) conguration has no phase shift between input and out-
put.
10.7 Common-Emitter Collector Feedback Conguration

Common-emitter collector feedback bias conguration is given in Figure 10.25 below
Figure 10.25: Common-emitter collector feedback bias conguration.
Figure 10.26: Small-signal equivalent circuit of the collector feedback bias circuit in Figure 10.25.
192

vi hie hie + hf e RC
Ri = = . . . if = − ib
ii RL =∞ 1 + ie +hf e RC
h RF + RC
RF +RC
∼ hie
= . . . hf e RC hie
hf e RC
1+
RF + RC

vo ∼ hie
Ri = = (10.7.58)
vi RL =∞ hf e RC
1+
RF + RC
βre
Ri ∼
= (10.7.59)
βRC
1+
RF + RC
10.7.2 Voltage Gain

vo hf e RF − hie −RC hie + hf e RC
Av = = . . . if = − ib
vi RL =∞ RF + RC hie RF + RC

∼ h f e RF −R C
= . . . hf e RF hie
RF + RC hie
hf e RC
≈− . . . RF RC
hie

vo hf e RC
Av = ≈− (10.7.60)
vi RL =∞ hie

RC
Av ≈ − (10.7.61)
re
io vo /RC Ri vo
Ai = = =
ii vi /Ri RC vi
Ri
= Av (10.7.62)
RC
hf e (RF + RC ) RF + RC
Ai ∼
=− . . . re model: Ai = − (10.7.63)
RF + (hf e + 1) RC RF /β + RC
193

vtest
Ro = = RC ||RF (10.7.64)

Ro = RC ||RF (10.7.65)
• If 1/hoe 6= ∞, then replace RC with (RC ||1/hoe ) in Ri , Av and Ro calculations.
• If a voltage source with source resistance Rs is connected to the input, replace RF with
[RF (Rs + hie ) / (hf e Rs + hie )] in Ro calculations.

10.8 Common-Base Conguration

Common-base conguration is given in Figure 10.28 below
Figure 10.28: Common-base conguration.
194
Figure 10.29: Small-signal equivalent circuit of the common-base circuit in Figure 10.28.
hie 26 mV
• Here, hib = = and hf b = −αac = −1.
hf e + 1 IEQ


vi
Ri = = RE ||hib (10.8.66)
ii RL =∞
• If RE ≥ 10hib , then Ri simplies to Ri = hib .

Ri = RE ||re (10.8.67)
10.8.2 Voltage Gain


vo vo hf b ie ie
Av = =
vi RL =∞ hf b ie ie vi

1
= (−RC ) (hf b )
hib
RC
= . . . hf b = −1
hib

vo RC
Av = = (10.8.68)
vi RL =∞ hib

RC
Av = (10.8.69)
re
195
io vo /RC Ri vo
Ai = = =
ii vi /Ri RC vi
Ri
= Av (10.8.70)
RC
RE ||hib RE ||re
Ai = ≈1 . . . re model: Ai = ≈1 (10.8.71)
hib re
circuit in Figure 10.30 above. Note that in the circuit ie = 0, so hf b ie = 0 as well.

vtest
Ro = = RC (10.8.72)

Ro = RC (10.8.73)
• If 1/hob 6= ∞, then replace RC with (RC ||1/hob ) in Ri , Av and Ro calculations.

• A common-base amplier conguration has no phase shift between input and output
196
Example 10.1: Consider the common-base BJT amplier in the gure below.
a) Perform DC analysis and nd the Q-point.

b) Evaluate the overall voltage gain AVs and the current gain Ai .
c) Sketch vo on the AC+DC load line graph when
i. vs = 100 sin (ωt) mV,
ii. vs = 900 sin (ωt) mV.
Solution: a) Let us rst draw the DC equivalent circuit rst as shown in Figure 10.32 below,
(a)
(b)
Figure 10.32: DC equivalent circuit of Figure 10.31: (a) as it is (b) Thévenin applied.
Here, RE = RE1 + RE2 = 0.2k + 1.5k = 1.7 kΩ.
197
Now, let us calculate VBB , RBB , ICQ , VCEQ and VCBQ

30k
VBB = (10) = 1.43 V,
30k + 180k
RBB = 30k||180k = 25.71 kΩ,
1.43 − 0.7
ICQ ∼= IEQ = = 0.4 mA,
25.71k/201 + 1.7k
VCEQ = 10 − (0.4m)(4.7k + 1.7k) = 7.44 V,
VCBQ = 7.44 − 0.7 = 6.74 V.
b) In order to calculate the voltage gain, we need to draw the common-base SSAC equivalent
circuit. As it is not given 1/hob = ∞. Let us now calculate hib as
26m
hib = = 65 Ω.
0.4m
So, the small-signal equivalent circuit is given in Figure 10.32 below
Figure 10.33: Small-signal equivalent circuit of Figure 10.31.
Now, let us calculate input resistance Ri and voltage gain with load AV as follows
Ri = RE2 || (RE1 + hib ) = 1.5k||(200 + 65) ∼ = 225 Ω

vo vo hf b ie ie
AV = =
vi hf b ie ie vi

1 RC ||RL
= (−RC ||RL ) (hf b ) =
RE1 + hib RE1 + hib
4.7k||10k 3.2k
= = = 12.08.
200 + 65 0.265k
Thus, overall voltage gain AVs and current gain Ai are given by

vo vo vi Ri 225
AVs = = = AV = (12.08)
vs vi vs Rs + Ri 100 + 225
= 8.36,

io vo /RL Ri 0.225k
Ai = = = AV = (12.08)
ii vi /Ri RL 10k
= 0.27.
198
c) Let us write down the AC load line equation for this common-base amplier, noting that
vo = vcb = −ic (RC ||RL ) = −ic Rac and vcb = vce − vbe = vce − REhib+hib vi ≈ vce )
1
vCB = −iC Rac + VCBQ + ICQ Rac . . . VCBQ = VCEQ − VBEQ

vCE − VBEQ = −iC Rac + VCEQ − VBEQ + ICQ Rac . . . vCB ≈ vCE − VBEQ
vCE = −iC Rac + VCEQ + ICQ Rac
So, we calculate Rac from the C-B loop and RDC from the C-E loop as follows
Rac = RC ||RL = 4.7k||10k = 3.2 kΩ,

RDC = RC + RE = 4.7k + 1.7k = 6.4 kΩ.
Note that, maximum available undistorted swing amplitude is
min (VCEQ , ICQ Rac ) = min(7.44, (0.4m)(3.2k)) = min(7.44, 1.28) = 1.28 V.
Thus, as AVs = 8.36, maximum input source amplitude which gives an undistorted output is
max(vs(p) ) = 1.28/8.36 = 153.1 mV.
If the input source amplitude exceeds this value, we will observe distortion at the output.
i. Forvs = 100 sin (ωt) mV, we are going to observe an undistorted sinusoidal output with an
amplitude of 0.836 V around VCBQ = 6.74 V as shown in Figure 10.34 below.
Figure 10.34: AC-DC load-lines for Example 10.1with input vs = 100 sin (ωt) mV.
199
ii. For vs = 900 sin (ωt) mV, we are going to observe a distorted output as shown in Figure 10.35
below.
Figure 10.35: AC-DC load-lines for Example 10.1with input vs = 900 sin (ωt) mV.
200
Chapter 11
FET Small-Signal Analysis
11.0.1 FET SSAC Analysis Steps
1. Draw the SSAC equivalent circuit
a) Draw the AC equivalent circuit (signal frequency is innity, i.e., f = ∞)

i. Capacitors are short circuit, i.e., XC → 0.
ii. Kill the DC power sources (i.e., AC value of DC sources is zero).
b) Replace FET with its small-signal equivalent model.
2. Calculate the three amplier parameters: Ri , Ro and Av

vi
a) Calculate no-load input resistance, Ri = ii .
RL =∞
b) Calculate output resistance, Ro .

vo
c) Calculate no-load voltage gain, Av = vi
.
RL =∞
11.1 FET Small-Signal Model

Small-signal equivalent model for a FET transistor is provided in Figure 11.1 below. This model
and its analysis is the same for all FET types, i.e., JFET, DMOSFET, EMOSFET, n-channel and
p-channel.
201
Figure 11.1: FET small-signal equivalent circuit.
Here,

∂ID
• gm = gf s = yf s = is the forward transfer conductance,
∂VGS Q-point

1 1 ∂VDS
• rds = = = is the output resistance.
gos yos ∂ID Q-point
Forward transfer conductance gm is mostly called as the transconductance parameter.

When rds 6= ∞, we can also use the voltage-controlled voltage source model (via Norton-to-Thévenin
transformation, a.k.a source transformation) as shown in Figure 11.2 below. We mostly use this model
for the common-gate and unbypassed self-bias congurations.
Figure 11.2: FET small-signal equivalent circuit with the voltage-controlled voltage source.
Here µ = gm rds is the forward transfer-voltage gain.
• Typical values of gm run from 1 mS to 5 mS,
• Typical values of rds run from 20 kΩ to 100 kΩ,
• Consequently, typical values of µ run from 20 to 500.
202
11.1.0.1 Transconductance Parameter (gm )
Transconductance parameter gm is given by

∂ID ∼ ∆ID
gm = = (11.1.1)
∂VGS Q-point ∆VGS Q-point
In other words, gm is the slope of the characteristics at the point of operation as shown in Figure 11.3
below.
Figure 11.3: Graphical denition of the transconductance gm .

2
VGS
• Let us derive gm for the JFET equation, ID = IDSS 1 − VP

∂ID 2IDSS VGS
gm = = 1−
∂VGS Q-point |VP | VP Q-point

2IDSS VGSQ
= 1− (11.1.2)
|VP | VP
r 2
2IDSS IDQ VGSQ
= . . . IDQ = IDSS 1 −
|VP | IDSS VP
r
IDQ 2IDSS
= gm0 . . . gm0 = (11.1.3)
IDSS |VP |
2
• Let us derive gm for the MOSFET equation, ID = k VGS − VGS(T h)

∂ID
gm = = 2k V GS − VGS(T h)

Q-point
∂VGS Q-point

= 2k VGSQ − VGS(T h) (11.1.4)
√ p 2
= 2 k IDQ . . . IDQ = k VGS − VGS(T h) (11.1.5)
203
11.1.0.2 Phase Relationship
The phase relationship between input and output depends on the amplier conguration circuit as
listed below.
• Common-Source: 180 degrees
• Common-Gate: 0 degrees
• Common-Drain: 0 degrees (Source-Follower)
11.2 Common-Source Fixed-Bias Conguration

Common-source xed-bias conguration is given in Figure 11.4 below
Figure 11.4: Common-source xed-bias conguration.
Figure 11.5: Small-signal equivalent circuit of the xed-bias circuit in Figure 11.4.
204

vi
Ri = = RG (11.2.6)
ii RL =∞
11.2.2 Voltage Gain


vo vo gm vgs vgs
Av = =
vi RL =∞ gm vgs vgs vi
= (−RD ||rds ) (gm ) (1)
= −gm (RD ||rds )

vo
Av = = −gm (RD ||rds ) (11.2.7)
vi RL =∞
• If rds ≥ 10RD , voltage gain Av reduces to
Av = −gm RD (11.2.8)
io vo /RD Ri vo
Ai = = =
ii vi /Ri RD vi
Ri
= Av (11.2.9)
RD
• If rds ≥ 10RD , current gain Ai reduces to
Ai = −gm RG (11.2.10)
205
circuit in Figure 11.6 above. Note that in the circuit vgs = 0, so gm vgs = 0 as well.

vtest
Ro = = RD ||rds (11.2.11)
• If rds ≥ 10RD , then Ro simplies to Ro = RD .
11.3 Common-Source Self-Bias Conguration

Common-source self-bias conguration is given in Figure 11.7 below
Figure 11.7: Common-source self-bias conguration.
Figure 11.8: Small-signal equivalent circuit of the self-bias circuit in Figure 11.7.
206

vi
Ri = = RG (11.3.12)
ii RL =∞
11.3.2 Voltage Gain


vo vo gm vgs vgs
Av = =
= (−RD ||rds ) (gm ) (1)
= −gm (RD ||rds )

vo
Av = = −gm (RD ||rds ) (11.3.13)
vi RL =∞
• If rds ≥ 10RD , no-load voltage gain Av reduces to
Av = −gm RD (11.3.14)
io vo /RD Ri vo
Ai = = =
ii vi /Ri RD vi
Ri
= Av (11.3.15)
RD
Ai = −gm RG (11.3.16)
207

vtest
Ro = = RD ||rds (11.3.17)
11.4 Common-Source Voltage-Divider Bias Conguration

Common-source voltage-divider bias conguration is given in Figure 11.10 below
Figure 11.10: Common-source voltage-divider bias conguration.
Figure 11.11: Small-signal equivalent circuit of the voltage-divider bias circuit in Figure 11.10.
208

vi
Ri = = R1 ||R2 (11.4.18)
ii RL =∞
11.4.2 Voltage Gain


vo vo gm vgs vgs
Av = =
= (−RD ||rds ) (gm ) (1)
= −gm (RD ||rds )

vo
Av = = −gm (RD ||rds ) (11.4.19)
vi RL =∞
• If rds ≥ 10RD , no-load voltage gain Av reduces to
Av = −gm RD (11.4.20)
io vo /RD Ri vo
Ai = = =
ii vi /Ri RD vi
Ri
= Av (11.4.21)
RD
Ai = −gm (R1 ||R2 ) (11.4.22)
209

vtest
Ro = = RD ||rds (11.4.23)
11.5 Common-Source Unbypassed Self-Bias Conguration

Common-source unbypassed self-bias (unbypassed RS ) conguration is given in Figure 11.13
below
Figure 11.13: Common-source unbypassed self-bias conguration.
Figure 11.14: Small-signal equivalent circuit of the unbypassed self-bias circuit in Figure 11.13.
210
• When RS is not bypassed, we normally use the voltage-controlled voltage source model in the
small-signal equivalent circuit as shown in Figure 11.14 above.


vi
Ri = = RG (11.5.24)
ii RL =∞
11.5.2 Voltage Gain


vo vo id vgs
Av = =
vi RL =∞ id vgs vi

µ vgs µvgs
= (−RD ) . . . id =
RS + RD + rds vgs + id RS RS + RD + rds
!
µ 1
= (−RD ) µRS
RS + RD + rds 1 + RS +R D +rds
µRD
=− . . . µ = gm rds
(µ + 1) RS + RD + rds
gm RD
=−
1 + gm RS + RSr+R
ds
D

vo gm RD
Av = =− (11.5.25)
vi RL =∞ RS + RD
1 + gm R S +
rds
• If rds ≥ 10 (RD + RS ), no-load voltage gain Av reduces to
gm RD
Av = − (11.5.26)
1 + gm RS
• If rds ≥ 10 (RD + RS ) and gm RS 1, no-load voltage gain Av reduces to
RD
Av ≈ − (11.5.27)
RS
io vo /RD Ri vo
Ai = = =
ii vi /Ri RD vi
Ri
= Av (11.5.28)
RD
211

vtest vtest
Ro = = vtest . . . itest = iRD + id
itest vs =0,RL =vtest RD
+ id
vtest −vgs
= . . . vs = −vgs , id =
RD
− vRgsS
vtest
RS
vtest vtest
= vtest vtest . . . vgs = −
RD
+ (µ+1)R S +rds
(µ + 1) + rds /RS
= RD || [(µ + 1) RS + rds ] . . . µ = gm rds
= RD || [(gm RS + 1) rds + RS ]
∼
= RD
As a result, Ro is given by

vtest ∼
Ro = = RD (11.5.29)
11.6 Source-Follower Conguration

Source-follower (common-drain) conguration is given in Figure 11.16 below
212
Figure 11.16: Source-follower conguration.
Figure 11.17: Small-signal equivalent circuit of the source-follower circuit in Figure 11.16.


vi
Ri = = RG (11.6.30)
ii RL =∞
11.6.2 Voltage Gain

Av is given by
No-load voltage gain

vo vo vgs
Av = =
vi RL =∞ vgs vi

1
= [gm (RS ||rds )] . . . vi = vgs + vo
1 + gm (RS ||rds )
gm (RS ||rds )
=
1 + gm (RS ||rds )
∼
=1
213

vo gm (RS ||rds ) ∼
Av = = =1 (11.6.31)
vi RL =∞ 1 + gm (RS ||rds )
• For the circuit in Figure 11.17, we can obtain the current-gain Ai as follows
io vo /RS Ri vo
Ai = = =
ii vi /Ri RS vi
Ri
= Av (11.6.32)
RS

vtest vtest
Ro = = vtest . . . itest = iRS ||rds − gm vgs
itest vs =0,RL =vtest − gm vgs
RS ||rds
vtest
= vtest . . . vtest = −vgs
RS ||rds
+ gm vtest
vtest
= vtest vtest
RS ||rds
+ 1/g m
1
= RS ||rds ||
gm
As a result, Ro is given by

vtest 1
Ro = = RS ||rds || (11.6.33)
gm
• If (RS ||rds ) ≥ 10/gm , output resistance Ro reduces to
1
Ro ∼
= (11.6.34)
gm
214
11.7 Common-Source Drain Feedback Conguration
Common-source drain feedback bias conguration is given in Figure 11.19 below
Figure 11.19: Common-source drain feedback bias conguration.
Figure 11.20: Small-signal equivalent circuit of the drain feedback bias circuit in Figure 11.19.


vi vgs
Ri = = . . . vi = vgs
ii RL =∞ gm vgs + vo / (RD ||rds )
RF + RD ||rds (1 − gm RF ) (RD ||rds ) vgs
= . . . vo =
1 + gm (RD ||rds ) RF + RD ||rds
∼ RF
= . . . RF RD ||rds
1 + gm (RD ||rds )
215

vo ∼ RF
Ri = = (11.7.35)
vi RL =∞ 1 + gm (RD ||rds )
11.7.2 Voltage Gain


vo (1 − gm RF ) (RD ||rds )
Av = = . . . vi = vgs
vi RL =∞ RF + RD ||rds
∼
= −gm (RD ||rds ||RF ) . . . gm RF 1

vo ∼
Av = = −gm (RD ||rds ||RF ) (11.7.36)
vi RL =∞
io vo /RD Ri vo
Ai = = =
ii vi /Ri RD vi
Ri
= Av (11.7.37)
RD

vtest
Ro = = RD ||rds ||RF (11.7.38)
• If a voltage source with source resistance Rs is connected to the input, replace RF with
[(RF + Rs ) / (1 + gm Rs )] in Ro calculations.
216
11.8 Common-Gate Conguration
Common-gate conguration is given in Figure 11.22 below
Figure 11.22: Common-gate conguration.
Figure 11.23: Small-signal equivalent circuit of the common-gate circuit in Figure 11.22.


vi vi
Ri = = . . . vi = −vgs
ii RL =∞ vi /RS − id
vi (µ + 1) vgs
= . . . id =
vi /RS + vi / RD +rds RD + rds
µ+1
RD + rds
= RS || . . . µ = gm rds
1 + gm rds
∼ 1
= RS || . . . rds ≥ 10RD and gm rds 1
gm

vo ∼ 1
Ri = = RS || (11.8.39)
vi RL =∞ gm
217
11.8.2 Voltage Gain

vo −id RD
Av = = . . . vi = −vgs
vi RL =∞ −vgs
(µ + 1) RD (µ + 1) vgs
= . . . id =
RD + rds RD + rds
(gm rds + 1) RD
= . . . µ = gm rds
RD + rds
∼
= gm RD . . . rds ≥ 10RD and gm rds 1
(11.8.40)

vo ∼
Av = = gm RD (11.8.41)
vi RL =∞
io vo /RD Ri vo
Ai = = =
ii vi /Ri RD vi
Ri
= Av (11.8.42)
RD
• If rds ≥ 10RD and gm rds 1, current-gain Ai reduces to

1
Ai = gm RS || ≈1 (11.8.43)
gm
218

vtest
Ro = = RD ||rds (11.8.44)
• If a voltage source with source resistance Rs is connected to the input, replace rds with
([1 + gm (Rs ||RG )] rds + Rs ||RG ) in Ro calculations. We can say that Ro ≈ RD in most cases.
219
Chapter 12
Frequency Response of Ampliers
12.1 First-Order RC Filters

12.1.1 First-Order Highpass RC Filter
Consider the rst order highpass (HP) RC circuit given in Figure 12.1 below, let us calculate the
voltage gain A = vo /vi . Note that, as the impedance of the capacitor changes with the frequency the
gain will change with the frequency.
Figure 12.1: First order highpass RC lter.
vo R 1
A(ω) = = . . . ZC = −jXC = −j
vi R + ZC ωC
1
= . . . ω = 2πf
ZC
1+
R
1
= (12.1.1)
1
1−j
ωCR
A(ω) is called frequency response of the lter circuit above. As the frequency response A(ω) is complex,
it has a magnitude and phase, i.e.,
A(ω) = |A(ω)| ej∠A(ω) (12.1.2)
220
Thus, A(ω) is called the frequency response, |A(ω)| is called the magnitude response and ∠A(ω)
is called the phase response.
Given that we know the frequency response of the system. Then, for a sinusoidal input vi (t)
vi (t) = Vm cos (ω0 t) , (12.1.3)
we obtain the output signal vo (t) as
vo (t) = |A(ω0 )|Vm cos (ω0 t + ∠A(ω0 )) . (12.1.4)
So, the magnitude and phase of the output determined by the frequency response of the system.
For this highpass system given in (12.1.1), magnitude response |A(ω)| and phase response ∠A(ω) are
given by
1
|A(ω)| = r (12.1.5)
1
1+
ω R2 C 2
2

1
∠A(ω)| = arctan (12.1.6)
ωRC
Note that ω → ∞ ⇒ |A(ω)| → 1 and ω → 0 ⇒ |A(ω)| → 0.
12.1.1.1 Cuto Frequency

The frequency where the output power drops to half (of the maximum output power) is called the
cuto frequency or corner frequency, ωc . Thus, at the cuto frequency, the output voltage gain
magnitude square will drop to half. As, in this case the maximum gain is one, i.e. max |A(ω)| = 1,
1 1
|A(ωc )|2 = . . . i.e., |A(ωc )| = √
2 2
1 1
=
1 2
1+
ωc2 R2 C 2
1 1
ωc = . . . fc =
RC 2πRC
Thus, cuto frequency ωc for the rst order highpass RC lter is given by
1
ωc = (12.1.7)
RC
221
Consequently, frequency response of the highpass lter A(ω) is given by
1
A(ω) = ωc (12.1.8)
1−j
ω
1
|A(ω)| = r (12.1.9)
ω2
1 + c2
ω
ωc
∠A(ω)| = arctan (12.1.10)
ω
12.1.1.2 Bode Plot

Amplitude response in (12.1.9) above has two asymptotes as shown below
ωc2
1 ⇒ |A(ω)| = 1 (12.1.11)
ω2
ωc2 ω ωc
1 ⇒ |A(ω)| = . . . |A(ωc )| = =1 (12.1.12)
ω2 ωc ωc
These two lines intersect at ω = ωc as shown in Figure 12.2 below.
Figure 12.2: Asymptotic Bode plot (scalar) of the rst order highpass RC lter in Figure 12.1.
12.1.1.3 Decibels (dB)

The decibel (dB) is a logarithmic unit used to express the ratio of two values of a physical quantity,
often power or intensity. One of these values is often a standard reference value, in which case the
decibel is used to express the level of the other value relative to this reference. The term decibel has
222
its origin in the fact that power and audio levels are related on a logarithmic basis, i.e.,
Po
GdB = 10 log10 (12.1.13)
P
i
Vo V2
= 20 log10 ...P = (12.1.14)
Vi R
Thus, magnitude response in decibels is given by
|A(ω)|dB = 20 log10 |A(ω)| (12.1.15)
Consequently, the normalized magnitude response (i.e., maximum value is 1) in decibels is given
by
|A(ω)|
|Ã(ω)|dB = 20 log10 (12.1.16)
max |A(ω)|
The two asymptotes of the amplitude response in (12.1.9) are expressed in dB as follows
ωc2
1 ⇒ 20 log10 1 = 0 dB (12.1.17)
ω2
ωc2 ω
1 ⇒ |A(ω)| = 20 log 10 = 20 log10 ω − 20 log10 ωc (12.1.18)
ω2 ωc
Figure 12.3: Asymptotic Bode plot (dB) of the rst order highpass RC lter in Figure 12.1.
As we see from the asymptotic magnitude response in Figure 12.3 above, a highpass lter attenuates
the low frequencies and keeps the high frequencies intact.
ω
Let us consider the second asymptote (i.e., 20 log10 ωc
) and for a given ω = ω1 consider the two cases
where ω2 = ω1 /2 and ω3 = ω1 /10, then
ω2 ω1 ω1
20 log10 = 20 log10 − 20 log10 2 ∼
= 20 log10 − 6 dB . . . one octave (12.1.19)
ωc ωc ωc
ω3 ω1 ω1
20 log10 = 20 log10 − 20 log10 10 = 20 log10 − 20 dB . . . one decade (12.1.20)
ωc ωc ωc
223
A change in frequency by a factor of two is equivalent to one octave. Similarly, a change in frequency
by a factor of ten is equivalent to one decade.
ω
Thus, the slope of the second asymptote (i.e., 20 log10 ωc
) is 6 dB/octave or 20 dB/decade.
So, actual magnitude of the normalized magnitude response at the

√ cuto frequency ωc is |Ã(ωc )| =
1/ 2. Thus, in dBs
1
20 log10 |Ã(ωc )| = 20 log10 √ ∼= −3 dB (12.1.21)
2
Thus, cuto frequency is always 3 dB below the maximum gain.
As a result if we plot (12.1.9) and (12.1.10) against ω , we obtain the magnitude and phase responses
of the rst order highpass RC lter as shown in Figure 12.4 below.
Figure 12.4: Magnitude (top) and phase (bottom) responses of the rst order highpass RC lter in
Figure 12.1.
12.1.2 First-Order Lowpass RC Filter

Consider the rst order lowpass (LP) RC circuit given in Figure 12.5 below, let us calculate the voltage
gain A = vo /vi . Note that, as the impedance of the capacitor changes with the frequency the gain
224
will change with the frequency.
Figure 12.5: First order lowpass RC lter.
vo ZC 1
A(ω) = = . . . ZC = −jXC =
vi ZC + R jωC
1
= . . . ω = 2πf
R
1+
ZC
1
= (12.1.22)
1 + jωCR
Thus, magnitude response |A(ω)| and phase response ∠A(ω) are given as
1
|A(ω)| = √ (12.1.23)
1 + ω 2 R2 C 2
∠A(ω)| = − arctan (ωRC) (12.1.24)
Note that ω → ∞ ⇒ |A(ω)| → 0 and ω → 0 ⇒ |A(ω)| → 1.
12.1.2.1 Cuto Frequency

Cuto frequency ωc can be found as,
1 1
|A(ωc )|2 = . . . i.e., |A(ωc )| = √
2 2
1 1
2 2 2
=
1 + ωc R C 2
1 1
ωc = . . . fc =
RC 2πRC
Thus, cuto frequency ωc for the rst order lowpass RC lter is given by
1
ωc = (12.1.25)
RC
225
Consequently, frequency response of the lowpass lter A(ω) is given by
1
A(ω) = ω (12.1.26)
1+j
ωc
1
|A(ω)| = s (12.1.27)
ω2
1+ 2
ωc

ω
∠A(ω)| = − arctan (12.1.28)
ωc
12.1.2.2 Bode Plot

The two asymptotes of the amplitude response in (12.1.27) are expressed in dB as follows
ω2
1 ⇒ 20 log10 1 = 0 dB (12.1.29)
ωc2
ω2 ωc
2
1 ⇒ |A(ω)| = 20 log10 = 20 log10 ωc − 20 log10 ω (12.1.30)
ωc ω
Figure 12.6: Asymptotic Bode plot (dB) of the rst order lowpass RC lter in Figure 12.5.
As we see from the asymptotic magnitude response in Figure 12.6 above, a lowpass lter keeps the
low frequencies intact and attenuates the high frequencies.
ωc
Let us consider the second asymptote (i.e., 20 log10 ω
) and for a given ω = ω1 consider the two cases
where ω2 = 2ω1 andω3 = 10ω1 , then
ωc ωc ωc
20 log10 = 20 log10 − 20 log10 2 ∼
= 20 log10 − 6 dB . . . one octave (12.1.31)
ω2 ω1 ω1
ωc ωc ωc
20 log10 = 20 log10 − 20 log10 10 = 20 log10 − 20 dB . . . one decade (12.1.32)
ω3 ω1 ω1
226
ω
Thus, the slope of the second asymptote (i.e., 20 log10 ωc
) is 6 dB/octave or 20 dB/decade.
So, actual magnitude of the normalized magnitude response at the

√ cuto frequency ωc is |Ã(ωc )| =
1/ 2. Thus, in dBs
1
20 log10 |Ã(ωc )| = 20 log10 √ ∼= −3 dB (12.1.33)
2
Thus, cuto frequency is always 3 dB below the maximum gain.
As a result if we plot (12.1.27) and (12.1.28) against ω , we obtain the magnitude and phase responses
of the rst order lowpass RC lter as shown in Figure 12.7 below.
Figure 12.7: Magnitude (top) and phase (bottom) responses of the rst order lowpass RC lter in
Figure 12.5.
12.2 Typical Frequency Response

The magnitudes of the gain response curves of an RC-coupled amplier system are given in Figure 12.8
below. In the plot low-, high-, and mid-frequency regions are dened. This magnitude response shown
in Figure 12.8 below is the response of a bandpass amplier. It amplies a band of frequencies
227
(namely midband, or mid-frequency band) and attenuates the low or high frequencies. Note that,
the low-frequency part of the amplier looks like a highpass amplier and the high-frequency part of
the amplier looks like a lowpass amplier.Thus, we can obtain a bandpass amplier by combining a
highpass and a lowpass amplier.
Figure 12.8: Typical magnitude response of a transistor amplier.
The purpose of frequency analysis in this course is to determine the low-frequency cuto fL and
the high-frequency cuto fH of the amplier. Low-frequency cut-o fL is determined by the capacitors
in the circuit, i.e., C1 , C2 and C3 , and high-frequency cuto fH is determined by the internal device
capacitances, wiring capacitances or parasitic capacitances.
Typically, low-frequency capacitors C1 , C2 and C3 are in the microFarad (µF) range, and high-
frequency capacitances (wiring capacitances and parasitic capacitances) are in the picoFarad (pF)
range.
Consequently, low-frequency capacitors are short-circuit for high-frequency, and high-frequency capa-
citances are open-circuit for low-frequency. So, low-frequency response and high-frequency response
will be dealt with separately. The bandwidth (or passband, or midband) of the amplier is deter-
mined as,
Bandwidth (BW) = fH − fL (12.2.34)
Up to now, we have calculated the mid-frequency (midband) input resistance Ri = Zimid , voltage gain
Av = Avmid and output resistance input resistance Ro = Zomid , where we ignored the low-frequency and
high-frequency eects assuming the low-frequency capacitances were short-circuit and high-frequency
capacitances were open-circuit.
Scalar and decibel plot of the normalized magnitude response is shown in Figure 12.9 and Figure 12.10
below, respectively.
228
Figure 12.9: Normalized scalar plot of the magnitude response given in Figure 12.8.
Figure 12.10: Normalized decibel plot of the magnitude response given in Figure 12.8.
12.3 Low Frequency Response

12.3.1 BJT Ampliers
For the circuit shown in Figure 12.11 below, the capacitors C1 , C2 , and C3 will determine the low-
frequency response. Capacitors C1 and C2 at the input and output of the circuit are called the
coupling capacitors, and C3 is called the bypass capacitor. We will now examine the impact of each
independently in the order listed as rst order RC lters.
229
Figure 12.11: A common-emitter voltage-divider bias BJT circuit.
12.3.1.1 Eect of Coupling Capacitor C1

For the BJT circuit shown in Figure 12.11 above, capacitor C1 and the equivalent-resistance of Rs
and Ri (Req1 = Rs + Ri ) form a rst-order highpass lter structure given in Figure 12.1 with a cuto
frequency fL1 of
1
fL1 = (12.3.35)
2π (Rs + Ri ) C1
where Rs is the source (e.g., voltage source) resistance and Ri is the input resistance of the amplier,
value of which for this circuit is given by
Ri = R1 ||R2 ||hie .

For the BJT circuit shown in Figure 12.11 above, capacitor C2 and the equivalent-resistance of Ro
and RL (Req2 = Ro + RL ) form a rst-order highpass lter structure given in Figure 12.1 with a cuto
frequency fL2 of
1
fL2 = (12.3.36)
2π (Ro + RL ) C2
where RL is the load resistance and Ro is the output resistance of the amplier, value of which for
this circuit is given by
Ro = RC ||1/hoe .
230
12.3.1.3 Eect of Bypass Capacitor C3
For the BJT circuit shown in Figure 12.11 above, capacitor C3 and the equivalent Thévenin resistance
Req3 seen by C3 form a rst-order lowpass lter structure given in Figure 12.5 with a cuto frequency
fL3 of
1
fL3 = (12.3.37)
2πReq3 C3
where Req3 is the Thévenin resistance seen by C3 (i.e., like the output resistance of the emitter-follower),
Rs ||R1 ||R2 + hie

Req3 = RE || .
hf e + 1
12.3.1.4 Combined Eect of C1 , C2 and C3

Each cuto frequency fL1 , fL2 and fL3 adds an additional 6 dB/octave slope as shown in Figure 12.12
below. Overall cuto frequency fL is higher than the highest value of these three cuto frequencies,
i.e.,
fL ≥ max (fL1 , fL2 , fL3 ) (12.3.38)
When the three cut-o frequencies (or the highest cuto frequency) are a decade apart from each
other, than the overall cuto frequency is almost equal to the highest of these three frequencies as
depicted in Figure 12.12 below, i.e.,
fL ≈ max (fL1 , fL2 , fL3 ) (12.3.39)
231
Figure 12.12: Low-frequency plot for the circuit given in Figure 12.11.
As Req3 normally has the lowest resistance value, generally fL3 holds the highest value. Also as
generally Ri > Ro , mostly fL2 > fL1 . So, generally fL3 > fL2 > fL1 .
Even though these assumptions may not hold, we generally select the value of the capacitors C1 , C2
and C3 properly to have the cuto frequencies to be at least a decade apart, e.g., fL3 > 10fL2 > 10fL1 ,
in order to reduce the coupling eect of all three capacitors to the cuto frequency fL .
If the decade-apart condition do not hold, then the cuto frequency fL will move up towards the mid-
frequency range and has to be calculated from the overall third-order highpass system by considering
the eects of all three-capacitors.
12.3.2 FET Ampliers

For the circuit shown in Figure 12.13 below, the capacitors C1 , C2 , and C3 will determine the low-
frequency response. Capacitors C1 and C2 at the input and output of the circuit are called the
coupling capacitors, and C3 is called the bypass capacitor. We will now examine the impact of each
independently in the order listed as rst order RC lters.
232
Figure 12.13: A common-source self-bias JFET circuit.

For the JFET circuit shown in Figure 12.13 above, capacitor C1 and the equivalent-resistance of Rs
and Ri (Req1 = Rs + Ri ) form a rst-order highpass lter structure given in Figure 12.1 with a cuto
frequency fL1 of
1
fL1 = (12.3.40)
2π (Rs + Ri ) C1
where Rs is the source (e.g., voltage source) resistance and Ri is the input resistance of the amplier,
Ri = RG .

For the JFET circuit shown in Figure 12.13 above, capacitor C2 and the equivalent-resistance of Ro
and RL (Req2 = Ro + RL ) form a rst-order highpass lter structure given in Figure 12.1 with a cuto
frequency fL2 of
1
fL2 = (12.3.41)
2π (Ro + RL ) C2
where RL is the load resistance and Ro is the output resistance of the amplier, value of which for
this circuit is given by
Ro = RD ||rds .
233
12.3.2.3 Eect of Bypass Capacitor C3
For the JFET circuit shown in Figure 12.13 above, capacitor C3 and the equivalent Thévenin resistance
Req3 seen by C3 form a rst-order lowpass lter structure given in Figure 12.5 with a cuto frequency
fL3 of
1
fL3 = (12.3.42)
2πReq3 C3
where Req3 is the Thévenin resistance seen by C3 (i.e., like the output resistance of the source-follower),
1
Req3 = RS ||rds ||
gm
12.3.2.4 Combined Eect of C1 , C2 and C3

Each cuto frequency fL1 , fL2 and fL3 adds an additional 6 dB/octave slope as shown in Figure 12.14
below. Overall cuto frequency fL is higher than the highest value of these three cuto frequencies,
i.e.,
fL ≥ max (fL1 , fL2 , fL3 ) (12.3.43)
When the three cut-o frequencies (or the highest cuto frequency) are a decade apart from each
other, than the overall cuto frequency is almost equal to the highest of these three frequencies as
fL ≈ max (fL1 , fL2 , fL3 ) (12.3.44)
234
Figure 12.14: Low-frequency plot for the circuit given in Figure 12.13.
As Req3 has the lowest resistance value, fL3 holds the highest value. Also as Ri Ro , fL2 > fL1 . So,
almost always fL3 > fL2 > fL1 .
We generally select the value of the capacitors C1 , C2 and C3 properly to have the cuto frequencies
to be at least a decade apart, e.g., fL3 > 10fL2 > 10fL1 , in order to reduce the coupling eect of all
three capacitors to the cuto frequency fL .
12.4 Miller Eect

For inverting ampliers (phase shift of 180◦ between input and output, resulting in a negative
value for Av ), the input and output capacitance is increased by a capacitance level sensitive to the
interelectrode capacitance between the input and output terminals of the device and the gain of the
amplier. Thus, Miller eect only occurs in common-emitter and common-source ampliers.
Capacitance Cf between input and output will be represented by its equivalent Miller capacitance at
the input CMi and at the output CMo .
For noninverting ampliers such as the common-base and emitter-follower (or common-gate and
source-follower) congurations, the Miller eect capacitance is not a contributing concern for high-
frequency applications.
12.4.0.1 Miller Input Capacitance CM i
Consider the network shown in Figure 12.15 below, let us calculate the input impedance Zi = vi /ii
235
vi vi vi vi − vo
Zi = = . . . i1 = , if =
ii i1 + if Ri ZCf
vi 1
= . . . vo = Av vi , ZCf =
vi /Ri + vi −A
ZC
v vi
jωCf
f
ZCf ZCf
= Ri || . . . ZMi =
1 − Av 1 − Av
1
= ZMi ||Ri . . . ZMi = , CMi = (1 − Av ) Cf
jωCMi
Figure 12.15: Circuit employed in the derivation of an equation for the Miller input capacitance CMi ,
where Av < 0.
So, Miller input capacitance CMi is given by
CMi = (1 − Av ) Cf (12.4.45)
Thus, the feedback capacitance Cf appears as a higher capacitance at the input, increased by a factor
of (1 − Av ). Note that, Av < 0.
12.4.0.2 Miller Output Capacitance CM o
Consider the network shown in Figure 12.16 below, let us calculate the output impedance Zo = vo /io
236
vo vo vo vo − vi
Zo = = . . . i1 = , if =
io i1 + if Ro ZCf
vo 1
= vo −vo /Av
. . . vo = Av vi , ZCf =
vo /Ro + jωCf
ZCf
ZCf ZCf
= Ro || . . . ZMo =
1 − A1v 1 − A1v

1 1
= Ro ||ZMo . . . ZMo = , CMo = 1− Cf
jωCMo Av
Figure 12.16: Circuit employed in the derivation of an equation for the Miller output capacitance
CMo , where Av < 0.
So, Miller output capacitance CMo is given by

1
CMo = 1− Cf ∼
= Cf (12.4.46)
Av
Thus, the feedback capacitance Cf appears as a similar capacitance at the output. Note that, Av < 0
and |Av | 1.
12.4.0.3 Miller Representation

Miller input and output capacitances for the feedback capacitance (Cf ) remove the feedback and
simplify the representation as shown in Figure 12.17 below.
237
Figure 12.17: Miller representation of the feedback capacitance in negative gain ampliers.
12.5 High Frequency Response

12.5.1 BJT Ampliers
For the high-frequency circuit shown in Figure 12.18 below, there are two factors that dene the −3 dB
cuto point: the network capacitance (parasitic (Cbe , Cbc , Cce ) and wiring (CWi , CWo ) capacitance) and
the frequency dependence of hf e (or β ). Note that, low-frequency capacitors C1 , C2 and C3 are short
circuit and have no eect in high-frequency analysis.
Figure 12.18: A common-emitter voltage-divider bias BJT circuit with the capacitors that aect the
high-frequency response.
12.5.1.1 Input Circuit Cuto Frequency fH 1
For the BJT circuit shown in Figure 12.18 above, equivalent total input capacitance Ceqi and the
Thévenin equivalent input resistance of Reqi = Rs ||Ri form a rst-order lowpass lter structure given
238
in Figure 12.5 with a cuto frequency fH1 of
1
fH 1 = (12.5.47)
2π (Rs ||Ri ) Ceqi
with
Ceqi = CWi + CMi + Cbe (12.5.48)
where Rs is the source (e.g., voltage source) resistance, Ri is the input resistance of the amplier
and CMi is the Miller input capacitance given by
Ri = R1 ||R2 ||hie , (12.5.49)
CMi = (1 − AV ) Cbc . (12.5.50)
12.5.1.2 Output Circuit Cuto Frequency fH 2
For the BJT circuit shown in Figure 12.18 above, equivalent total output capacitance Ceqo and the
Thévenin equivalent output resistance of Reqo = Ro ||RL form a rst-order lowpass lter structure
given in Figure 12.5 with a cuto frequency fH2 of
1
fH2 = (12.5.51)
2π (Ro ||RL ) Ceqo
with
Ceqo = Cce + CMo + CWo (12.5.52)
where RL is the load resistance, Ro is the output resistance of the amplier and CM o is the Miller
output capacitance given by
Ro = RC ||1/hoe , (12.5.53)
CMo = (1 − 1/AV ) Cbc ∼

= Cbc . (12.5.54)
12.5.1.3 hf e (or β ) Variation Cuto Frequency fβ

The hf e parameter (or β) of a transistor varies with frequency as shown in Figure 12.19 below and
given by
hf emid
hf e = (12.5.55)
1 + j ffβ
where fβ is given by
fT ∼ 1 1
fβ = = . . . fT ∼
= (12.5.56)
hf emid 2π hie (Cbe + Cbc ) 2π re (Cbe + Cbc )
239
Figure 12.19: hf e and hf b versus frequency in the high-frequency region.
12.5.1.4 Combined Eect of fH , fH and fβ 1 2
Each cuto frequency fH1 , fH2 and fβ adds an additional 6 dB/octave slope as shown in Figure 12.20
below. Overall cuto frequency fH is lower than the lowest value of these three cuto frequencies,
i.e.,
fH ≤ min (fH1 , fH2 , fβ ) (12.5.57)
When the three cut-o frequencies (or the lowest cuto frequency) are a decade apart from each other,
than the overall higher cuto frequency fH is almost equal to the lowest of these three frequencies as
fH ≈ min (fH1 , fH2 , fβ ) (12.5.58)
240
Figure 12.20: Normalized magnitude response (normalized gain vs. frequency) for the circuit given in
Figure 12.18.
As Miller input capacitance CMi has the highest capacitance, almost always fH1 holds the lowest value.
Also not always, but generally fβ < fH2 .
12.5.2 FET Ampliers

For the high-frequency circuit shown in Figure 12.21 below, there are two factors that dene the −3 dB
cuto point: the network capacitance (parasitic (Cgs , Cgd , Cds ) and wiring (CWi , CWo ) capacitance).
Note that, low-frequency capacitors C1 , C2 and C3 are short circuit and have no eect in high-
frequency analysis.
241
Figure 12.21: A common-source self-bias JFET circuit with the capacitors that aect the high-
frequency response.
12.5.2.1 Input Circuit Cuto Frequency fH 1
For the JFET circuit shown in Figure 12.21 above, equivalent total input capacitance Ceqi and the
Thévenin equivalent input resistance of Reqi = Rs ||Ri form a rst-order lowpass lter structure given
in Figure 12.5 with a cuto frequency fH1 of
1
fH 1 = (12.5.59)
2π (Rs ||Ri ) Ceqi
with
Ceqi = CWi + CMi + Cgs (12.5.60)
where Rs is the source (e.g., voltage source) resistance, Ri is the input resistance of the amplier
and CMi is the Miller input capacitance given by
Ri = RG , (12.5.61)
CMi = (1 − AV ) Cgd . (12.5.62)
12.5.2.2 Output Circuit Cuto Frequency fH 2
For the JFET circuit shown in Figure 12.21 above, equivalent total output capacitance Ceqo and the
Thévenin equivalent output resistance of Reqo = Ro ||RL form a rst-order lowpass lter structure
given in Figure 12.5 with a cuto frequency fH2 of
1
fH2 = (12.5.63)
2π (Ro ||RL ) Ceqo
with
242
Ceqo = Cds + CMo + CWo (12.5.64)
where RL is the load resistance, Ro is the output resistance of the amplier and CM o is the Miller
output capacitance given by
Ro = RD ||rds , (12.5.65)
CMo = (1 − 1/AV ) Cgd ∼

= Cgd . (12.5.66)
12.5.2.3 Combined Eect of fH and fH 1 2
Each cuto frequency fH 1 and fH 2 adds an additional 6 dB/octave slope. Overall cuto frequency fH
is lower than the lowest value of these three cuto frequencies, i.e.,
fH ≤ min (fH1 , fH2 ) (12.5.67)
When the two cut-o frequencies are a decade apart from each other, than the overall higher cuto
frequency fH is almost equal to the lowest of the two frequencies, i.e.,
fH ≈ min (fH1 , fH2 ) (12.5.68)
As Miller input capacitance CMi has the highest capacitance, almost always fH1 > fH2 .
12.6 Gain-Bandwidth Product

There is a Figure of Merit applied to ampliers called the Gain-Bandwidth Product (GBP)
that is commonly used to initiate the design process of an amplier. It provides important information
about the relationship between the gain of the amplier and the expected operating frequency range.
The gain-bandwidth product of an amplier is constant. Thus, gain and bandwidth are inversely
proportional, i.e., when we increase the gain, the bandwidth decreases. As a result, we can express
the gain-bandwidth product (GBP) as follows
GBP = |Avmid | ×BW . . . BW = fH − fL (12.6.69)

∼
= |Avmid | ×fH . . . fH fL (12.6.70)
For example, fT is the gain-bandwidth product for fβ as it is the cuto frequency for hf e = 1, i.e.,
fα ∼
= fT .
243
Chapter 13
Multistage (Cascaded) Ampliers
13.1 Cascaded Systems

In cascaded (or multistage) systems output of one amplier is connected to the input to the next
amplier as shown in Figure 13.1 below.
Figure 13.1: A cascaded (or multistage) system.
We would like to represent the overall system as a voltage-gain amplier as shown in Figure 13.2
below.
Figure 13.2: Overall representation of the system as a single voltage-gain amplier.
vi vL(open-circuit)
So, the input resistance Ri = ii
, the output resistance Ro = iL(short-circuit)
and the no-load voltage gain
vo(no-load)
Av = vi
of the whole cascaded system is given by
Ri = Ri1 (13.1.1)
Ro = Ron (13.1.2)
Ri2 Rik Rin

Av = Av1 × × Av2 × · · · × × Avk × · · · × × Avn (13.1.3)
Ro1 + Ri2 Rok−1 + Rik Ron−1 + Rin
244
where Rik , Rok and Avk are the input resistance, output resistance and no-load gain of the k -th stage,
respectively, 1 ≤ k ≤ n and n is the maximum number of stages.
NOTE: Thus, the input resistance of the current stage acts as a load for the previous stage, or the
output resistance of the previous stage acts as a source resistance for the current stage.
Consequently, we can represent the overall no-load voltage-gain Av in terms of the load-included
voltage gains of each stage except the last stage

vo
Av = = AV1 × AV2 × · · · AVk · · · × Avn (13.1.4)
vi RL =∞
where AVk is the load-included voltage gain of k -th stage given by

Rik+1
AVk = Avk . (13.1.5)
Rok + Rik+1
Similarly, we can represent the overall no-load voltage-gain Av in terms of the source-included voltage
gains of each stage except the rst stage

vo
Av = = Av1 × Avs2 × · · · Avsk · · · × Avsn (13.1.6)
vi RL =∞
where Avsk is the source-included voltage gain of k -th stage given by

Rik
Avsk = Avk . (13.1.7)
Rok−1 + Rik
Example 13.1: For the gure below, nd the input resistance Ri , output resistance Ro and
the overall voltage gain AVs = vo /vs of the whole system.
Figure 13.3: A two-stage cascaded system for Example 13.1.
Solution: The input resistance Ri , output resistance Ro and the total voltage gain AVs of the
overall system are given as follows
Ri = Ri1 = 10 kΩ, (13.1.8)
Ro = Ro2 = 5.1 kΩ, (13.1.9)

Ri2 26
Av = Av1 Av2 = (1) (240) ∼
= 164.21, (13.1.10)
Ro1 + Ri2 12 + 26

Ri RL 10k 8.2k ∼
AVs = Av = (164.21) = 92. (13.1.11)
Rs + Ri Ro + RL 1k + 10k 5.1k + 8.2k
245
Homework 13.1: Calculate the overall voltage gain AVs by removing the rst stagein Figure 13.3,
i.e., connecting Rs directly to the second stage. Thus, explain the purpose of the rst stage.
13.2 AC-Coupled Multistage Ampliers

In AC-coupled multistage ampliers, the DC bias circuits are isolated from each other by the cou-
pling capacitors at the input and output of each stage.
Thus,
• The DC calculations are independent of the cascading.

• The AC calculations for gain and impedance are interdependent.
the no-load voltage gain Av = vo /vi of the whole system.
Figure 13.4: An AC-coupled two-stage FET amplier for Example 13.2.
Solution: The input resistance Ri , output resistance Ro and the no-load voltage gain Av of the
Ri = RG1 (13.2.12)
Ro = RD2 ||rds2 (13.2.13)
Av = [−gm2 (RD2 ||rds2 )] [−gm1 (RD1 ||rds1 ||Ri2 )] (13.2.14)
= gm2 gm1 (RD2 ||rds2 ) (RD1 ||rds1 ||RG2 ) . (13.2.15)
246
the no-load voltage gain Av = vo /vi of the whole system.
Figure 13.5: An AC-coupled two-stage BJT amplier for Example 13.3.
Solution: The input resistance Ri , output resistance Ro and the no-load voltage gain Av of the
Ri = R1 ||R2 ||hie1 (13.2.16)
Ro = RC2 ||1/hoe2 (13.2.17)

hf e2 (RC2 ||1/hoe2 ) hf e1 (RC1 ||1/hoe1 ||Ri2 )
Av = − − (13.2.18)
hie2 hie1
hf e2 hf e1 (RC2 ||1/hoe2 ) (RC1 ||1/hoe1 ||R3 ||R4 ||hie2 )
= . (13.2.19)
hie2 hie1
• We can also represent these results in the re model as follows
Ri = R1 ||R2 ||β1 re1 (13.2.20)
Ro = RC2 ||ro2 (13.2.21)

−RC2 ||ro2 RC1 ||ro1 ||Ri2
Av = − (13.2.22)
re2 re1
(RC2 ||ro2 ) (RC1 ||ro1 ||R3 ||R4 ||β2 re2 )
= . (13.2.23)
re2 re1
247
Example 13.4: For the gure below,
a) Draw AC and DC load lines for both transistors.
b) Calculate the overall voltage gain AVs = vo /vs .

c) Find vs(max) which produces maximum undistorted output voltage.
Figure 13.6: An AC-coupled two-stage BJT amplier for Example 13.4.
Homework 13.2: Solve the question given in Example 13.4.
13.3 DC-Coupled Multistage Ampliers

In DC-coupled multistage ampliers, the DC bias circuits are not isolated from each other.
Thus,
• The DC calculations are not independent of the cascading.

• The AC calculations for gain and impedance are interdependent.
DC-coupled multistage ampliers are used either to amplify very low frequency signals or to amplify
DC signals.
248

Figure 13.7: A DC-coupled two-stage BJT amplier for Example 13.5.
Solution: a) Let us rst start with DC analysis and apply the Thévenin theorem at the base
od the rst transistor
30k
VBB1 = 30 = 10 V (13.3.24)
30k + 60k
RBB1 = 30k||60k = 20 kΩ (13.3.25)
Note that, IE1 = IRE 1 + IB2 ∼

= IRE 1 assuming IE2 ∼ IE1 . So, we can nd IRE 1 as follows
VBB 1 − VBE 1 (ON ) 10 − 0.6 ∼

IRE 1 ∼
= = = 4.82 mA (13.3.26)
RE1 + RBB 1 / (β + 1) 1k + 20k/21
Consequently, ICQ1 ∼
= IRE 1 = 4.82 mA and RDC 1 ∼
= RE1 = 1 kΩ. Also, as VB2 = VE2 = 4.82 V,
we can nd IE2 as
VE1 − VBE 2 (ON ) 4.82 − 0.6 ∼
IE2 = = = 4.22 mA (13.3.27)
RE2 1k
Thus,IE2 ∼ IE1 and our assumption holds. Here assuming α = 20/21 ≈ 1, we obtain RDC 2 ∼
=
RC + RE2 = 3 kΩ.
249
As Rac1 ∼
= RDC 1 = 1 kΩ and Rac2 = RDC 2 = 3 kΩ, AC and DC load-lines coincide for both
transistors, i.e.,
vCE1 = VCC − iC1 Rac1 . . . AC-DC load lines are the same (13.3.28)
vCE2 = VCC − iC2 Rac2 . . . AC-DC load lines are the same (13.3.29)
Consequently, AC (and DC) load-line for the rst transistor is shown in Figure 13.8 below
Figure 13.8: AC-DC load-line for the rst transistor in Example 13.5.
We can see that maximum undistorted swing for the rst transistor is given by
vCE1(max) = min (VCEQ1 , ICQ1 Rac1 ) = min (25.18, 4.82) = 4.82 V. (13.3.30)
Similarly, AC (and DC) load-line for the second transistor is shown in Figure 13.9 below
250
Figure 13.9: AC-DC load-line for the second transistor in Example 13.5.
We can see that maximum undistorted swing for the second transistor is given by
vCE2(max) = min (VCEQ2 , ICQ2 Rac2 ) = min (17.34, 12.66) = 12.66 V. (13.3.31)
b) Let us rst nd hie1 , hie2 and Ri1

γ 26m
ie1 = hf e1 = 20 = (20)(5.39) ∼= 108 Ω (13.3.32)
ICQ1 4.82m
γ 26m
hie2 = (hf e2 + 1) = 21 = (21)(6.16) ∼= 129 Ω (13.3.33)
ICQ2 4.22m
Ri1 ∼= R1 ||R2 || [hie1 + (hf e1 + 1) RE1 ] = 30k||60k|| [108 + (21) (1k)] ∼
= 10.3 kΩ (13.3.34)
Later, let us calculate the no-load gain Av2 = vo /vi2 = vo /vo1 of the second stage
vo −hf e2 RC − (20) (2k)

Av2 = = = = 1.89 (13.3.35)
vo1 hie2 + (hf e2 + 1) RE2 129 + (21) (1k)
Now, let us calculate the overall gain AVs1 = vo1 /vs of the rst stage

vo1 Ri1 (hf e1 + 1) RE1
AVs1 = =
vs Rs + Ri1 hie + (hf e1 + 1) RE1
1
10.3k (21) (1k) ∼
= = 0.91. (13.3.36)
1k + 10.3k 108 + (21) (1k)
So, the overall voltage gain AVs is given by
AVs = AVs1 × Av2 = (0.91) (1.89) = 1.72. (13.3.37)
251
c) From vCE1(max) and vCE2(max) calculated (13.3.30) and (13.3.31) in part (a), and from Av2 and
AVs1 calculated (13.3.35) and (13.3.36) in part (b), we see that the limiting factor comes from
the rst stage. Because
vCE2(max)

12.66
vCE1(max) < ⇒ 4.82 < ⇒ (4.82 V < 6.7 V) (13.3.38)
Av2 1.89
Consequently,
vCE1(max) 4.82
vs(max) = = = 5.30 V. (13.3.39)
AVs1 0.91

252
a) Calculate the overall voltage gain AVs = vo /vs .

b) Find the output resistance Ro .
253
13.4 Cascode Amplier
The cascode conguration is a CE-CB combination, where the collector of the rst transistor is
connected to the emitter of the second transistor as shown in Figure 13.12 below.
Figure 13.12: A cascode conguration.
The arrangements provide a relatively high-input impedance with low voltage gain for the rst CE
stage to ensure the input Miller capacitance is at a minimum, whereas the following CB stage provides
the high gain.
Therefore, therefore this combination works well in high frequency applications.
254
Example 13.8: For the cascode amplier below, nd the input resistance Ri , output resistance
Ro and the voltage gain Av = vo /vi .
Figure 13.13: A cascode amplier circuit for Example 13.8.
Solution: Let us perform DC analysis rst and calculate IEQ1
VB1 − VBE(ON )
IEQ1 = (13.4.40)
RE
RB3
RB1 +RB2 +RB3
VCC − VBE(ON )
∼
= . . . ignoring IB1 and IB2 as βRE RB3
RE
(13.4.41)
4.7k
6.8k+5.6k+4.7k
18 − 0.7 4.95 − 0.7
= = (13.4.42)
1k 1k
= 4.25 mA (13.4.43)
(13.4.44)
As α = 100/101 ∼
= 1, IEQ1 ∼
= ICQ1 = IEQ2 ∼
= ICQ2 . hie = hie1 = hie2 given
So, by

γ 26m ∼
hie = (hf e + 1) = (101) = 618 Ω (13.4.45)
IEQ 4.25m
So, the SSAC equivalent circuit is given in Figure ?? below
255
Figure 13.14: SSAC equivalent circuit for Example 13.8.
Thus, we can calculate Ri , Ro and Av as follows
Ri = RB3 ||RB2 ||hie1 = 4.7k||5.6k||618 ∼

= 498 Ω (13.4.46)
Ro = RC = 1.2 kΩ (13.4.47)

vo ie2 ib1
Av = (13.4.48)
ie2 ib1 vi

1
= (−hf b2 RC ) (−hf e1 ) . . . hf b = −1 (13.4.49)
hie1
(100) (1.2k)
=− = −194. (13.4.50)
0.618k
Homework 13.5: Show that the voltage gain AV1 = vo1 /vi = −1 for the rst stage of the amplier.
Consequently, comment on the Miller eect.
13.5 Darlington Pair

A very popular connection of npn two bipolar junction transistors for operation as one superbeta
npn transistor is the Darlington connection shown in Figure 13.15 below.
Figure 13.15: Darlington combination.
The main feature of the Darlington connection is that the composite transistor as shown in Figure 13.16
below acts as a single unit with a current gain that is the product of the current gains of the individual
transistors.
256
Figure 13.16: Single npn transistor representation of the Darlington pair.
Consequently, current gain βD and base-emitter turn-on voltage VBED (ON ) are given as follows
βD = β1 β2 + β1 + β2 ≈ β1 β2 (13.5.51)
VBED (ON ) = 2VBE(ON ) (13.5.52)
Such that IC = βD IB and IE = (βD + 1) IB when both transistors are in the forward active mode.
Homework 13.6: Show that expressions (13.5.51) and (13.5.52) above for βD and VBED (ON ) are
correct.
13.6 Feedback Pair

The feedback pair connection shown in Figure 13.17 below is a two-transistor circuit that operates
like the Darlington circuit.
Figure 13.17: Feedback pair connection.
Notice that the feedback pair uses a pnp transistor driving an npn transistor, the two devices acting
eectively much like one pnp transistor as shown in Figure 13.18 below. As with a Darlington con-
nection, the feedback pair also provides a very high current gain.
257
Figure 13.18: Single pnp transistor representation of the feedback pair.
Consequently, current gain βF and emitter-base turn-on voltage VBEF (ON ) are given as follows
βF = β1 β2 + β1 ≈ β1 β2 (13.6.53)
VBEF (ON ) = VBE(ON ) (13.6.54)
Such that IC = βF IB and IE = (βF + 1) IB when both transistors are in the forward active mode.
Homework 13.7: Show that expressions (13.6.53) and (13.6.54) above for βF and VBEF (ON ) are
correct.
258

Ele230 Lecture Notes PDF

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Ele230 Lecture Notes PDF

Uploaded by

Copyright:

Available Formats

Electronics I

List of Figures xvi

3 Rectiers and Voltage Regulating Filters 44

4 Bipolar Junction Transistor (BJT) 72

7 Field Eect Transistors (FETs) 131

8 DC Biasing of FETs 150

9 AC-DC Load Lines of FET Circuits 170

10 BJT Small-Signal Analysis 173

11 FET Small-Signal Analysis 201

12 Frequency Response of Ampliers 220

13 Multistage (Cascaded) Ampliers 244

2.1 A series clipper circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.1 Ideal half-wave rectier output of a sinusoidal input vi (t) = Vm sin(2πt/T ). . . . . . . 45

4.1 Types of transistors: (a) pnp, (b) npn. . . . . . . . . . . . . . . . . . . . . . . . . . . 72

6.1 A voltage-divider common-emitter BJT circuit. . . . . . . . . . . . . . . . . . . . . . 119

8.1 Fixed-bias JFET circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

10.1 Two-port voltage-gain amplier model. . . . . . . . . . . . . . . . . . . . . . . . . . . 173

11.1 FET small-signal equivalent circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

12.1 First order highpass RC lter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

13.1 A cascaded (or multistage) system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

Example 1.1 (Diode Example 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Example 1.2 (Diode Example 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Example 1.3 (Diode Example 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Example 1.4 (Diode Example 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Example 2.1 (Series Clipper with a DC source) . . . . . . . . . . . . . . . . . . . . . . . 30

Example 2.2 (Various Series Clippers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Example 2.3 (Parallel Clipper with a DC source) . . . . . . . . . . . . . . . . . . . . . . 32

Example 2.4 (Diode Limiter or Dual-Diode Parallel Clipper) . . . . . . . . . . . . . . . 32

Example 2.5 (Various Parallel Clippers) . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Example 2.6 (Clamper Example 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Example 2.7 (Clamper Example 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Example 2.8 (Various Clampers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Example 2.9 (Zener Regulator) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Example 3.1 (DC Component of Half-Wave Rectier Output) . . . . . . . . . . . . . . . 45

Example 3.2 (DC Component of Full-Wave Rectier Output) . . . . . . . . . . . . . . . 45

Example 3.3 (DC Component of Triangular Waveform) . . . . . . . . . . . . . . . . . . 46

Example 3.4 (AC Component of Triangular Waveform) . . . . . . . . . . . . . . . . . . 46

Example 3.5 (RMS value of an AC+DC signal) . . . . . . . . . . . . . . . . . . . . . . . 48

Example 3.6 (RMS value of Triangular Waveform) . . . . . . . . . . . . . . . . . . . . . 49

Example 3.7 (RMS value of Half-Wave Rectier Output) . . . . . . . . . . . . . . . . . 50

Example 3.8 (RMS value of Full-Wave Rectier Output) . . . . . . . . . . . . . . . . . . 50

Example 3.9 (RMS value of AC component - Triangular Waveform) . . . . . . . . . . . 50

Example 3.10 (RMS value of AC component - Half-wave Rectier Output) . . . . . . . . 51

Example 3.11 (RMS value of AC component - Full-wave Rectier Output) . . . . . . . . 51

Example 3.12 (Voltage Regulation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Example 3.13 (Ripple Factor of Half-Wave Rectier Output) . . . . . . . . . . . . . . . . 59

Example 3.15 (Capacitor Filter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Example 3.16 (RC Filter Example 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Example 3.17 (RC Filter Ecample 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Example 3.18 (π Filter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Example 4.1 (Amplication in Common-Base Conguration) . . . . . . . . . . . . . . . 79

Example 4.2 (Determining β) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Example 5.1 (Fixed-Bias BJT Circuit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Example 5.2 (Fixed-Bias Load Line) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Example 5.3 (Emitter-Stabilized Bias BJT Circuit) . . . . . . . . . . . . . . . . . . . . . 99

Example 5.4 (Voltage-Divider Bias BJT Circuit) . . . . . . . . . . . . . . . . . . . . . . 103

Example 5.5 (Common-Collector Bias Circuit) . . . . . . . . . . . . . . . . . . . . . . . 106

Example 5.6 (Voltage-Divider Bias pnp Circuit) . . . . . . . . . . . . . . . . . . . . . . 107

Example 5.7 (Bias Stabilization) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Example 6.1 (AC-DC Load Lines Example 1) . . . . . . . . . . . . . . . . . . . . . . . . 126

Example 6.2 (AC-DC Load Lines Example 2) . . . . . . . . . . . . . . . . . . . . . . . . 127

Example 6.3 (AC-DC Load Lines Example 3) . . . . . . . . . . . . . . . . . . . . . . . . 129

3 Rectiers and Voltage Regulating Filters 44

7 Field Eect Transistors (FETs) 131

12 Frequency Response of Ampliers 220

13 Multistage (Cascaded) Ampliers 244

3.1 Ideal half-wave rectier output of a sinusoidal input vi (t) = Vm sin(2πt/T ). . . . . . . 45

10.1 Two-port voltage-gain amplier model. . . . . . . . . . . . . . . . . . . . . . . . . . . 173

12.1 First order highpass RC lter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Example 3.1 (DC Component of Half-Wave Rectier Output) . . . . . . . . . . . . . . . 45

Example 3.2 (DC Component of Full-Wave Rectier Output) . . . . . . . . . . . . . . . 45

Example 3.7 (RMS value of Half-Wave Rectier Output) . . . . . . . . . . . . . . . . . 50

Example 3.8 (RMS value of Full-Wave Rectier Output) . . . . . . . . . . . . . . . . . . 50

Example 3.10 (RMS value of AC component - Half-wave Rectier Output) . . . . . . . . 51

Example 3.11 (RMS value of AC component - Full-wave Rectier Output) . . . . . . . . 51

Example 3.13 (Ripple Factor of Half-Wave Rectier Output) . . . . . . . . . . . . . . . . 59

Example 4.1 (Amplication in Common-Base Conguration) . . . . . . . . . . . . . . . 79

Example 13.2 (AC-Coupled FET Amplier) . . . . . . . . . . . . . . . . . . . . . . . . . 246

Example 13.3 (AC-Coupled BJT Amplier 1) . . . . . . . . . . . . . . . . . . . . . . . . 247

Example 13.4 (AC-Coupled BJT Amplier 2) . . . . . . . . . . . . . . . . . . . . . . . . 248

Example 13.5 (DC-Coupled BJT Amplier 1) . . . . . . . . . . . . . . . . . . . . . . . . 249

Example 13.6 (DC-Coupled BJT Amplier 2) . . . . . . . . . . . . . . . . . . . . . . . . 252

Example 13.7 (DC-Coupled BJT Amplier 3) . . . . . . . . . . . . . . . . . . . . . . . . 253

Example 13.8 (Cascode Amplier) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Homework 3.1 (Full-Wave Rectiers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Homework 13.2 (AC-Coupled BJT Amplier) . . . . . . . . . . . . . . . . . . . . . . . . . 248

Homework 13.3 (DC-Coupled BJT Amplier 1) . . . . . . . . . . . . . . . . . . . . . . . . 252

Homework 13.4 (DC-Coupled BJT Amplier 2) . . . . . . . . . . . . . . . . . . . . . . . . 253

Homework 13.5 (Cascode Amplier) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256