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Testability Lec 21 PDF
Testability Lec 21 PDF
Design for
Testability
Outline
q Testing
– Logic Verification
– Silicon Debug
– Manufacturing Test
q Fault Models
q Observability and Controllability
q Design for Test
– Scan
– BIST
q Boundary Scan
q A2 {1010} {1110} A1
n2 n3
q A1 {0100} {0110} A0
q A0 {0110} {0111}
q n1 {1110} {0110}
q n2 {0110} {0100}
q n3 {0101} {0110}
q Y {0110} {1110}
Flop
SI Q
D
q Normal mode: flip-flops behave as usual
q Scan mode: flip-flops behave as shift register
scan-in
q Contents of flops
Flop
Flop
Flop
can be scanned Flop
Flop
Flop
Logic Logic
inputs outputs
Flop
Flop
values scanned
Flop
Flop
Flop
in scanout
(b)
f f
fd
f D
f Q
fd
SCAN
fd X
Q
fs f f
fs f
SI
(c)
fs
f f
Flop
Flop
D D D
1 110
2 101
3 010
Flops reset to 111 4 100
5 001
6 011
7 111 (repeats)
C[0]
C[1]
Q[2] / SO
Flop
Flop
Flop
SI 1
0 Q[0]
Q[1]
CHIP B CHIP C
CHIP A CHIP D
Serial Data In