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effective area of Litz wire. ܨோ is the ratio between AC and Then, the plant transfer function ܶ ሺݏሻ can be
DC loss. ߩ௦ is simulated current density. Table III represented in Eq. (18).
డ ሺ௦ሻ
summarizes the simulated transformer losses and related ܶ ሺݏሻ ൌ
డ௦
ൌ
specifications. మ ಽೝమష మ
మ
భ మೞ మ
Table III. Simulated transformer losses and related specifications. ଶమ ோ మೞమ భ
ି ೝభ ା
ೞయ ಽ భ
గమ మ మమ
మ (18)
Parameters Heavy load Light load ቄቀ
భ
ା௦ೝభ ቁାቀమ ௦ೝమ ା ା మ ோ ቁቂଵା
భ
ቀ
భ
ା௦ೝభ ቁቃቅ
మೞభ మೞమ ഏ ೞಽ మೞభ
Primary ܨோ 3.04 1.9
As indicated in Fig. 10, system loop gain is defined as,
Secondary ܨோ 3.22 2.13
Core loss (W) 16 8.1
ܩܮൌ ܥሺݏሻܶ ሺݏሻ (19)
Winding loss (W) 15.1 5.2 Therefore, the closed loop transfer function ݃ሺݏሻ of the
PI control system is obtained.
ሺ௦ሻ் ሺ௦ሻ
IV. DESIGN METHODOLOGY OF THE CONTROL STAGE ݃ሺ ݏሻ ൌ ൌ
ଵାሺ௦ሻ் ሺ௦ሻ
ೖ
ା
A. Closed Loop Control Strategy ೞ
మ (20)
భ మ మమ భ భ
ഏమ ቊ൬మೞ శೞಽೝభ ൰శቆమೞಽೝమశ శ ೃ ቇభశೞಽ ൬ శೞಽೝభ ൰൨ቋ
ೖ భ మೞమ ഏమ మೞభ
Frequency modulation [18] as a part of closed loop ା ା
ೞ మ
మ ಽೝమష మ
control is implemented to achieve the CV charging of the ۇభ
మమ ೃ ೇ ۈమ షಽೝభ శ
మೞ మۊ
మೞ భ ೞయ ಽ భ ۋ
battery, which is demonstrated in the Fig. 9. Voltage control ۉ ی
loop is implemented to regulate the output voltage. As In order to guarantee the system stability using the
indicated by Fig. 9, a general PI compensator is small signal model, all the poles of the closed loop gain
implemented in the feedback loop and the transfer function ݃ሺݏሻ should be located in the left-half-plane. Thus, bode
for a PI compensator is given as Eq. (16). plot of this system has been investigated, as shown in Fig.
௦ା௭ 10. It is clear from the bode plot that the PI controller offers
ܥሺݏሻ ൌ ݇ ൌ ݇ ቀ ቁ (16)
௦ ௦
a high attenuation to the higher frequency (>switching
where, ݖis the zero of controller.
frequency) components by maintaining enough phase
With the increase of ݇ , the magnitude response gets a
margin (~166o) simultaneously. This helps the system act as
gain offset resulting the zero crossing to be happening at a more robust to any high frequency disturbances.
farther frequency, which increases the bandwidth. This
results in a faster dynamic response but may jeopardize
Magnitude (dB)
Frequency (kHz)
Fig. 9. Voltage control loop structure of the CLLC converter. Fig. 10. Bode plot system response with PI controller.
Similarly, this closed loop control strategy can be Considering the phase angle, turn-on of the secondary
implemented to achieve the constant current (CC) charging side switches should be strictly synchronized with the
of the battery. In the closed current loop, output current is polarity of the secondary resonant current. If the SR timing
sensed and employed as feedback signal. During the period is not properly set, there will be a circulating current in the
of CC charging of the battery, the regulated charging current secondary resonant tank to cause additional conduction loss.
is required. By means of frequency modulation, the output To minimize the circulating current in secondary resonant
current is regulated and raises the battery terminal voltage tank, Eq. (29) must be satisfied, which will prohibit the
until the upper charge voltage limit is reached, when the conduction through the undesired path.
current drops due to saturation. Thus, CC charging can be ݐௗ̴௦ ݐௗ௬ ߜ௫ (29)
achieved by using this control loop strategy. where, ݐௗ̴௦ denotes the dead-time during turn-on of a
B. Proposed Synchronous Rectification Method secondary MOSFET and ݐௗ௬ is the settling phase delay
time, which is the phase difference between primary and
Due to the characteristics of resonant tank, there exists secondary PWM in the digital signal processor. Fig. 12
a phase shift between primary MOSFET gate pulse and shows the scenario of dead time and phase delay.
secondary resonant current, which is defined as į and Vgs, pri Vgs, sec Vgs, pri Vgs, sec
determined by the resonant network and operating
frequency. A systematic modeling is given below to conduct tdelay
the phase lag estimation without the help of sensors. tdb_rise t
From FHA, the input impedance ܼ of the equivalent
Ir2
circuit in Fig. 2 can be obtained as follows.
ଵା௧ ା௧ ାሺ௧ ା௧ ሻ t
ܼ ൌ షഘమభమమೃǡ య భ ర మ ಽ (21)
ାఠభ ൬ଵିఠమ ଶమ ቀ
మ ାమ ቁ൰
Zero crossing happens
మ
Fig. 12. Theoretical waveforms and phase delay.
where,
భ Fig. 13 shows the conducting path of circulating current
ݐଵ ൌ ߱ସ ܥଵ ʹܥଶ ቀܮ ܮଶ ܮଵ ܮଶ ቁ (22) in the secondary side. If the gate pulse of high MOSFET
మ
ఠయ ோǡ భ ଶమ ሺ ାభ ሻ
ݐଶ ൌ (23) comes earlier than zero crossing of the resonant current, the
మ
ଶమ secondary side resonant current partially circulates through
ݐଷ ൌ െ߱ଶ ቀܮ ܥଵ ܮଵ ܥଵ ܮଶ ʹܥଶ ቁ (24)
మ the high-side MOSFET and resonant capacitor (Cr3). In
ఠோǡ ଶమ
ݐସ ൌ
మ
(25) addition, a considerable portion of the resonant current takes
Thus, ߜ is obtained as, the path of discharging the battery. This circulation results
ߜ ൌ ߮ூ ିூೞ ߮ ିூ ൌ ݈ܽ݊݃݁ ቀ ቁ ݈ܽ݊݃݁ሺܼ݅݊ሻ
ூ
(26) in additional conduction losses in the secondary MOSFET
ூೞ and transformer winding, which potentially degrades the
ூ
where, ݈ܽ݊݃݁ ቀ ቁ represents the phase difference between conversion efficiency. To minimize circulating current in
ூೞ
primary and secondary resonant current, which can be the secondary side, dead band control is introduced so that
derived from FHA model. zero crossing of resonant current occurs within the dead
௦ሺ ାమ మ ሻା
మ
ାோǡ
time.
ೞమమ ൫మ ିఠమ ଶమ ሺ ାమ మ ሻ൯ାఠோǡ ଶమ
ೞ
ൌ
௦
ൌ
ିఠమ ଶమ
(2)
మ ିఠమ ଶమ ሺ ାమ మ ሻ
݈ܽ݊݃݁ ቀ ቁ ൌ െ
ሺ
ೞ ఠோǡ ଶమ
ሻ (28)
The plot of phase angle ߜ versus frequency is shown in
Fig. 11. Note that the zero-crossing frequency is around
109kHz, where the primary gate pulse has the same phase
angle with the secondary current. Within the operating
frequency range, it can be observed that the phase angle has Fig. 13. Circulating current path in the secondary side if (a) gate pulse is
the lagging and leading behaviors with respect to different appropriately engaged; (b) gate pulse is not appropriately engaged.
frequencies.
To implement this methodology, additional margins
90
need to be added to withstand the quantization error, as
45 Phase leading shown in Eq. (30),
Phase (deg)
ଵ ଵ
0 Frequency (kHz): 109.55 ݐௗ̴௦ ݐ ݐௗ̴ ݐ௪ (30)
Phase lagging Phase (deg): 0 ଶ ೝ
-45
where, ݐ and ݐௗ̴ denote the turn-on time and dead
-90 Operating range time during turn-off of the secondary MOSFETs,
-135 1 2 3 respectively. ݐ௪ is the additional margin, which is
10 10 10
Frequency (kHz) kept at 20ns.
Fig. 11. Phase angles between primary PWM and secondary resonant Moreover, another trade-off should be taken into
current in frequency-domain. consideration that the dead time needs to be long enough for
handling the worst case within the given frequency range. V. EXPERIMENTAL RESULTS
On the other hand, it is noteworthy to mention that the As verification to the proof-of-concept, the bi-
increase of the dead time degrades the power conversion directional CLLC converter is designed and tested up to
efficiency and the regulation in CV mode control. 3.3kW. Photographs of the prototype is shown in Fig. 15.
To verify this methodology, a laboratory experiment
with the developed prototype are conducted. Fig. 14 shows
the experimental waveforms of dead band control,
respectively. Drain-to-source voltage ሺܸௗ௦ ሻ during the dead
time is higher than that during the conduction period due to
the differences in voltage drops between the body diode and
MOSFET. Fig. 15. CLLC converter prototype.
Fig. 16 shows the steady state waveforms of the CLLC
converter operating at 3.3kW with 110kHz switching
frequency. The output voltage and output current are
regulated at 400V and .54A, respectively at an input of
600V.
Iout
Vds
Ires,2
Vout
Fig. 14. Verification to SR operations.
For a fair comparison, the SiC Schottky diode (a) (b)
SCS120AGC is added to be another candidate for the Fig. 16. Experiment results at full power: (a) steady state waveforms in CV
comparison objective. The key parameters of the selected mode. (b) Thermal image of the transformer.
diode and the MOSFET (C2M0040120D) are summarized In order to verify the effectiveness of voltage loop and
in Table IV. current loop design, both step-up and step-down load
Table IV. Key parameters of the selected diode and the MOSFET. transients are conducted in the experiment. Fig. 1 (a) and
SiC diode SiC MOSFET
Fig. 1 (b) show the closed voltage loop transients from
ܴௗ௦Ǥ - 40݉ȳ 2kW to 1.5kW and 1.5kW to 2kW, respectively. Output
Forward voltage ܸ 1.V 3.3V voltage is settled at its reference level i.e. 400V within 30ms
Reverse recovery charge ܳ - 283nC for both the cases.
Reverse recovery time ݐ 0ns 54nS
Blocking voltage 600V 1200V
Continuous forward current 20A 60A