Architecture of TMS320C5X DSPs

said
The block diagram of the internal architecture of C5X is shown in Fig. 3.1. The 320C5X DSPs for
are

to have advanced Harvard architecture because they have separate memory bus structures pro-
the program and data
gram and data and have instructions that enable data transfer between memory
area.

3.2 BUS STRUCTURE

Separate program and data buses allow simultaneous access to program instructions and data, provid-
ing a high degree of parallelism. For example, while data is multiplied, a previous product can be loaded
into, added to or subtracted from the accumulator and, at the same time, a new address can be
generated. Such parallelism supports a powerful set of arithmetic, logic and bit-manipulation opera
tions that can all be performed in a single machine cycle. In addition, the C5X includes the control
mechanisms to manage interrupts, repeated operations and function calling.
The 'CSX architecture has four buses and their functions are as follows:
SS DigalSgnalPecess

MEMORY

Program Data Progra

ROM SARAM
Data
DARAM
Data Pro
B2
Peripheral
DARAM
82x 16) Senial
512 port 1
81
x16) Se
LOST K S12x 16
port 2
TDM
Serial
port
Buffered
Senal
pot

Progrem CPU Timer

conboliee Memony
Progren Mapped Host
COunte Regste
CALU
pot 18
Staus interface
control
Multiplier Testiem
egisters Accumulator ukaton
Hardware Auxiliary ACC bufer
Sadk
Shiters Parellel
Register Logic
son Anthmetic
Generaion Anthmetic Logic unit Unit
Logic Unit

o
Tme Instructon (ARAU)
Register
(ALU) (PLU)

Data Bu
Fig. 3.1 Intemal architecture of C5X
Program bus (PB): It carries the instruction code and immediate
space to the CPU. operands from program memoryy
Program address bus (PAB): It
provides addresses to program
Writes memory space for both reads and
Data read bus (DB): It
Data read address bus interconnects various elements of the CPU to data
and data buses can work(DAB): provides the address to access the data
It memory space.
together memory
on-chip data memory andspace.
to transfer The program
program memory to the data from
multiplier for single-cycle multiply/accumulateintermal or external
operations.
 TMS320CSX
59
Architecture of

occupy data memO

CPU registers (except STO and STI), Deripheral registers and I/O ports funcuons
their
or the registers/execution units in the CPU of C5X
DSP processors and
space. Some
are as follows.

3.3 CENTRAL ARITHMETIC LOGIC UNIT (CALU)

arithmetic logic unit (ALU), accu
It consists of the following elements: (16x16)-bit parallel multiplier, and
register (PREG) each with 32 bits
mulator (ACC), accumulator buffer (ACCB), product
0-16-bit left barrel shifter and right barrel shifter.
performed in
One of the operands for the ALU operation comes from ACC. The result operations
of
word of ACC can be
central ALU are stored in ACC. Either the higher order word or lower order Ihe
loaded from memory. A 32-bit register denoted as ACCB is used for temporary storage of ACC.
of numbers repre
hardware multplier unit in the C5X processors performs 16 x 16 multiplication
The 16-bit tempo-
sented in 2's complement form. The 32-bit PREG holds the result of multiplication.
rary register 0 (TREGO) holds the multiplicand. The other operand for the multiplication can be speci

fied using one of the addressing modes.

0-16-bit left barrel shifter and right barrel shifter in CALU permit the contents of memory to be left
shifted by 0 to 16 bits beforetheyare either fed to ALU or stored from ALU to memory, The CPU
registers ACC and PREG can also be shifted using these shifters. In this case they require two cycles.
AS-bit register TREGl specifies the number of bits by which the scaling shifter should shift eitherthe
incoming data to one of the CPU registers or vice versa. When the incoming data to CPU is left shifted
by the scaling shifter the LSBs are filled with 0.

3.4 AUXILIARY REGISTER ALU (ARAU)

It consists of eight 16-bit auxiliary registers (ARs) ARO-AR7, a 3-bit auxiliary register pointer (ARP)
and an unsigned 16-bit ALU. ARAU calculates indirect addresses by using inputs from ARs, 16-bit
index register (INDX) and auxiliary register compare register (ARCR). The ARAU can autoindex the
current AR while the data memory location is being addressed and can index either by +1 or by the
contents of the INDX. As a result, accessing data does not require the CALU for address manipulation;
therefore, the CALU is free for other operations in parallel. This makes the instructions to be executed
faster compared to the conventional microprocessors. For example, let us consider the following
sequence of 8085 instructions:
MOV A, M
INXH
These instructions enable the accumulator to be loaded
using indirect addressing mode and HL
register used as the address pointer is incremented. These two instructions can be
replaced by a single
5X instruction LACC *4, 0.
Further, any one of the auxiliary registers can be used as the address
above instruction. The pointer and incremented by the
register that will be used is specified by the content of the ARP
The auxiliary registers ARO-AR7 may also be used as the
general purpose registers for holding the
operands for arithmetic and logical operations in CALU. Some of the other
functions are as follows: registers of ARAU and their