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Outline
Multiplexers
Combinational Synthesis Using Multiplexers
Circuit Building Decoders
Blocks Synthesis Using Decoders
Encoders

VOLKAN KURSUN Code Converter Example

Some material from McGraw Hill
Unsigned Comparators
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2-to-1 Multiplexer Larger Multiplexers

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s
s f  A multiplexer with n data inputs
w0
w1
0
1
f 0 w0
needs log2n select inputs (or 2n data
1 w1
(b) Truth table
inputs require n select signals)
(a) Graphical symbol
Larger multiplexers can be built using
w0 w0 smaller multiplexers
Example-1: a 4-to-1 multiplexer can
s f s be built with three 2-to-1 multiplexers
w1 w1 Example-2: a 16-to-1 multiplexer can
f
(d) Circuit with transmission gates
be built with five 4-to-1 multiplexers
(c) Sum-of-products circuit
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 4-to-1 Multiplexer 4-to-1 Multiplexer
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f = s1’s0’w0 + s1’s0w1 + s1s0’w2 + s1s0w3 Example-1: a 4-to-1 multiplexer can

s0
s1 s1 s0 f
s
be built with three 2-to-1 multiplexers
w0
w1
00
01
0 0 w0 1 s1 s0 f
f 0 1 w1
w2 10
1 0 w2 s0
w3 11
1 1 w3
0 0 w0
(a) Graphic symbol (b) Truth table
s0 0 1 w1
w0 0 w2
w0
1 0
s1
w1 1 1 1 w3
w1
0
f f
w2
1

w2 0
w3
w3 1
(c) Circuit
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8-to-1 Multiplexer VHDL Code 8-to-1 Multiplexer VHDL Code

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 16-to-1 Multiplexer 2x2 Crossbar Switch
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 nxk crossbar switch: a s

Example-2: a 16-to-1 multiplexer can
circuit with n data inputs
be built with five 4-to-1 multiplexers and k outputs with x1 y1

f
capability to connect any x2 y2

input to any output based (a) A 2x2 crossbar switch

on select signals
s2
s3
x1 0
 2x2 crossbar switch: either 1
y1

of the two inputs x1 and x2 s y2 y1

can be connected to either s 0 x2 x1
1 x1 x2
of the two outputs y1 and x2 0
y2
y2 under the control of a 1

select signal s
w11

w12

w15
w0

w3

w4

w7

w8
s0
s1

(b) Implementation using multiplexers

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Synthesis of Logic Functions

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Outline
Multiplexers  Multiplexers can be used to synthesize logic
functions: apply the inputs as select signals and
Synthesis Using Multiplexers the output corresponding to each row in the truth
table as constant data inputs to the multiplexer
Decoders  Example: Consider the following XOR function with
two inputs f = w1 w2
Synthesis Using Decoders w 1
w 2
f
w
w
2
1

Encoders 0 0 0
0
0 1 1
1
Code Converter Example 1 0 1 1
f

1 1 0 0
Unsigned Comparators
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Implementation using a 4-to-1 multiplexer
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 Synthesis of Logic Functions 3-Input Majority Function
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 Example: Consider the following XOR function with  Implementation with a 4-to-1 multiplexer:
two inputs f = w1 w2 any two of the three inputs can be applied
 A better implementation with only one 2- to the select inputs of the multiplexer
w1 w2 w3 f
to-1 multiplexer: w1 input is applied as 0 0 0 0
w1

0
w2

0 0
f

the select signal to the multiplexer 0

0
0
1
1
0
0
0
0
1
1
0
w3
w3
w1 w2 f 0 1 1 1 1 1 1
w1 f 1 0 0 0
Modified
w1 1 0 1 1
truth table
0 0 0 w2
1 1 0 1
0 1 1 1 1 Note: 3-input majority
0 1 1 function implements
1 w2 w2 w2
w1 the carry output of a
1 0 1 f
0 full adder
w3
1 1 0 f
1
(b) Modified truth table (c) Circuit
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3-Input XOR with Multiplexers 3-Input XOR with 1 Multiplexer

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 
 Can be implemented with two 2-to-1  Can be implemented with one 4-to-1
multiplexers. When w1 = 0, 2 3. multiplexer. Use w1 and w2 to drive the
Alternatively, when w1 = 1, 2 3. select inputs of the 4-to-1 multiplexer
w1 w2 w3 f w2 w1 w2 w3 f w2
0 0 0 0 w1 0 0 0 0
w3
w1
0 0 1 1 0 0 1 1
w2  w3
0
0
1
1
0
1
1
0
w3 2 3
0
0
1
1
0
1
1
0
w3 w3
1 0 0 1 1 0 0 1
1 0 1 0
w2 ⊕ w3 f 1 0 1 0
w3
f
1 1 0 0 1 1 0 0
w3
1 1 1 1 1 1 1 1

Truth table
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Truth table
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 Shannon’s Expansion Theorem
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3-Input Majority Function Revisited

 Example: revisit the three-variable majority
function 1 2 3 1 2 1 3 2 3
Let us expand f with w1using Shannon’s theorem:
 The expansion is done with w1 above. In 1 2 3 2 3 1 2 3 2 3
general, any of the n variables can be used 1 2 3 1 2 3
for the expansion. w1 w2 w3 f w1
0 0 0 0 w1 f
w2
 Example: revisit the three-variable majority 0 0 1 0
0 w2w3 w3
function 1 2 3 1 2 1 3 2 3 0 1 0 0
1 w2 + w3
Let us expand f using w1:
0
1
1
0
1
0
1
0 Truth table f
1 2 3 2 3 1 2 3 2 3 1 0 1 1
1 1 0 1
1 2 3 1 2 3
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1 1 1 1
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3-Input XOR Function Revisited Choice of Variable for Shannon’s Expansion

 Example: revisit the 3-input XOR function  The complexity of the logic expression may vary
depending on which variable wi is used for expansion:
1 2 3 1 2 3 try different variables and choose the expansion
Let us expand f with w1using Shannon’s theorem: with the lowest cost
1 2 3 1 2 3  Example: Consider the following function
1 2 3 1 3 2 3
1 2 3 1 2 3
w1 w2 w3 f w2 Shannon’s expansion with w1 yields:
0 0 0 0 w1 1 3 2 3 𝟏 3 2 3
0 0 1 1 1 3 2 𝟏 2 3
w2  w3
0
0
1
1
0
1
1
0 w3 2 3
Shannon’s expansion with w2 yields:
1 0 0 1 2 1 3 3 𝟐 1 3 3
1
1
0
1
1
0
0
0
w2 ⊕ w3
f 2 1 3 𝟐 1 3
1 1 1 1 Shannon’s expansion with w3 yields the lowest cost:
Truth table
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Circuit VOLKAN KURSUN
3 1
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2 𝟑 1 2 3 2 𝟑 1
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VOLKAN KURSUN Bilkent University VOLKAN KURSUN Bilkent University

Shannon’s Multi-Variable Expansion Shannon’s Multi-Variable Expansion

 Shannon’s expansion can be done with  Example: consider the following function
more than one variable 1 2 3 1 3 1 2 1 3

 

1 2 n 1 2 n 1 2 1 2 3 1 2 3 1 2
n 1 2 n 1 2 n 3 1 2 3 1 2 3
 1 2 3 1 2 3 1 2 3 1 2
1 2 3
w 2
w 1
1 2 n 1 2 3 n 1 2 3
w 3
n 1 2 3 n 1 2 3
n 1 2 3 n 1 2 3 f
n 1 2 3 n 1 2 3 n 1
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Shannon’s Single-Variable Expansion 3-Input Majority Function Revisited

 Example: implement the same function with  Example: the three-variable majority function
2-to-1 multiplexer 1 2 3 1 2 1 3 2 3
We had expanded f with w1 using Shannon’s theorem:
1 2 3 1 3 1 2 1 3
1 2 3 1 2 3 2 3 2 3
 Let us expand g and h with w2: w1 w2 w3 f

1 2 3 1 2 3 1 2 3 2 3 2 3 2 2 3 0 0 0 0
1 3 1 2 3) 2 3 2 3 2 3 2 0 0 1 0
w1 w2 w1
0 1 0 0
0 0 1 1 1
w3
1 0 0 0
f f
w3 1 0 1 1
1 1 0 1
w2 1
1 1 1 1
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 Binary Decoder
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Outline
Multiplexers  A binary number applied as input is decoded and the
corresponding output is asserted. Only one output is
Synthesis Using Multiplexers asserted at a time (one-hot encoding) and the asserted
output corresponds to the valuation of the binary input
Decoders
Synthesis Using Decoders
Encoders
Code Converter Example
Unsigned Comparators
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Binary Decoder with Enable Larger Decoders

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 When Enable = 1, the decoder behaves as before  n-to-2n decoder: a binary decoder with n inputs
 When Enable = 0, all outputs are forced to 0: when the has 2n outputs
decoder is disabled, no output is asserted regardless of
the values of w0 and w1

 Large decoders can be built as an array of

inverters and AND gates. Alternatively, larger
decoders can be constructed from smaller
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decoders.
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 3-to-8 Decoder 4-to-16 Decoder Tree
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 Example: a 3-to-8 decoder built from two 2-to-4 decoders  Example: a 4-to-16 decoder built w0
deco-0
w0 y0 y0
where the w2 input drives the enable inputs of the two decoders from five 2-to-4 decoders where w1 w1 y1 y1
the first decoder drives the enable y2 y2
 w2 = 0 and enable = 1, upper decoder is enabled while the inputs of the four decoders in the y3 y3
En
lower decoder is disabled second stage
 w2 = 1 and enable = 1, upper decoder is disabled while the  w3w2 = 0b00 and en = 1, deco-0 is deco-1
w0 y0 y4
enabled while the other decoders
w
lower decoder is enabled y in the second stage are disabled
w1 y1 y5
0 w0 y0 0 y2 y6
w1 y1 w3w2 = 0b01 and en = 1, deco-1 is w2 w0 y0 y3 y7
w1 y1  En
enabled while the other decoders w3 w1 y1
y2 y2 y2
w2 in the second stage are disabled deco-2
En y3 y3 En En y3 w0 y0 y8
 w3w2 = 0b10 and en = 1, deco-2 is
w1 y1 y9
enabled while the other decoders y2 y10
in the second stage are disabled y3 y11
En
 w3w2 = 0b11 and en = 1, deco-3 is
En w0 y0 y4
enabled while the other decoders deco-3
w1 y1 y5 in the second stage are disabled w0 y0 y12
y2 y6 w1 y1 y13
 en = 0, all decoders are disabled
y2 y14
En y3 y7 and all outputs are forced to 0
En y3 y15
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Synthesis Using Decoders

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Outline
Multiplexers Any logic function with n-inputs can
be implemented using an n-to-2n
Synthesis Using Multiplexers
decoder and OR gates (OR the
Decoders minterms for which the function = 1)
Synthesis Using Decoders
Encoders
Code Converter Example
Unsigned Comparators
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 Synthesis Using Decoders 4-to-1 Multiplexer Using a Decoder
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 Example: 3-input full adder designed with a 3-  The one-hot encoded outputs of a decoder can be used
to-8 decoder and two OR gates to select among the input channels of a multiplexer
ci xi yi ci + 1 si i =  En = 1, the circuit behaves as a 4-to-1 multiplexer
w0
 En = 0, f = 0
i 1 =
0 0 0 0 0 2-to-4
0 0 1 0 1 decoder w1
0 1 0 0 1 s0 i0 y0
0 1 1 1 0 s1 i1 y1 f
1 0 0 0 1 y2 w2
1 En y3
1 0 1 1 0
1 1 0 1 0
w3
1 1 1 1 1
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Decoders Act As Demultiplexers

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Outline
 Demultiplexer does the opposite of a multiplexer: places
the data from a single input channel onto one of multiple
Multiplexers
output channels
 Example: a 2-to-4 decoder can be used as a 1-to-4
Synthesis Using Multiplexers
demultiplexer. The enable input of the decoder serves as
the data input of the demultiplexer. The actual data inputs Decoders
w1 and w0 of the decoder serve as the select signals for
the demultiplexer. The valuation of w1w0 determines which Synthesis Using Decoders
of the four outputs the enable signal is transferred to when
en = 1. Alternatively, when en = 0, all outputs are 0
Encoders
Code Converter Example
Unsigned Comparators
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 Binary Encoders 4-to-2 Binary Encoder
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 2n-to-n encoder: performs the opposite function  Encodes information from 4 inputs into a 2-bit
of a decoder. Encodes information from 2n code: output y1 is 1 when w3 or w2 is 1 and
inputs into an n-bit code output y0 is 1 when w1 or w3 is 1. Therefore, the
 Only one input is supposed to have a value of 1 outputs can be generated with two OR gates.
and the outputs present the binary number w3 w2 w1 w0 y 1 y0 w0 Circuit
that identifies which input is asserted
w3 w2 w1 w0 y1 y0 w1
w0 0 0 0 1 0 0 y0
y0
0 0 0 1 0 0 0 0 1 0 0 1
2n n w2
0 0 1 0 0 1 inputs outputs
0 1 0 0 1 0 yn – 1
0 1 0 0 1 0
w2n – 1 y1
1 0 0 0 1 1 1 0 0 0 1 1 w3
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What Are Encoders Used For? Priority Encoder

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 Each input has a priority level associated with it

 Practical use: more economical (2n-to-n
and the encoder output indicates the active
compaction) transmission of information input with the highest priority
in digital systems  When an input with higher priority is asserted,
 Encoders are used to reduce the number the other inputs with lower priority are ignored
of bits to represent information: encoding  Example: 4-to-2 priority encoder where w3 has
the information allows the transmission the highest priority and w0 has the lowest priority.
link to be built with fewer wires The outputs y1 and y0 represent the binary
number that corresponds to the highest
 Encoding also reduces the needed priority input set to 1. A third output z is
memory capacity for storing provided to check if at least one input is
information: fewer bits are stored asserted. If at least one of the inputs is 1, z = 1. If
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none of the inputs is 1 (all inputs are 0), z =VOLKAN
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0. KURSUN
 4-to-2 Priority Encoder
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Outline
 Example: 4-to-2 priority encoder where w3 has Multiplexers
the highest priority and w0 has the lowest priority
w3 w 2 w 1 w0 y 1 y0 z Synthesis Using Multiplexers
0 0 0 0 d d 0 Decoders
0 0 0 1 0 0 1
0 0 1 x 0 1 1 Synthesis Using Decoders
0 1 x x 1 0 1
1 x x x 1 1 1 Encoders
 Define a set of intermediate signals i0, i1, i2, and i3
i0 = w3’w2’w1’w0, i1 = w3’w2’w1, i2 = w3’w2, i3 = w3
Code Converter Example
y0 = i1 + i3, y1 = i2 + i3, z = i0 + i1 + i2 + i3 Unsigned Comparators
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Hexadecimal Display Hexadecimal Display VHDL

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 Design a decoder to display hexadecimal digits

that correspond to 4-bit binary inputs on a 7-
segment display

Case statement must include a WHEN clause for all possible valuations of
the select signal: OTHERS keyword covers all remaining valuations
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 Unsigned Comparator
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Outline
Multiplexers  Compare the values of two unsigned binary
numbers
Synthesis Using Multiplexers  Example: design a 4-bit comparator to compare
the values of two unsigned inputs A = a3a2a1a0 and
Decoders B = b3b2b1b0
 Define intermediate signals i0, i1, i2, and i3 to
Synthesis Using Decoders determine if the corresponding bit positions are
equal: i0 = 0 0, i1 = 1 1, i2 = 2 2, i3 =
Encoders
3 3

Code Converter Example  AeqB = i3i2i1i0

 AgtB = 3 3 i3 2 2 i3i2 1 1 +i3i2i1 0 0
Unsigned Comparators  AltB = (AeqB + AgtB)’ = AeqB’AgtB’
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4-Bit Unsigned Comparator 4-Bit Unsigned Comparator

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AeqB = i3i2i1i0, AgtB = 3 3 i3 2 2 i3i2 1 1 +i3i2i1 0 0

Alternative design (use the negative and zero flags
AltB = (AeqB + AgtB)’ = AeqB’AgtB’ of a subtractor):

N xgty
Z

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V output: Irrelevant for
unsigned subtraction xlty
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xeqy VOLKAN KURSUN