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    Benc4453021718 Senibina Komputer

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    Muhammad Harith B. Badzli
    The document describes a 4-stage pipelined processor executing 7 instructions. A timing diagram is shown with the stages of each instruction - Fetch (F), Decode (D), Operand Fetch (O), Execute (E). Instruction 4 encounters a pipeline hazard when a JUMP instruction is executed in Instruction 3, before Instruction 4 can complete. The pipeline hazard is classified and two mechanisms are recommended to mitigate pipeline hazards.

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    Benc4453021718 Senibina Komputer

    Uploaded by

    Muhammad Harith B. Badzli
    5 views17 pages
    The document describes a 4-stage pipelined processor executing 7 instructions. A timing diagram is shown with the stages of each instruction - Fetch (F), Decode (D), Operand Fetch (O), Execute (E). Instruction 4 encounters a pipeline hazard when a JUMP instruction is executed in Instruction 3, before Instruction 4 can complete. The pipeline hazard is classified and two mechanisms are recommended to mitigate pipeline hazards.

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    benc4453021718 Senibina Komputer

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    The document describes a 4-stage pipelined processor executing 7 instructions. A timing diagram is shown with the stages of each instruction - Fetch (F), Decode (D), Operand Fetch (O), Execute (E). Instruction 4 encounters a pipeline hazard when a JUMP instruction is executed in Instruction 3, before Instruction 4 can complete. The pipeline hazard is classified and two mechanisms are recommended to mitigate pipeline hazards.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    5 views17 pages

    Benc4453021718 Senibina Komputer

    Uploaded by

    Muhammad Harith B. Badzli
    The document describes a 4-stage pipelined processor executing 7 instructions. A timing diagram is shown with the stages of each instruction - Fetch (F), Decode (D), Operand Fetch (O), Execute (E). Instruction 4 encounters a pipeline hazard when a JUMP instruction is executed in Instruction 3, before Instruction 4 can complete. The pipeline hazard is classified and two mechanisms are recommended to mitigate pipeline hazards.

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    of 17

    SULIT

    (BENC 4453)

    Table Q2(b)
    Line Label lnstru_sti,on ..
    •·

    1 Rl =Rl + 1
    2 R2 = R2+2
    3 JUMPL6
    4 R4=R4+4
    5 R5=R5+5
    6 L6: R6 = R6+6
    7 END

    (i) Create the timing diagram (as in Table Q2(b)(i)) to show how many time units
    are needed for a processor with the 4-stage pipelining.

    Table Q2(b)(i)
    Time-+
    1 2 3 4 5 6 ... ...
    Instruction 1 FI DA FO EX
    Instruction 2
    Instruction 3

    [7 marks]

    (ii) Explain what happened to Instruction 4 during the implementation.


    [2 marks]

    (iii) Classify the pipeline hazard that occurred when JUMP instruction is
    implemented. Explain your answer.
    [2 marks]

    (iv) Recommend TWO (2) mechanisms to mitigate the impact of the pipeline
    hazards.
    [2 marks]

    - 12 -
    SULIT

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