RHSC Debug

RHSC Debug
-- For Internal Use Only --
1 © 2018 ANSYS, Inc. ANSYS Confidential

RHSC Debug
• For getting into debug mode in RHSC, need to do following
>>> os.system('date')
Mon Sep 10 21:22:07 PDT 2018 → MS10
0
>>> os.system('domainname’)
sjo → SO
0
>>> cm_enable_dev_mode('SOMS10')
>>>
• For debug session, following option will help
set_obfuscate_names(True)
– SOTJ26 is the code
– first and last letter from SJO
– first letter from date, first letter from month , and date
• Then, it turns on Debug Mode

Make sure how the PPN created
• For making sure how many PPN created

– av.get_stats()['num_power_partitions’]
– db.get_num_ppns(sv)
– grep "dc stats for ppn" gp/Worker*log | awk '{print $7" "$8}' | sort –u
• For viewing how XT/PP created in GUI

– gui_add_xt_boxes(gui,dv)
– gui_add_pp_boxes(gui, av)

Make sure how created xt-partition
• For making sure how many xt-partition has created

– len(dv.get_partitions())
– gp_scheduler_write_stats('run_stats.txt',dbs=db)
In the output file, it contains the information as following
– 'num_parts': 399,
– 'xt_partitions': [(20,
18, -> This means 21*19=399xt-pn
• For viewing how xt-partition created in GUI
– gui_add_xt_boxes(gui,dv)
it displays how xt-partition created

Make sure how created power-partition(PPN)
• For making sure how many PPN created

– av.get_stats()['num_power_partitions’]
– grep "dc stats for ppn" gp/Worker*log | awk '{print $7" "$8}' | sort –u
– gp_scheduler_write_stats('run_stats.txt',dbs=db)
In the output file, it contains the information as following
– 'matrix_stats': {'pp0': {'ncol': 836604, 'nnz': 3346416, 'nrow': 836604, 'pin_count': 870349},
– 'pp1': {'ncol': 670270, 'nnz': 2681080, 'nrow': 670270, 'pin_count': 512234},
– 'pp4': {'ncol': 128, 'nnz': 512, 'nrow': 128, 'pin_count': 64}},
– 'num_power_partitions': 5,
– 'power_partitions': {'pp0’: ….. → Can understand how the PPN created
• For viewing how PPN created in GUI

– gui_add_pp_boxes(gui,av)
options['analysis_options'].force_num_pp_parts = 1

Force to create PPN
• For controlling number of PPN, following option will be used
options['analysis_options'].force_num_pp_parts = 1
Or
options['layout_options'].force_xt_partitions="1x1"
options['layout_options'].force_xt_partitions="5x5"

Debug Menu
• After pick one of xt-partition, and

right-click, the debug menu appear

Debug Menu
Show Unreduced Circuit Show Reduced Circuit

Change Resistance Value of Circuit
• For changing resistance value of circuit
def ckt_optimize(circuits, dv):
almetal_layer = dv.convert_to_id(Layer('ALMETAL'))
for ckt in circuits:

if ckt.is_coupling() or ckt.is_overlay():
continue
for edge in ckt.get_edges():
if edge.get_layer() == almetal_layer:
if round(edge.get_resistance(),5) == 0.00692:
edge.set_resistance(2.93e-02)
elif round(edge.get_resistance(),5) == 0.06817:
edge.set_resistance(0.0)
edge.set_resistance(0.036)

RedHawk
It asks password. Now, it will display how resistance network

Type “window config” Password = debug true extracted…
Then, ‘Configuration’ window appears
When you want to away from debug mode, type “show SA”
RedHawk Cont’
show SA -node
It displays how the node created…

RedHawk – voltage for instance
plot voltage -name C642/C618092 -sv
Type “plot voltage -name C642/C618092 -sv”, then voltage waveform window will appear

RedHawk – current for instance
Type “gsr set plot_region_no_limit 1”

Then, ‘plot current -region -inst_list c250/c200/c10/BW1_BUF482409_1’, then current waveform window will appear

RedHawk – current for instance
apache.imap: You should set DYNAMIC_SAVE_WAVEFORM 2 in GSR file for enabling this feature.
351799 c250/c200/c10/fpul/flcd0/clk_fpud_L1_8 230.300000 -328.300000 Otherwise you can see the waveform by Aqua for seeing original current waveform by APL
apache.pwr:
351799 230.300000 -328.300000 1 1 2.00001 0.100219 10479 10479 -1 2e+08 2 0 0 0.214752 TMRBUFCLXPA 400 387.5 550 479.384 -9 -9 0 -1 17
mstate.out
# Time: start_time end_time dt (ps)
# <inst_ID> <sample_ID> <state1> <switchT1> ... <stateN> <switchTN>
351799 188 c01 1659 c10 4161 c01 6659 c10 9161 c01 11659 c10 14161 c01 16659 c10 19161 c01 21659 c10 24161 c01 26659 c10 29161 c01 31659 c10
34161 c01 36659 c10 39161 c01 41659 c10 44161 c01 46659 c10 49161
For Checking Current Waveform..

-> Using aqua
➢ aqua cell.current
Select Cell Type
For finding target waveform,

you should use “search” in the
GUI menu
Select Sample ID

• CAP • Current
aplreader TMRBUFCLXPA.cdev aqua TMRBUFCLXPA.current
#############################################################
# #
# Copyright (C) 2002-2018 ANSYS, Inc. #
# aplreader: Current Profile and cdev/pwcdev Reader #
# version 19.1.2 RHEL6 Released Date: 06/14/2018 #
# Linux2.6.32-696.el6.x86_64 #
# #
#############################################################
Info: Reading cdev9v2 file- 'TMRBUFCLXPA.cdev'
Info: cell=TMRBUFCLXPA
Temperature = 25.000000 C; State = ADS_DEFAULT_STATE_LOW; vector = A; active_input = A; active_output = Y;
VDD = 1.350000 V; VSS = 0.000000 V;
pin = VDD, esc = 3.16097e-14 F, esr = 326.273 ohm
pin = VSS, esc = 3.16097e-14 F, esr = 326.273 ohm
pin = VDD, leak = 2.56489e-11 A
pin = VSS, leak = 1.79391e-11 A
Temperature = 25.000000 C; State = ADS_DEFAULT_STATE_HIGH; vector = A; active_input = A; active_output = Y;
VDD = 1.350000 V; VSS = 0.000000 V;
pin = VDD, esc = 3.32599e-14 F, esr = 200.09 ohm
pin = VSS, esc = 3.32599e-14 F, esr = 200.09 ohm
pin = VDD, leak = 9.10471e-12 A
pin = VSS, leak = 1.55631e-11 A
Info: Done

RedHawk-SC – current for instance
From Command
# Plot Instance Waveforms

inst = Instance('c250/c200/c10/fpul/flcd0/clk_fpud_L1_8')
pinP = Pin('VDD’)
pinG = Pin(‘VSS')
# Plot Instance Waveform
print('scn.get_demand_current')
wf = scn.get_demand_current(instance=inst,pin=pinP)
write_to_file('instP.idemandinst',data=wf)
wf = scn.get_demand_current(instance=inst,pin=pinG)
write_to_file('instG.idemandinst',data=wf) You should set keep_stats_level=KeepStats('Full’)
print('av.get_current')
wf = av.get_used_demand_current(instance=inst,pin=pinP)
in analysis-view for enabling this
write_to_file('instP.iinst',data=wf)
wf = av.get_used_demand_current(instance=inst,pin=pinG)
write_to_file('instG.iinst',data=wf)
print('av.get_voltage')
wf = av.get_voltage(instance=inst,pin=pinP)
write_to_file('instP.vinst',data=wf)
wf = av.get_voltage(instance=inst,pin=pinG)
write_to_file('instG.vinst',data=wf)
Instead of writing out to file, you can see waveform using following command.
# Gathering the Instance data
attr = dv.get_attributes(inst) >>> plot(wf)
write_to_file('inst_dv.attr' ,data=attr)
attr = scn.get_attributes(inst) Or you can directly see in console
write_to_file('inst_scn.attr',data=attr)
attr = av.get_attributes(inst) >>> print(attr)
write_to_file('inst_av.attr',data=attr)
eve = scn.get_logic_signal(inst)
write_to_file('inst.signal',data=eve)
eve = scn.get_instance_events(inst)
write_to_file('inst.event',data=eve)
net = Net('C642/N15601')
eve = evx.get_signal_net_cap(net)
write_to_file('inst.netcap',data=eve)

RedHawk-SC – APL current for the cell
From Command You can find out input_transition_time and C1-R-C2 value in the report of
write_to_file('instG.vinst',data=wf) command
cell_name='TMRBUFCLXPA'
user_conditions = {'from_pin' : Pin('A'), 'from_dir' : 'r', 'to_pin' : Pin('Y'), 'to_dir' : 'r', 'input_transition_time' : 4e-10, 'pi_c1': 1.803-14, 'pi_c2' : 1.966e-13,
'pi_r' : 47.58, 'voltage' : 1.35, 'temperature' : 25.0, 'pg_pin' : Pin('VDD'), 'debug_level' : 0, 'include_other_voltages' : False}
dc_result = dv_get_cell_apl_dynamic_currents(dv, Cell(cell_name), user_conditions)
plot(dc_result)
user_conditions = {'from_pin' : Pin('A'), 'from_dir' : 'r', 'to_pin' : Pin('Y'), 'to_dir' : 'r', 'input_transition_time' : 4e-10, 'pi_c1': 1.803-14, 'pi_c2' : 1.966e-13,
'pi_r' : 47.58, 'voltage' : 1.35, 'temperature' : 25.0, 'pg_pin' : Pin('VSS'), 'debug_level' : 0, 'include_other_voltages' : False}
plot(dc_result)
user_conditions = {'from_pin' : Pin('A'), 'from_dir' : 'f', 'to_pin' : Pin('Y'), 'to_dir' : 'f', 'input_transition_time' : 3.875e-10, 'pi_c1': 1.803-14, 'pi_c2' : 1.966e-
13, 'pi_r' : 47.58, 'voltage' : 1.35, 'temperature' : 25.0, 'pg_pin' : Pin('VDD'), 'debug_level' : 0, 'include_other_voltages' : False}
plot(dc_result)
user_conditions = {'from_pin' : Pin('A'), 'from_dir' : 'f', 'to_pin' : Pin('Y'), 'to_dir' : 'f', 'input_transition_time' : 3.875e-10, 'pi_c1': 1.803-14, 'pi_c2' : 1.966e-
13, 'pi_r' : 47.58, 'voltage' : 1.35, 'temperature' : 25.0, 'pg_pin' : Pin('VSS'), 'debug_level' : 0, 'include_other_voltages' : False}
plot(dc_result)
Instead of plotting waveform, you can write out to file using following command.
>>> write_to_file(‘apl_current.wf',data=dc_results)

RedHawk-SC – APL current for the cell(Read APL)
AVM.conf（APL)を読んだ時の波形の確認方法の件
include('./input_files.py')
options = get_default_options()
avm_files = [ './avm.conf', ]
lv = db.create_liberty_view(avm_config_file_names=avm_files, liberty_file_names=lib_files, tag='lv', options=options)
ここまでは設定
APL波形確認
des = dv.get_lib_design()
cell=des.get_cell('HS1P0352W42B04C_RM1R')
セル名指定
apl = cell.lookup_apl_dynamic_current(des,1.32,25)
ここで(des,1.32,25)の1.32は電圧、25は温度を指定しています
table = apl['dynamic_currents'][37517][0]['table']
aplの中のネットID：37517 State：0 を指定してます

stateは0（Read)，1(standby_Ntrig)，2(standby_trg)，3(Write)
wave_state0 = table.get_waveform_from_index(0,0)
plot(wave_state0.get_waveform())

Steps to remove APL samples
Script : /nfs/sjo2ae384-6.data2/ansurasa/TomaHawk/Dyn_correaltion_SH_RH/apl.pl
Steps for generating one sample (single voltage)
STEP1. covert the APL binary file to text file
aplchk -w current.txt cell.current

(apl debug password needed)
STEP2. Run below perl script on text file generated in 1st step and specify voltage value
perl apl.pl current.txt 0.6
STEP3. again covert back text file to binary
aplchk -a2b <output> <input>

MBFF Handling
❑ With Multi-bit flip-flop, it is assumed all switching flops in the bank are switching at
the same time (controlled by the same clock pin).
❑ With Multi-bit flip-flop, it is assumed all flops in the bank are electrically identical (all
flops share the same APL current profile).
❑ MBFF APL firing time :

SH : Both clock and output event currents are fired at the clock event firing time
RH : Clock event current fired at clock event time and output event current at
output event firing time

Local ground current scaling handling
❑ RH Distributes total ground current into the driver ground and receiver ground based
on driver properties, SPEF RC cap and input pin (FANIN) cap distribution .
❑ SH does not have local ground scaling mechanism , It sinks total ground current at
driver ground .
❑ We are using “DYNAMIC_LOCAL_GROUND_CURRENT_SCALING 0” in RH to match

with SH behavior .
Click to add text
❑ SH R&D started working on local ground mechanism implementation in SH , They
have implemented the “DYNAMIC_LOCAL_GROUND_CURRENT_SCALING 1” (RH
default ) option in SH - PE Testing is ongoing .

Debug for NPV scn

show_npv_run
If scn is crushed, create scenario view with

debug_instances.

View and Options

Options
• Following options are available
options = get_default_options()
options = get_default_options(legacy_mode=True)
Same!!
Click to add text
options = get_default_options(redhawk_mode=True)
For making sure default option value..

>>> options = get_default_options()
>>> options['extraction_options'].via_chopping_distance
{'*': 0.5}
>>> options['extraction_options'].top_via_chopping_distance
0.0
>>> options['extraction_options'].enable_via_clustering
'off'

Options – All Options list
• Following options are available
>>> gp.get_default_options()
value_change_options aa = gp.get_default_options()
layout_options for xx in aa.keys():
activity_profile_options
thermal_options print(xx)
scenario_options
power_options
switching_activity_options
path_options
voltage_impact_options
multichip_options
effective_resistance_options
signal_net_current_options
hdl_options
extraction_options
tech_options
liberty_options
analysis_options
timing_graph_options
cmm_options
simulation_options
power_profile_options
grm_options
electromigration_options

Each Options’ option
>>> options['analysis_options'].all_options_ 'expected_factor_nnz_per_ppn': 'cycl e_s tats_method': 'i teration_convergence_threshold_local': 0.02,
'ma x_num_points_in_total_demand': 'pi n_cap_policy': 's nap_instance_current_peaks_only': 'deca p_min_cap':
'res calc_group_currents': 'deca p_model_mode': 'i teration_convergence_voltage_check': 'memory_allowed_per_partition': 8192.0,
's olver_type': 'ena ble_start_from': 'i teration_convergence_threshold_current_rel_change': 'wa veform_compress_initial_max': 1e-06,
's plit_waveforms_to_xps': 'current_source_scale': 1.0, 'pa rti tion_node_cost_factor_v6': 'ps eudo_dc_max_iterations':
'ma x_s olver_threads': 1, 'ma x_l oad_cap_scale_for_toggle': 'mi n_xt_to_pp_ratio': 'i teration_convergence_threshold_current_abs_change':
'default_power_gate_r_off': 's pool_elongation_sparsification_threshold': 'num_xt_partitions_per_overlap_for_simulation': 'i teration_convergence_threshold_current_abs_change_dc':
'ma tri x_dump_file_prefix': 'mi n_res_for_package': 'i teration_convergence_threshold_max_diff_ratio': 'i teration_convergence_threshold_spool_current_rel':
'ma tri x_min_nnz_per_part': 'pa ckage_sim_mode': 'deca p_mode': 'ma x_i ter_count_dc':
'pp_s hape_aspect_ratio_factor': 'ma x_rhs_current': 'i teration_convergence_threshold_current_rel_change_dc': 'xt_to_neighbors': '',
's wi tching_instance_decap_scale': 's ki p_load_caps_in_decap_generation': False, 'pa rtition_pin_cost_factor_v6': 'force_num_pp_parts':
'ma tri x_partitioning_options': 'probe_shadow_cell_pins': 'i teration_convergence_threshold_local_max_rel_diff': 'fa ctor_nnz_exponent':
's olver_temp_dir': 's titch_res': 'i teration_convergence_threshold_local_spool': 0.001, 'deca p_max_res':
'pa rtition_method': 11, 'i teration_convergence_current_check': 'norton_res': 'i ntegration_method':
'i teration_convergence_threshold_dc_current_abs_diff': 'ra mp_up_dc_level_factor': 's cheduler_barrier': 'deca p_external_rh_info':
'pa rtition_resistor_cost_factor_v6': 'el t_multiplier_for_package': 'expected_pin_ppn': 's ta mp_intrinsic_decaps': 1,
'power_partition_snap_points': 'dc_ti me_step_for_package': 0.0, 'ma x_s liding_window_time_step': 's a ve_rlck_netlist':
'mi n_iter_count_dc': 'a daptive_iteration_convergence_threshold': 0.05, 'probe_rollup_instance_pins': 'deca p_max_cap':
'i ncremental_solve_max_diff_threshold': 'xt_to_pp': 'hi stogram_num_bins_map_factor': 'keep_stamped_currents':
'ma x_xt_to_pp_ratio': 'i teration_convergence_threshold': 0.01, 'mi n_iter_count_spool_tr': 'i teration_convergence_threshold_spool': 0.001,
'default_power_gate_r_on': 'bookkeep_combine_step_increment': 'mi n_res': 'deca p_cload_scale':
'i teration_convergence_threshold_max_diff': 'num_pp_factor': 's olver_work_dir': 'ma x_num_cycl es_in_stats':
'vol ta ge_derate_method': 'num_xt_partitions_per_simulation_partition': 'ena ble_legacy_update': 'vol ta ge_derate_blend':
'ma x_book_threads': 1, 'i teration_convergence_threshold_dc': 0.01, 'pa rtition_pin_cost_factor': 'ma tri x_reduction_level':
'i teration_convergence_threshold_spool_current_abs': 'ma x_i ter_count_vcheck': 's a ve_pp_ds': 'a vg_dc_override':
'pa rtition_weight_mode': 2, 'pa rtition_dimensions': 'expected_nodes_ppn': 'rmodel_density':
'force_power_gate_r_on': 'pi n_count_factor_for_load_balancing': 2.5, 'bookkeeping_version': 'deca p_r_driver_estimation_v1':
'grounding_r': 'bump_group_override': 'check_dc_convergence': 'pp_to_xt':
'deca p_r_driver_scale': 'us e_voltage_shift': 'probe_decap_cell_pins': 's a ve_rlck_prefactor_matrix':
'power_gate_pin_resistance': 'mi n_iter_count': 'pa rti tion_factorization_factor': 's s or_factor_dc': 1.0,
'force_l oad_cap': -1.0, 'mi n_load_cap_scale_for_toggle': 'demand_current_shift_limit': 's olver_conserve_memory':
'deca p_min_res': 'num_bump_groups': 'remove_disconnected_arc_demand': 'ma tri x_dump_part_id':
'dc_time_step': 1e-06, 'expected_resistor_ppn': 'ma x_i ter_count': 'tra nsient_voltage_compression_degree':
'ena ble_pin_count_decap': 's nap_instance_currents': 's s or_factor': 1.0, 'bump_sparsity_factor':
'deca p_intr_res_scale': 'hi stogram_num_bins': 's nap_hh_step_multiplier': 'i teration_convergence_threshold_dc_current_rel_diff':
'ma x_check_steps': 'ma x_check_level': 'res calc_num_groups': 'el t_multiplier':
'rmodel_resistance': 'power_partition_strategy': 'mi n_iter_count_spool_dc': 'expected_max_nodes_per_ppn':
'deca p_intr_cap_scale': 'fa ctor_nnz_exponent_min': 's olver_reduction_type': 'i teration_convergence_threshold_local_dc': 0.02,
'pa rti tion_weight_method': 1, 'ra mp_up_nl_r_mult': 'es timate_mem_usage_method': 0, 'fa ctorization_precision':
'a vg_dc_correction': 'force_power_gate_r_off': 's a ve_vi ew_step_increment':
'ma x_node_voltage': 'probe_filler_cell_pins': 'fa ctor_nnz_exponent_max':

Making sure how was set each Options’ option (Tech & EM option)
>>> gp_dict(options['tech_options'].options_) >>> gp_dict(options['electromigration_options'].options_)

{'create_estimated_cap_model': True, {'buffer_size': 1000,
'max_length_to_min_width_ratio': 100.0, 'check_em_for_rollup': False,
'use_solver_for_effective_eps': False} 'check_em_for_shadow': False,
'em_apply_duty_ratio_mode': 0,
'enable_fit_apply_ratio': True,
'enable_length_based_em': True,
'fit_check_perpendicular_edge': False,
'ignore_half_node_scale_for_em': False,
'ignore_sliver_for_gui_browser': False,
'max_reported_violations': 1000000000000000.0,
'pin_as_down_via': False,
'pin_node_as_branch_for_fit': False,
'scheduler_barrier': False,
'treat_lv_as_w_for_samsung': False}

Making sure how was set each Options’ option (liberty option)
>>> gp_dict(options['liberty_options'].options_)
{'apl_read_show_statistics': False,
'apl_voltage_selection': 'All',
'apl_waveform_local_tolerance': 0.01,
'apl_waveform_peak_tolerance': 0.01,
'apl_waveform_table_min_delta': 1e-17,
'convert_apl_to_nlpm': False,
'decap_estimation_scale': 1.0,
'estimate_missing_decaps': True,
'macro_pin_count_threshold': 50,
'nlpm_extrapolation': False,
'partition_liberty_apl_currents': True,
'resistance_unit_is_ohms': False,
'waveform_interpolation_policy': 'Interpolation'}

Making sure how was set each Options’ option (extraction option)
>>> gp_dict(options['extraction_options'].options_) 'drop_tsv_coupling_beyond_max_spacing': False, 'max_num_shell_nodes_borders': 0, 'rollup_overunder_size': 20, 'unused_pseudo_via_layers': None,
{'abs_clean_tolerance': 0.0001, 'drop_unreduced_circuits': None, 'max_ohm_per_length': 5.0, 'rollup_phantom_group_grid_size': 10, 'use_any_angle_cleaner': False,
'auto_bump_blob_detect': True, 'enable_45_degree_snapping': False, 'max_query_distance': 10.0, 'rollup_signal_net_handling': 'keep', 'use_berkeley_solver': True,
'awe_accuracy': 1e-07, 'enable_cache_reuse': False, 'max_res_length': 0.0, 'self_inductance_only': False, 'use_decap_pin_as_regular': True,
'build_mesh_circuit': True, 'enable_cross_metal_via_merging': False, 'min_length_for_inductance': 50.0, 'separated_metal_pseudo_via_layers': None, 'use_old_spef_parser': False,
'build_open_data_for_gui': True, 'enable_density_origin_shift': True, 'move_finger_phantom_to_slab': True, 'si_density_method': 1, 'use_predefined_cap': False,
'bump_blob_boundary_ratio': 0.8, 'enable_equal_potential_for_inductance': False, 'multi_layer_pin_moving': False, 'signal_net_accuracy': 10, 'use_predefined_res': False,
'bump_blob_detect_distance': 0.0, 'enable_full_length_inductance': True, 'non_color_geometry_handling_method': 0, 'skip_outline_smoothing': False, 'use_serial_open_detector': False,
'bump_blob_detect_method': 'circuit', 'enable_line_end_etching': True, 'non_color_geometry_reporting_size': 10, 'skip_pg_pin_cap': False, 'use_signal_decouple_mode': True,
'bump_rect_aspect_ratio_limit': 2.0, 'enable_merge_clean_layers': True, 'nonmanhattan_clean_method': 3, 'skip_pin_resistance': 0, 'via_chopping_distance': {'*': 0.5},
'check_dnets': False, 'enable_new_extractor': True, 'num_reduction_pass': 2, 'skip_reduction_layers': None, 'via_clustering_max_col_cuts': 1000,
'chop_shadow_vias': False, 'enable_new_scanline': True, 'offset_stack_via_snap_is_overlap': True, 'skip_signal_pin_cap': False, 'via_clustering_max_cuts_per_small_via': 2,
'chop_single_long_cut_via_only': False, 'enable_offset_stack_via_snap': False, 'offset_stack_via_snap_ratio': 3, 'sliver_aspect_ratio': 8.0, 'via_clustering_max_distance': {'*': 0.0},
'circuit_pruning_level': 2, 'enable_pruning_for_shadows': False, 'open_detector_method': 2, 'sliver_intersect_threshold': 0.7, 'via_clustering_max_row_cuts': 1000,
'clean_manhattan_rating_method': 'V1', 'enable_reduction_for_pi_model': True, 'overunder_for_smoothing': False, 'snap_to_45_threshold': 0.005, 'via_clustering_min_metal_width': 0.0,
'clean_polygon_flow': 'V2', 'enable_tsv_coupling_cap': False, 'parallel_spef_parsing_chunk_size': 1000, 'spef_instantiation_chunk_size': -1, 'via_clustering_min_small_via_count': 5000,
'clean_property_merge_mode': 'UsePriority', 'enable_via_clustering': 'off', 'parallel_spef_parsing_threshold': 5000, 'spef_stamper_group_size': 10, 'via_squashing_threshold': None,
'clean_range_query_mode': 'RTreeStar', 'extract_dangling': True, 'pi_model_large_net_threshold': 1024, 'split_power_gate_arcs': True, 'zero_shadow_via_layers': None}
'clean_sliver_remove_mode': 'AspectRatio', 'extract_pg_net_only': False, 'pin_moving_distance_to_via_chopping_ratio': 0.2, 'split_via_cells_by_surround': {'*': 0.0},
'cpm_reduction': False, 'extract_shield_traps': False, 'pin_reduce_chop_res': 0.0, 'spr_group_scheme': '4x4:0',
'cpm_reduction_multi_layer_pin_moving': True, 'extract_sliver_long_edge_only': True, 'pin_short_res': 1.0, 'spr_power_gate_pin_resistance': -1.0,
'cpm_reduction_pin_short_res': 1000000.0, 'extract_virtual_pin': False, 'power_net_accuracy': 100, 'spr_trace_through_subnet_bump': False,
'cpm_reduction_power_net_reduction_error_in_sec': 1e-09, 'force_top_metal_clean_direction': 'UNKNOWN', 'power_net_reduction_error_in_secs': 1e-12, 'stair_node_distance': 5.0,
'cpm_reduction_res_pruning_abs_threshold': 0.001, 'histogram_num_bins': 512, 'power_net_reduction_level': 3, 'stair_node_distance_eco': 2.0,
'cpm_reduction_res_pruning_rel_threshold': 0.001, 'histogram_num_bins_map_factor': 10, 'pseudo_via_for_covertical_layer': True, 'store_coupling_cap': False,
'cpm_reduction_squashing_layer_thresholds': {'*': 5e-09}, 'ignore_lef_mask_color': False, 'quick_estimate_pi_model': False, 'store_dnets': False,
'cpm_reduction_use_decap_pin_as_regular': True, 'include_ron_in_spr': False, 'recognize_bridge_via': True, 'store_load_cap': True,
'cross_metal_via_merging_max_col_cuts': 20, 'inductance_resistance_ratio_threshold': 1e-13, 'record_signal_net_shorts': False, 'thickness_variation_range': None,
'cross_metal_via_merging_max_distances': {'*': 2.5}, 'internal_tweaks': XTExtractTweaks(1e-15, 0.15, 1, 0, 'redhawk_compatible_mode': False, 'top_via_chopping_distance': 0.0,
'cross_metal_via_merging_max_row_cuts': 20, 100000, 2, 67900012, 0), 'reduce_top_layer_circuit': False, 'trace_and_connect_mask': True,
'cross_metal_via_merging_max_spacing_ratio': 5, 'long_cut_via_chopping_distance': {}, 'reduction_keep_via_stack': False, 'track_net_shorts': True,
'debug_lee': False, 'mark_bump_pin_shapes_in_cleaner': False, 'reduction_num_creep_nodes': 0, 'treat_pgfill_as_mfill': False,
'delete_single_pin_with_phantom': False, 'mark_cmm_shapes': False, 'reduction_res_pruning_threshold': None, 'treat_sadp_as_mfill': True,
'density_limits': None, 'mark_fingers': True, 'rel_clean_tolerance': 0.001, 'trifling_trap_size_threshold': 0.0003,
'density_tile_size': (0.0, 0.0), 'mark_power_gate_pin': True, 'relax_shadow_pin_moving': True, 'trim_slivers': True,
'density_tile_step_size': (0.0, 0.0), 'max_inductance_distribution_length': 5.0, 'resistance_inductance_ratio_threshhold': 10000000000000.0, 'trim_slivers_by_area': False,
'drop_non_bottom_pins': False, 'max_num_shell_nodes': 0, 'resistance_only': False, 'trim_slivers_try_limit': 2,

Making sure how was set each Options’ option (layout option)
>>> gp_dict(options['layout_options'].options_) 'enable_focus_pg_nets_v2': True, 'max_times_default_layer_cut_thickness ': 200, 'regrouping_factor_for_xt_part_to_instance_map': 0,
{'abs_clean_tolerance': 0.0001, 'enable_instance_checksum': True, 'max_trap_length': 0.0, 'rel_clean_tolerance': 0.001,
'auto_bump_distance': 100.0, 'enable_net_to_partition': True, 'merge_cmm_pins_to_master': False, 'remove_backslash': True,
'auto_rename_sub_nets': 'CmmOnly', 'enable_netlist_partition': True, 'merge_lefs': False, 'report_eco_shorts': False,
'bumps_at_top_def_hier_only': True, 'enable_power_gates': True, 'min_net_chunk_size': 10000.0, 'scope_def_via_names': True,
'bumps_at_top_def_layer_only': False, 'enable_via_reformation_from_obs ': False, 'min_num_netlist_partitions': 1, 'shadow_max_via_compress_distance': 20.0,
'cell_phantom_mode': 'AllBottom', 'enable_worker_deps_for_def_flattening': True, 'min_trap_length': 0.0, 'shadow_via_compress_cut_limit': (100, 100),
'cell_phantom_size': 0.02, 'explode_cell_names': None, 'name_context_cache_size': 5120.0, 'short_report_level': 1,
'chop_pin_extra': 1, 'finger_detection_method': 2, 'net_chunk_size': 50000.0, 'site_modifies_cell': False,
'clean_manhattan_rating_method': 'V1', 'focus_on_pg_nets': [], 'netlist_partition_ratio': 0.05, 'site_rotation_follows_cell_size': True,
'clean_polygon_flow': 'V2', 'force_equal_partitions': 0, 'num_cells_per_build_instance_graph_job': 0, 'skip_delete_cells': '',
'clean_property_merge_mode': 'UsePriority', 'force_num_xt_parts': -1, 'num_cmm_clone_pin_groups': 100, 'skip_dummy_nets': None,
'clean_range_query_mode': 'RTreeStar', 'force_top_metal_clean_direction': 'UNKNOWN', 'num_net_chunks': 0, 'slab_limit_ratio': 0.1,
'clean_sliver_remove_mode': 'AspectRatio', 'force_voltage_source_on_missing': True, 'num_xt_part_multiplier': 1.0, 'sliver_aspect_ratio': 8.0,
'cleaner_follows_dominant_direction': 1, 'force_xt_partitions': '', 'obs_via_forming_size_ratio': 5.0, 'sliver_intersect_threshold': 0.7,
'cleaner_use_lef_preferred_direction': True, 'global_bus_delimiter': '', 'overunder_for_smoothing': False, 'snap_to_45_threshold': 0.005,
'cmm_def_promotion_geom_threshold': 0, 'group_cmm_clone_pins': True, 'package_end_time_for_repeat_pwl': 1e-06, 'spice_case_sensitive': True,
'connect_fill_layers': '', 'honor_shadow_lef_size': False, 'package_max_edges_for_coords': 0, 'split_high_res_for_package': -1.0,
'controlled_sources_nortan_resistance': 1e-06, 'ignore_macro_eeq': False, 'partition_cut_thickness': 1.0, 'staircase_cut_direction': 'horizontal',
'convert_to_staircase': False, 'ignore_maskshift_error': False, 'partition_method': 1, 'staircase_interval': 0.2,
'cover_bump_cells': None, 'ignore_package_coupling_elements': False, 'partition_pin_count': 150000, 'std_cell_size_multiplier': 1.0,
'create_phantoms_for_filler_cell': True, 'ignore_polygons': 0, 'partition_pratio_data': False, 'strict_liberty_sanity_check': False,
'create_pin_service_for_fake_cells': False, 'instance_chunk_size': 1000000, 'partition_shape_count': 25000, 'top_layer_effective_distance': 0.0,
'create_pin_service_for_fake_cells_in_parallel': True, 'large_conn_net_threshold': 1000, 'per_ds_file_cmm_rhgds_cells': 1, 'trace_and_connect_mask': True,
'degrading_def_cell_max_shape_count': 1000, 'macro_phantom_distance': 20.0, 'pin_density_weight_for_partition': 0.7, 'trim_slivers': True,
'degrading_def_cell_min_instance_count': 1000, 'mark_fingers': True, 'power_gate_arc_detection_mode': 'ConnectNearest', 'trim_slivers_by_area': False,
'density_window_width': 50.0, 'mark_power_gate_pin': True, 'power_gate_cell_phantom_mode': 'AllBottom', 'trim_slivers_try_limit': 2,
'detailed_phantom_for_promoted_cmm': False, 'max_flatten_jobs': 0, 'power_gate_values_from_apl_on_state': True, 'unidirectional_pin_current_layer': None,
'di_check': True, 'max_instance_count_per_netlist_partition': 10000000, 'ppi_cell_edge_max_threshold': 50.0, 'use_dynamic_cut_thickness': True,
'disable_component_maskshift_sanitycheck': False, 'max_length_to_min_width_ratio': 100.0, 'ppi_cell_edge_relative_threshold': 1.0, 'use_flat_netlist_stream_ds': False,
'drop_def_trimmetal': ['*_TRIMMETAL_FILLS_RESERVED '], 'max_num_netlist_partitions': 900, 'propose_num_netlist_partitions': 0, 'use_stream_ds_file': True,
'drop_tie_down_phantoms': True, 'max_num_xt_parts': 100000, 'push_pg_pininst': None, 'use_via_location_for_phantom': True,
'effective_distance': 4.0, 'max_partition_ratio': 0.0, 'ratio_to_error_cell_pin_sanity_check': 0.1, 'via_surround_flatten': 1,
'enable_component_maskshift': False, 'max_phantom_distance': 15.0, 'read_fill_layers': 1, 'wildcard_connection_expansion_mode': 'Auto',
'enable_controlled_sources': True, 'max_phantom_distance_power_gate': 0.0, 'record_macro_pins': True, 'xt_to_pp_ratio': 30}

Making sure how was set each Options’ option (scenario option)
>>> gp_dict(options['scenario_options'].options_) 'gate_delay_scale': 1.0, 'tw_use_sta_clock_domain': False,
{'allow_icg_enable_to_switch': 0, 'generate_peak_current_container': False, 'tw_use_sta_const': True,
'apl_firing_time_interpolation_policy': 'Method4FiringOnly', 'glitch_eater_multiplier': 1.0, 'use_cached_nlpm_calc': False,
'apl_interpolation_policy': 'Method4', 'include_propagated_input_events_for_sequential': False, 'use_gate_vcd_frequencies': True,
'apl_voltages_selection_thresholds': (0.8, 1.1), 'infer_icg_enable_signals_from_fanin_prop': True, 'use_gate_vcd_on_icgs': True,
'apply_gate_vcd_to_clock_nets': True, 'infer_icg_enable_signals_from_rtl_vcd': False, 'use_gen_src': True,
'apply_gate_vcd_to_data_nets': True, 'internal_tweaks': SMScenarioTweaksPickler('22 'use_net_delay': False,
'apply_pratio_distribution': True, serialization::archive 13 0 0 0 0 1 9.999999776e-03 'use_pg_arcs_in_csg': True,
'apply_rtl_vcd_to_all_instances': False, 1.000000047e-03 1 9.999999776e-03 1.000000047e-03|n'), 'use_pi_model': True,
'assign_cell_leakage_to_primary_power': False, 'is_activity_profile_run': False, 'use_power_gate_logic_signal': True,
'is_pcvs_base_run': False, 'use_tick_vcd_at_clock_source': False,
'base_scenario_duration_for_target_power_settings': None,
'ccs_power_current_includes_leakage': True, 'legacy_mode': 0, 'use_timed_vcd_at_clock_source': False,
'cell_types_with_independent_nlpm': [], 'legacy_mode_for_avg_power': 0, 'vcd_overrides_lso': False,
'local_ground_current_scaling': 0, 'vcd_replay_experiment': False,
'clock_cycle_mode': 'Adaptive',
'clocks_never_die': False, 'macro_apl_pin_based_current_characterization': True, 'vcd_roll_over_policy': False,
'correlation_mode': '', 'macro_demand_current_restart': False, 'vcv_v2': False,
'macro_demand_current_restart_from_leakage': True, 'zero_delay_vcd_order_clock_event_first': {'macro': False,
'create_heatmaps': True,
'cs_generation_mode': 'Default', 'macro_use_input_states': True, 'sequential': False}}
'debug_vcv': False, 'macro_when_behavior': 'always',
'max_cycles_of_dominant_clock': 20,
'demand_current_restart': True,
'dirty_data_init_mode': 0, 'max_num_points_in_total_demand': 1000000,
'dominant_clock_period': -1.0, 'max_time_resolution_seconds_in_total_demand': 1e-12,
'max_voltage_samples': 5,
'enable_duration_based_compute_dc_average': True,
'enable_events_for_scan_out_pins': True, 'memory_use_avm_waveform': True,
'enforce_all_icg_on': False, 'min_cycles_of_dominant_clock': 1,
'min_instance_coverage_for_sim_time': 99.0,
'event_time_precedence_honor_cycle': True,
'multi_voltage_demand_current': False,
'experiment1': False,
'force_arc_delay': -1.0, 'nlpm_base_mult': 2.0,
'nlpm_use_level': 2,
'force_clock_propagation': False,
'no_instance_events': 0,
'force_cs': 'liberty',
'force_load_cap': -1.0, 'npv_leakage_for_physical_instances': False,
'npv_rise_init_probability': 0.5,
'force_lso_propagation': False,
'npv_seq_cell_fit_in_cycle': True,
'force_lso_propagation_mode': 'preserve_logic',
'force_pin_slew': -1.0, 'npv_switching_time_policy': 'early_edge',
'functional_current_scales': None, 'num_digits_in_templates': 3,
'num_lcps': 1,

Making sure how was set each Options’ option (VCV option)
>>> gp_dict(options['value_change_options'].options_)
{'debug_mode': 'None',
'disable_all_auto_mapping': False,
'disable_exact_auto_mapping': False,
'disable_pin_namemapping': False,
'enable_default_rtl_namemapping_rules': True,
'enable_pin_namemapping': False,
'fuzzy_chars': '/_[]',
'multi_bit_delimiters': [],
'multi_bit_prefixes': [],
'name_mapper': 'MultiBitMapping',
'num_fsdb_api_threads': 2,
'signal_based_chunks': 1,
'store_xp_based_data': False,
'time_based_chunks': 1,
'use_first_event_as_initial_level': True,
'use_vcv_name_map': False,
'vcd_x_logic_state': None}

Making sure how was set each Options’ option (grm option)
rm_options'].options_) 'decap_max_cap': 0.001, 'force_load_cap': -1.0, 'linv_sparsification_ratio': 0.75, 'min_xt_to_pp_ratio': 20, 'pp_shape_aspect_ratio_factor': 1.5
onvergence_threshold': 0.05,'decap_max_res': 1000000000.0, 'force_num_pp_parts': 0, 'linv_sparsification_threshold': 1e-07, 'norton_res': 1e-06, 'pp_to_xt': None,
'decap_min_cap': 1e-20, 'force_power_gate_r_off': -1.0, 'linv_sparsification_threshold_max': 0.0001, 'num_bump_groups': -1, 'probe_decap_cell_pins': False,
rue, 'decap_min_res': 1e-06, 'force_power_gate_r_on': -1.0, 'log_reporting_interval_percent': 0.05, 'num_moments': 12, 'probe_filler_cell_pins': False,
se, 'decap_mode': 'scale_toggle', 'ground_rmodel_grid_cap': False, 'matrix_dump_file_prefix': 'matrix_dump', 'num_poles': 4, 'probe_rollup_instance_pins': False,
tep_increment': 200, 'decap_model_mode': 1, 'grounding_r': 1000000000.0, 'matrix_dump_part_id': -1, 'num_pp_factor': 1.0, 'probe_shadow_cell_pins': False,
e': {}, 'decap_r_driver_estimation_v1': False, 'histogram_num_bins': 512, 'matrix_min_nnz_per_part': 1000, 'num_xt_partitions_per_overlap_for_s 'pseudo_dc_max_iterations': 10,
': 1.0, 'decap_r_driver_scale': 1.0, 'histogram_num_bins_map_factor': 10, 'matrix_partitioning_options': 1, imulation': 2, 'push_down_subnet_ploc_voltages'
ce': False, 'default_power_gate_r_off': 10000000.0, 'incremental_solve_max_diff_threshold': 0.0001, 'matrix_reduction_level': 3, 'num_xt_partitions_per_simulation_pa 'ramp_up_dc_level_factor': -1.0,
_to_pwl': 'Rollup', 'default_power_gate_r_on': 100.0, 'inductor_analysis_method': 0, 'max_book_threads': 1, rtition': 9, 'ramp_up_net_dc_level': {},
'off_state_gate_resistor': -1.0, 'ramp_up_nl_r_mult': 1.0,
'demand_current_random_shift': 0.0, 'integration_method': 0, 'max_check_level': -1,
'demand_current_random_shift_templates': False,'iteration_convergence_current_check': True, 'max_check_steps': 5, 'optimize_rollup_decap_rc': True, 'remove_disconnected_arc_demand
equency': 200000000.0, 'demand_current_shift_limit': 5e-09, 'iteration_convergence_threshold': 0.001, 'max_iter_count': 250, 'package_bump_stitch_radius': 0.1, 'rescalc_group_currents': True,
e, 'elt_multiplier': {}, 'iteration_convergence_threshold_current_abs_change': 1e-08, 'max_iter_count_dc': 250, 'package_sim_mode': 'Auto', 'rescalc_num_groups': 1,
False, 'elt_multiplier_for_package': {}, 'iteration_convergence_threshold_current_abs_change_dc': 1e-08, 'max_iter_count_vcheck': 50, 'partition_dimensions': '5x5:1', 'rmodel_border_mode': 'all',
'enable_balanced_currents': False, 'iteration_convergence_threshold_current_rel_change': 0.002, 'max_load_cap_scale_for_toggle': 1.0, 'partition_factorization_factor': 1.7, 'rmodel_bump_count': 10,
'enable_cpm_r': False, 'iteration_convergence_threshold_current_rel_change_dc': 0.0001, 'max_node_voltage': 1000000.0, 'partition_method': 11, 'rmodel_count': 9,
ne, 'enable_dc_current_adjustment': True, 'iteration_convergence_threshold_dc': 0.01, 'max_num_cycles_in_stats': 128, 'partition_node_cost_factor_v6': 1.0, 'rmodel_coupling_circuit_mode': 'cr
, 'enable_high_capacity_package_simulation': True, 'iteration_convergence_threshold_dc_current_abs_diff': 0.01, 'max_num_points_in_total_demand': 1000000, 'partition_pin_cost_factor': 0.0, 'rmodel_default_inductance': 0.0,
'enable_legacy_update': False, 'iteration_convergence_threshold_dc_current_rel_diff': 0.005, 'max_ppn_balancing_refinement_iters': 100, 'partition_pin_cost_factor_v6': 0.0, 'rmodel_intrinsic_cap_scale': 1.0,
e, 'enable_pin_count_decap': True, 'iteration_convergence_threshold_local': 0.01, 'max_rhs_current': 10000000000.0, 'partition_resistor_cost_factor_v6': 0.0, 'rmodel_large_resistance': 0.0,
'partition_weight_method': 1, 'rmodel_layer_depth': 2,
e, 'enable_ppn_to_worker_load_balancing': True, 'iteration_convergence_threshold_local_dc': 0.01, 'max_sleep_for_sim_lock': 10.0,
'enable_rmodel_bump_current_adjustment': True,'iteration_convergence_threshold_local_max_rel_diff': inf, 'max_sliding_window_time_step': 0, 'partition_weight_mode': 2, 'rmodel_load_cap_scale': 1.0,
sim_perc': 0.99, 'enable_rmodel_coupled_mode': False, 'iteration_convergence_threshold_local_spool': 0.001, 'max_solver_preparation_threads': 1, 'pin_cap_policy': 'max', 'rmodel_load_count': 0,
sim_time': 0.0, 'enable_rmodel_inductance': False, 'iteration_convergence_threshold_max_diff': 0.0003, 'max_solver_threads': 1, 'pin_count_factor_for_load_balancing' 'rmodel_max_inductance': 1e-09,
: 2.5,
time': None, 'enable_start_from': False, 'iteration_convergence_threshold_max_diff_ratio': 0.1, 'max_sparse_l_density': 0.2, 'rmodel_max_resistance': 1000000.0
'power_gate_pin_resistance': -1.0,
'estimate_mem_usage_method': 0, 'iteration_convergence_threshold_spool': 0.001, 'max_time_resolution_seconds_in_total_demand': 1e-12, 'rmodel_merge_resistance': 0.0,
'power_partition_snap_points': [1, 1, 1,
, 'expected_factor_nnz_per_ppn': 750000000.0, 'iteration_convergence_threshold_spool_current_abs': 0.001, 'max_voltage_derate_ratio': 0.307, 'rmodel_min_edge_ratio': 0.0001,
1, 5, 5, 8, 8, 8, 8, 8, 16, 16, 16, 16, 16],
'expected_max_nodes_per_ppn': 200000000, 'iteration_convergence_threshold_spool_current_rel': 0.005, 'max_xt_to_pp_ratio': 100, 'rmodel_min_inductance': 0.0,
'power_partition_strategy':
'expected_nodes_ppn': 20000000, 'iteration_convergence_threshold_total_bump_current_abs_change': 1e-08, 'memory_allowed_per_partition': 8192.0, [(50000000.0, 1), 'rmodel_mode': 'admittance',
': 1.0, 'expected_pin_ppn': 10000000, 'iteration_convergence_threshold_total_bump_current_abs_change_dc': 0.0, 'min_iter_count': 1, (150400000.0, 5), (411000000000.0, 500), 'rmodel_pg_route_cap_scale': 1.0,
'EffectiveDvD', 'expected_resistor_ppn': 15000000, 'iteration_convergence_threshold_total_bump_current_rel_change': 0.002, 'min_iter_count_dc': 1, (1900000000.0, 20), (882700000000.0, 700), 'rmodel_resistance': 0.1,
(10400000000.0, 25), (5009200000000.0, 800),
'factor_nnz_exponent': 1.2, 'iteration_convergence_threshold_total_bump_current_rel_change_dc': 0.0, 'min_iter_count_spool_dc': 1, (18600000000.0, 30), (6083000000000.0, 900), 'rmodel_rl_scale': 1000000000.0,
ckage': 0.0, 'factor_nnz_exponent_max': 1.35, 'iteration_convergence_voltage_check': True, 'min_iter_count_spool_tr': 1, (25100000000.0, 64), (7197700000000.0, 1000), 'rmodel_snap_threshold': 0.1,
.0, 'factor_nnz_exponent_min': 1.1, 'keep_stamped_currents': False, 'min_load_cap_scale_for_toggle': 0.0, (34200000000.0, 70), (8349200000000.0, 1200), 'rmodel_tiny_resistance': 0.001,
(96800000000.0, 200), (9534500000000.0aa, 1400),
fo': None, 'factorization_precision': 'double', 'keep_time_range_for_switching_instances': True, 'min_res': 0.0001, (115300000000.0, 220), (22834700000000.0, 2200),
': 1.0, 'fail_threshold_for_disconnected_ratio': 0.95, 'keep_used_demand_currents': False, 'min_res_for_package': 1e-06, (168400000000.0, 255), (72443600000000.0, 4400)],
(222600000000.0, 300),
: 1.0, 'force_bad_package_spice': False, 'linsol_default_debug_level': 20, 'min_sleep_for_sim_lock': 2.0,

(simulation &
Making sure how was set each Options’ option power option)
>>> gp_dict(options['simulation_options'].options_) 'package_end_time_for_repeat_pwl': 1e-06, >>> gp_dict(options['power_options'].options_)
{'apply_reduction_inverse_map': True, 'package_max_edges_for_coords': 0, {'apl_interpolation_policy': 'Method4',
'controlled_sources_nortan_resistance': 1e-06, 'pin_reduce_chop_res': 0.0, 'assign_cell_leakage_to_primary_power': False,
'cpm_reduction': False, 'power_gate_pin_resistance': -1.0, 'independent_input_internal_power': False,
'cpm_reduction_multi_layer_pin_moving': True, 'power_net_reduction_error_in_secs': 1e-12, 'parse_chunk_size': 512,
'cpm_reduction_pin_short_res': 1000000.0, 'power_net_reduction_level': 3, 'pin_cap_policy': 'max',
'cpm_reduction_power_net_reduction_error_in_sec': 1e-09, 'reduce_top_layer_circuit': True, 'use_pi_model': True}
'cpm_reduction_res_pruning_abs_threshold': 0.001, 'reduction_keep_via_stack': False,
'cpm_reduction_res_pruning_rel_threshold': 0.001, 'reduction_num_creep_nodes': 0,
'cpm_reduction_squashing_layer_thresholds': {'*': 5e-09}, 'reduction_res_pruning_threshold': None,
'cpm_reduction_use_decap_pin_as_regular': True, 'relax_shadow_pin_moving': True,
'cross_metal_via_merging_max_col_cuts': 20, 'short_res_subnet_bumps_no_package': -1.0,
'cross_metal_via_merging_max_distances': {'*': 2.5}, 'skip_reduction_layers': None,
'cross_metal_via_merging_max_row_cuts': 20, 'spice_case_sensitive': True,
'cross_metal_via_merging_max_spacing_ratio': 5, 'split_high_res_for_package': -1.0,
'drop_non_bottom_pins': False, 'use_decap_pin_as_regular': False,
'enable_controlled_sources': True, 'via_squashing_threshold': None,
'enable_cross_metal_via_merging': False, 'zero_shadow_via_layers': None}
'enable_reduced_em_flow': False,
'enable_reduction': True,
'ignore_package_coupling_elements': False,
'max_num_shell_nodes': 0,
'max_num_shell_nodes_borders': 0,
'multi_layer_pin_moving': False,
'num_reduction_pass': 2,
'num_xts_factor_nnz_stats': 10,

(value_change &
Making sure how was set each Options’ option switching_activity
>>> gp_dict(options['value_change_options'].options_) option)
{'debug': False,
>>> gp_dict(options['switching_activity_options'].options_)
'debug_mode': 'None',
{'annotate_net_in_saif': False,
'disable_pin_namemapping': False,
'derate_sequential_output_pin_toggle_rate_by_clock': True,
'enable_default_rtl_namemapping_rules': True,
'enable_port_saif': True,
'enable_pin_namemapping': False,
'slices_per_ds': 100,
'fuzzy_chars': '/_[]',
'tw_use_sta_const': True,
'multi_bit_delimiters': [],
'vcd_roll_over_policy': False}
'multi_bit_prefixes': [],
'name_mapper': 'MultiBitMapping',
'num_fsdb_api_threads': 2,
'signal_based_chunks': 1,
'streaming_flush_data': False,
'time_based_chunks': 1,
'use_first_event_as_initial_level': True,
'use_uniform_signal_chunk': False,
'use_vcv_name_map': False,
'var_limit_for_flush': 100000,
'vcd_x_logic_state': None,
'vcv_new': True}

Making sure how was set each Options’ option (analysis option)
>>> gp_dict(options['analysis_options'].options_) 'pp_shape_aspect_ratio_facto r': 1.5, 'skip_load_caps_in_decap_gen erati
{'adaptive_iteration_conv ergenc e_th reshold': 0.05, 'enable_rmodel_inductance' : False, 'iteration_convergence_threshold_spool_current _abs': 0.001, 'min_iter_count': 1, 'pp_to_xt': None, 'snap_hh_step_multiplier': 1.0,
'apl_decap_v1': False, 'enable_start_from': False, 'iteration_convergence_threshold_spool_current _rel' : 0.005, 'min_iter_count_dc': 1, 'probe_decap_cell_pins': False, 'snap_instance_current_peaks_only
'avg_dc_correction': True, 'estimate_mem_usage_method' : 0, 'iteration_convergence_threshold_tot al _bump_current _abs_change': 1e-08, 'min_iter_count_spool_dc': 1, 'probe_filler_cell_pins': False, 'snap_instance_currents': 0.0,
'avg_dc_override': False, 'expected_factor_nnz_per_ppn': 750000000.0, 'iteration_convergence_threshold_tot al _bump_current _abs_change_dc': 0.0, 'min_iter_count_spool_tr': 1, 'probe_rollup_instance_pins': False, 'solver_conserve_memo ry': False,
'bookkeep_combine_step_increment': 200, 'expected_max_nodes_per_ppn': 200000000, 'iteration_convergence_threshold_tot al _bump_current _rel _change' : 0.002, 'min_load_cap_scale_for_toggle' : 0.0, 'probe_shadow_cell_pins': False, 'solver_enable_increment al_dc' : 1
'bump_group_override': {}, 'expected_nodes_ppn': 20000000, 'iteration_convergence_threshold_tot al _bump_current _rel _change_dc': 0.0, 'min_res': 0.0001, 'pseudo_dc_max_iterations': 10, 'solver_reduction_type': 1,
'bump_sparsity_factor': 1.0, 'expected_pin_ppn': 10000000, 'iteration_convergence_volt age_ch eck' : True, 'min_res_for_package' : 1e-06, 'push_down_subnet_ploc_voltages': True, 'solver_temp_dir': '',
'check_dc_convergence': False, 'expected_resistor_ppn': 15000000, 'keep_stamped_currents': False, 'min_sleep_for_sim_lock': 2.0, 'ramp_up_dc_level_fac tor': -1.0, 'solver_type': 'Ebu',
'convert_pin_sources_to_pwl': 'Rollup', 'factor_nnz_exponent': 1.2, 'keep_time_range_fo r_s witching_instanc es': True, 'min_xt_to_pp_ratio': 20, 'ramp_up_net_dc_lev el': {}, 'solver_type_fallback': 'None',
'cpm_decap_rollup_frequency': 200000000.0, 'factor_nnz_exponent_max': 1.35, 'keep_used_demand_currents': False, 'norton_res': 1e-06, 'ramp_up_nl_r_mult': 1.0, 'solver_work_dir': 'solver_work',
'current_source_scale': 1.0, 'factor_nnz_exponent_min': 1.1, 'linsol_default_debug_level' : 20, 'num_bump_groups': -1, 'remove_disconnected_arc _demand': False, 'split_waveforms_to_xps': True,
'cycle_stats_method': 'EffectiveDvD', 'factorization_precision': 'auto', 'linv_sparsification_ratio': 0.75, 'num_pp_factor': 1.0, 'rescalc_group_currents': True, 'spool_elongation_sparsification_th
'dc_time_step': 0.0, 'fail_threshold_for_disconnected_ratio': 0.95, 'linv_sparsification_threshold': 1e-07, 'num_xt _part itions_p er_overlap _for_simul ation': 2, 'rescalc_num_groups': 1, 1e-08,
'dc_time_step_for_package' : 0.0, 'force_bad_package_spice' : False, 'linv_sparsification_threshold_max': 0.0001, 'num_xt_partitions_per_simulation_p artit ion': 9, 'rmodel_border_mode': 'all', 'ssor_factor': 1.0,
'decap_cload_scale': 1.0, 'force_load_cap': -1.0, 'log_reporting_interval _p erc ent': 0.05, 'off_state_gate_resistor' : -1.0, 'rmodel_bump_count': 10, 'ssor_factor_dc': 1.0,
'decap_external_rh_info' : None, 'force_num_pp_parts': 0, 'matrix_dump_file_prefix' : 'matrix_dump', 'optimize_rollup_decap_rc': True, 'rmodel_count': 9, 'stamp_current_method': 0,
'decap_intr_cap_scale': 1.0, 'force_power_gate_r_off': -1.0, 'matrix_dump_part_id': -1, 'package_bump_stitch_radius': 0.1, 'rmodel_coupling_circuit_mode' : 'cross', 'stamp_intrinsic_decaps': 1,
'decap_intr_res_scale': 1.0, 'force_power_gate_r_on': -1.0, 'matrix_min_nnz_per_part': 1000, 'package_sim_mode': 'Auto', 'rmodel_default_inductance': 0.0, 'stamp_non_rmodel_ppn_currents':
'decap_max_cap': 0.001, 'ground_rmodel_grid_cap': False, 'matrix_partitioning_options': 1, 'partition_dimensions': '5x5:1', 'rmodel_intrinsic_cap_scale' : 1.0, 'stitch_res': 0.0001,
'decap_max_res': 1000000000.0, 'grounding_r': 1000000000.0, 'matrix_reduction_level': 3, 'partition_factorization_factor': 1.7, 'rmodel_large_resistance' : 0.0, 'switching_instance_decap_scale' :
'decap_min_cap': 1e-20, 'histogram_num_bins': 512, 'max_book_threads': 1, 'partition_method': 11, 'rmodel_layer_depth': 2, 'transient_voltage_compression_de
'decap_min_res': 1e-06, 'histogram_num_bins_map_factor' : 10, 'max_check_level': -1, 'partition_node_cost_factor_v6': 1.0, 'rmodel_load_cap_scale' : 1.0, 'use_delay_stats_for_pin_volt ages':
'decap_mode': 'scale_toggle', 'incremental_solve_max_diff _threshold': 0.0001, 'max_check_steps': 5, 'partition_pin_cost_factor': 0.0, 'rmodel_load_count': 0, 'use_voltage_shift': True,
'decap_model_mode': 1, 'inductor_analysis_method': 0, 'max_iter_count': 250, 'partition_pin_cost_factor_v6': 0.0, 'rmodel_max_inductance': 1e-09, 'voltage_derate_bl end': 1.0,
'decap_r_driver_esti mat ion_v1': False, 'integration_method': 0, 'max_iter_count_dc': 250, 'partition_resistor_cost_factor_v6': 0.0, 'rmodel_max_resistance' : 1000000.0, 'voltage_derate_fo r_rmod el': True,
'decap_r_driver_scal e': 1.0, 'iteration_convergence_current _check' : True, 'max_iter_count_vcheck': 50, 'partition_weight_method': 1, 'rmodel_merge_resistanc e': 0.0, 'voltage_derate_method': 'Off',
'default_power_gate_r_off': 10000000.0, 'iteration_convergence_threshold': 0.01, 'max_load_cap_scale_fo r_to ggl e': 1.0, 'partition_weight_mode' : 2, 'rmodel_min_edge_rat io': 0.0001, 'voltage_derate_us e_arc _volt age':
'default_power_gate_r_on': 100.0, 'iteration_convergence_threshold_current _abs_ch ange': 1e-08, 'max_node_voltage': 1000000.0, 'pin_cap_policy': 'max', 'rmodel_min_inductance': 0.0, 'waveform_compress_initi al_max' :
'demand_current_random_shift': 0.0, 'iteration_convergence_threshold_current _abs_ch ange_dc' : 1e-08, 'max_num_cycles_in_stats': 128, 'pin_count_factor_for_load_balancin g': 2.5, 'rmodel_mode': 'admittance', 'xt_to_neighbors': None,
'demand_current_random_shift _templates': False, 'iteration_convergence_threshold_current _rel _change': 0.002, 'max_num_points_in_total_d emand': 1000000, 'power_gate_pin_resistanc e': -1.0, 'rmodel_pg_route_cap _scal e': 1.0, 'xt_to_pp': None}
'demand_current_shift_limit' : 5e-09, 'iteration_convergence_threshold_current _rel _change_dc' : 0.0001, 'max_ppn_balancing_refinement _it ers': 100, 'power_partition_snap_points': [1, 1, 1, 1, 5, 5, 8, 8, 'rmodel_resistance': 0.1,
'elt_multiplier': {}, 'iteration_convergence_threshold_dc': 0.01, 'max_rhs_current': 10000000000.0, 8, 8, 8, 16, 16, 16, 16, 16], 'rmodel_rl_scale': 1000000000.0,
'elt_multiplier_for_pac kage' : {}, 'iteration_convergence_threshold_dc_cu rrent_abs_diff': 0.01, 'max_sleep_for_sim_lock' : 10.0, 'power_partition_strategy': [(50000000.0, 1), 'rmodel_snap_threshold': 0.1,
'enable_balanced_currents' : False, 'iteration_convergence_threshold_dc_cu rrent_rel _diff': 0.005, 'max_sliding_window_time_st ep': 0, (150400000.0, 5), (411000000000.0, 500), 'rmodel_tiny_resistance': 0.001,
'enable_dc_current_adjustment': True, 'iteration_convergence_threshold_loc al': 0.01, 'max_solver_preparat ion_threads': 1, (1900000000.0, 20), (882700000000.0, 700), 'save_pp_ds': False,
'enable_high_capacity_pac kage_simul ation': True, 'iteration_convergence_threshold_loc al_dc' : 0.01, (10400000000.0, 25), (5009200000000.0, 800),
'max_solver_threads': 1, 'save_rlck_netlist': False,
(18600000000.0, 30), (6083000000000.0, 900),
'enable_legacy_updat e': False, 'iteration_convergence_threshold_loc al_max _rel _diff': inf, 'max_sparse_l_density': 0.2, 'save_rlck_prefactor_mat rix': False,
(25100000000.0, 64), (7197700000000.0, 1000),
'enable_pin_count_decap': True, 'iteration_convergence_threshold_loc al_spool' : 0.001, 'max_time_resolution_s econds_in_to tal _demand' : 1e-12, (34200000000.0, 70), (8349200000000.0, 1200), 'save_view_step_increment' : 1000,
'enable_ppn_to_worker_lo ad_b alancing' : True, 'iteration_convergence_threshold_max _diff': 0.0003, 'max_voltage_derate_ratio' : 0.307, (96800000000.0, 200), (9534500000000.0, 1400), 'scheduler_barrier': True,
'enable_rmodel_bump_current _adjust ment' : True, 'iteration_convergence_threshold_max _diff_ratio' : 0.1, 'max_xt_to_pp_ratio': 100, (115300000000.0, 220), (22834700000000.0, 2200),'simulate_system_response': False,
'enable_rmodel_coupled_mode' : False, 'iteration_convergence_threshold_spool': 0.001, (168400000000.0, 255), (72443600000000.0, 4400)],
'memory_allowed_p er_partition' : 8192.0, 'skip_load_caps_in_decap_gen eration': False,
(222600000000.0, 300),

Making sure how was set each Options’ option (multichip &
multichip_coupling
option)
>>> gp_dict(options['multichip_options'].options_)
{'cp_model_ranges': {'max_ind': 1000.0, 'max_r': 1000000.0, 'min_ind': 1e-15, 'min_r': 1e-06}}
>>> gp_dict(options['multichip_coupling_options'].options_)
{'coupling_layer_number': 1}

Making sure how was set each Options’ option (signal_net_current
option)
>>> gp_dict(options['signal_net_current_options'].options_)
{'current_heatmap_modes': ['default'],
'default_frequency': 1000000000.0,
'default_slew': 5e-11,
'default_toggle_rate': 0.2,
'default_voltage': 1.0,
'emsolver_options': {},
'histogram_num_bins': 512,
'histogram_num_bins_map_factor': 10,
'keep_debug_files': False,
'keep_lib_clock_pin': False,
'net_customizations': None,
'node_count_limit': 150000,
'pin_cap_policy': 'default',
'primary_output_pin_cap': None,
'remove_used_files': True,
'replicate_signal_net_data': False,
'scale_slew_to_full': False,
'short_pin_nodes': True,
'simulation_engine_mode': 2,
'temp_directory': None}

Making sure how was set each Options’ option (signal_net_current
option)
>>> gp_dict(options['signal_net_current_options'].options_)
{'current_heatmap_modes': ['default'],
'default_frequency': 1000000000.0,
'default_slew': 5e-11,
'default_toggle_rate': 0.2,
'default_voltage': 1.0,
'emsolver_options': {},
'histogram_num_bins': 512,
'histogram_num_bins_map_factor': 10,
'keep_debug_files': False,
'keep_lib_clock_pin': False,
'net_customizations': None,
'node_count_limit': 150000,
'pin_cap_policy': 'default',
'primary_output_pin_cap': None,
'remove_used_files': True,
'replicate_signal_net_data': False,
'scale_slew_to_full': False,
'short_pin_nodes': True,
'simulation_engine_mode': 2,
'temp_directory': None}

View (All the view listed) - 1
>>> help(SeaScapeDB)
FUNCTIONS
context_aware_em_check(pg_em_view, signal_em_view, em_threshold=50.0)
Performing context aware RMS EM analysis.
create_activity_profile_view(design_view, vcd_files, timing_window_files=None, sdc_files=None, rtl_namemap_files=None, bus_mode=False, physical_mode=False, top_n_cycles_for_density=100, num_x_tiles=10, num_y_tiles=10, voltage_levels=None, virtual_supplies=None,
supply_connection_rules=None, options=None, tag='fsdb_profile')
FSDB profiler.
create_analysis_combo_view(analysis_view, extra_analysis_views, time_shifts, tag='avc', options=None, step_size=None, duration=None)

Create an AnalysisComboView in this database.
create_analysis_view(simulation_view=None, scenario_views=None, tag='av', duration=None, step_size=None, options=None, start_from=None, keep_stats_level=None, ramp_up_nets=None, off_state_nets=None, repeat_simulation_time=None, initial_condition='avg_dc',
delay_simulation_start=None, current_type_for_dc=None, delay_stats=None, current_snap_method=None, enable_start_from=False, current_derate_mode=None, battery_levels=None, symmetric_repeat=None, simulate_system_response=False, scheduler_barrier=None)
Create an AnalysisView in this database.
create_chip_thermal_model(ev, scn=None, pwr=None, leakage_file='', leakage_factor={}, temperatures=[], resolution=10.0,ctm_output_directory='', chip_id=-1, tag='ctm_files')

Create CTM(chip thermal model) files.
create_chunked_data(tag='cd', save_to_db=True)
Create a ChunkedData object in this database.
create_chunked_dict(tag='cdd', save_to_db=True, max_hash_size=16384)

Create a ChunkedDict object in this database.
create_demand_current_view(db, timing_view=None, extract_view=None, external_parasitics=None, voltage_levels=None, options=None, tag='scn_curr', process_corner='default_process')

Create a view that contains all demand currents for all transitions.
create_design_view(lib_views=None, tag='dv', top_cell_name=None, lef_files=None, def_files=None, gds_files=None, external_instances=None, macro_views=None, phymodel_views=None, skip_nets=None, focus_pg_nets=None, options=None, stackup_file=None,
gds_layer_map_file=None, rename_pg_nets=None, tech_view=None, tech_layer_map_file=None, hdl_view=None, design_ecos=None, merge_clean_layers=None, lef_def_layer_map_file=None, scan_chain_data=None, default_tech_lef=None, custom_cell_phantoms=None)
Create a DesignView object in this database.
create_dynamic_power_view(timing_view, extract_view=None, external_parasitics=None, analysis_duration=None, time_interval_length=None, tag='dpwr', voltage_levels=None, temperature=25.0, disable_clocks=None, clock_source_toggle_rates=None, options=None,
activity_level=None, mode_definitions=None, instance_settings=None, gate_vcd_mode='off', prefer_gate_vcd_clock_period=True, rtl_vcd_mode='on', infer_icg_enable_signals_from_rtl_vcd=False, infer_icg_enable_signals_from_fanin_prop=False, zero_delay_mode=False,
process_corner='default_process', value_change_data=None, virtual_supplies=None, supply_connection_rules=None, transition_time_precedence=None, event_time_precedence=None, generate_instance_events_only=False, limit_net_cap_to_pin_max_cap=False,
include_input_only_events=True, calculation_settings=None, results_spec=None, default_input_pin_transition_time=1e-11)
Create a dynamic PowerView.
create_effective_resistance_view(simulation_view, select_settings=None, options=None, tag='reff')

Create reff view.
create_electromigration_view(analysis_view, tag='emv', mode='DC', temperature_em=None, delta_t_rms=None, thermal_view=None, context_factors=None, calculate_fit=False, temperature_fit=None, fit_life_time=None, fit_mode='basic', fit_tech_file=None,
em_ruleset_names=None, em_mission_factor=None, options=None, em_settings=None, fit_settings=None, create_fit_heatmap=True)
Create an ElectromigrationView in this database.

create_explorer_view(dbs=None, views=None, timing_view=None, extract_views=[], tag='xv', missing_via_user_views=[], enable_die=True, enable_dwe=False, enable_hse=False, enable_gui=False)
Prepare data for RedHawk-SC Explorer.
create_extract_view(design_view, tech_view, tag='ev', mode='pg', tech_layer_map_file=None, temperature=None, calculate_spr=False, options=None, probes=None, rollup_settings=None, extract_inductance=False, inductance_layers=None, enable_via_clustering=None,
tsv_subckts=None, bump_equal_potential_radius=None)
Create an ExtractView object in this database.
create_extract_view_from_files(design_view, input_files, store_dnet=False, store_pi_model=True, tag='exv', store_load_cap=False, options=None)

Create an ExtractView object from parasitics data in input_files.
create_extract_view_from_redhawk_output(design_view, rh_db_path=None, node_file=None, res_file=None, src_file=None, layer_name_map=None, net_name_map=None, tag='evrh', options=None)

Create an ExtractView object from parasitics data generated from RedHawk.
create_fx_view(design_view, fxdb=None, input_tcl_file=None, fx_executable=None, tag='fx', num_fx_workers=2, distributed=True)

Create an FXView object in this database.
create_hdl_design_view(tag='hdl', pthdl_options=None, lib_views=None, options=None)

Create an HDLDesignView object in this database.
create_hdl_view(tag, options)
Create an HDLView object in this database.
create_legacy_timing_view(design_view, process_corner='default_process', tag='tv', timing_window_files=None, options=None)

Create a TimingView for legacy flows.
create_liberty_view(liberty_files=None, apl_switch_files=None, apl_files=None, avm_config_files=None, pgarc_files=None, tag='lv', settings=None, options=None)

Create a LibertyView object in this database; contains library cell data.
create_macro_view(model_details=None, tag='macro', phymodel_views=None, options=None)

Create a MacroView (gds2rh/macro model) object in this database.
create_merged_power_view(input_views, tag='pwr_merged', options=None)

Create a PowerView by merging scaled instance power from existing PowerViews.
create_modified_design_view(design_view, eco_commands=None, cell_commands=None, flatten_std=True, tag='mdv', options=None, config_view=None, die_name=None, die_sub_id=1)

Create an ModifiedDesignView object in this database.
create_modified_extract_view_from_rollup(extract_view, rollup_settings, tag='mevr', exceptions_as_errors=False)

Create an ExtractView object form rollup.
create_multichip_analysis_view(multichip_views, tag='mcav', duration=None, step_size=None, options=None, start_from=None, keep_stats_level=None, ramp_up_nets=None, off_state_nets=None, repeat_simulation_time=None, initial_condition='avg_dc',
Create a MultichipAnalysisView in this database.
create_multichip_config_view(configfile, tag='mccfg', options=None)

Create a MultiChipConfigView object in this database.

create_multichip_coupling_view(multichip_views, tag='mcpl', options=None)
Create a MultiChipCouplingView object in this database.
create_multichip_electromigration_view(analysis_view, tag='mcemv', mode='DC', temperature_em=None, delta_t_rms=None, thermal_view=None, context_factors=None, calculate_fit=False, temperature_fit=None, fit_life_time=None, fit_mode='basic', fit_tech_file=None,
em_ruleset_names=None, em_mission_factor=None, options=None, em_settings=None, fit_settings=None, create_fit_heatmap=True)
Create a MultiChipElectromigrationView in this database.
create_multichip_thermal_view(pg_em_view=None, signal_em_view=None, sh_file=None, trf_file=None, temperature_environment=0.0, tag='mcthmv', create_heatmap=True, edge_heatmap_types=['temperature'], instance_heatmap_types=['temperature'],

thermal_calculation_settings=None, context_factors=None, options=None)
Create a MultiChipThermalView in this database.
create_no_prop_scenario_view(db, timing_view, extract_view=None, external_parasitics=None, power_view=None, voltage_levels=None, supply_connection_rules=None, temperature=25.0, analysis_duration=None, frame_length=None, arrival_time_policy='min',
process_corner='default_process', object_settings={}, mode_definitions=None, value_change_data=None, default_input_pin_transition_time=1e-11, random_seed=0, data_types=None, tag='scn', options=None, always_active_clocks=False, limit_net_cap_to_pin_max_cap=False,
ensure_coverage=False, auto_switch_macros=False, macro_settings=None, current_data_precedence=['APL', 'CCSPower', 'NLPM'], default_clock={}, target_power_settings={})
Create a dynamic ScenarioView without propagation.
create_nrc(tech_file_name, em_only_tech_file_name=None, supplemental_tech_files=None, via_variation=None, tag='nrc', options=None, start_layer=None)

Create an NRC object from a technology file.
create_path_view(design_view, gtr_files, tag='pv', options=None)

Create a PathView in this database.
create_physical_model_view(cfg_file, dbunit=2000, options=None, tech_view=None, tag='gv')

Create physical model view.
create_power_profile_view(timing_view, extract_view=None, external_parasitics=None, analysis_duration=None, time_interval_length=None, tag='pwr_profile', voltage_levels=None, temperature=25.0, options=None, activity_level=None, mode_definitions=None,
infer_icg_enable_signals_from_fanin_prop=False, object_settings={}, prefer_gate_vcd_clock_period=True, process_corner='default_process', value_change_data=None, virtual_supplies=None, supply_connection_rules=None, calculation_settings=None,
limit_net_cap_to_pin_max_cap=False, results_spec=None)
Create a PowerProfileView with power vs. time data.
create_power_view(design_view=None, power_files=None, switching_activity_view=None, extract_view=None, external_parasitics=None, timing_view=None, process_corner='default_process', voltage_levels=None, virtual_supplies=None, supply_connection_rules=None,
temperature=25.0, instance_settings=None, tag='pwr', options=None, limit_net_cap_to_pin_max_cap=False, current_data_precedence=['NLPM', 'APL', 'CCSPower'], calculation_settings=None)
Create a PowerView from IPF files and/or switching activity input.
create_power_view_from_scenario(scn, tag='pwr', options=None)

Create a PowerView from a Dynamic ScenarioView.
create_raw_gds_view(gds_file, tag='rawgds', options=None)

Create a RawGDSView object in this database; contains per-instance voltage data.
create_reduced_model_view(simulation_view, scenario_view=None, analysis_view=None, tag='gv', options=None, cpm_port_map=None, cpm_nx=None, cpm_ny=None, cpm_cdie=None, cpm_plocname=None, cpm_parasitics=None, cpm_repeat_current_time=None,
cpm_noglobal_gnd=None, cpm_passive=None, cpm_probes=None, cpm_use_afs=None, cpm_pincurrent=None, coupled_simulation=None)
Create an GrmView (generic reduced model) in this database.
create_scaled_power_view(pwr_orig, target_power_settings=None, toggle_rate_settings=None, scenario_view=None, pwr_example=None, tag='pwr_scaled', precedence='top-down', scale_leakage_power=False, leakage_scaling_factor=None, options=None)
Create a PowerView by scaling instance power from an existing PowerView.

create_scenario_view(timing_view=None, extract_view=None, external_parasitics=None, power_view=None, tag='scn', lso_files=None, voltage_levels=None, temperature=25.0, disable_clocks=None, clock_source_toggle_rates=None, options=None, simulation_flow=True,
use_signal_caps=True, activity_level=None, random_seed=None, use_instance_checksum=True, target_power=0, mode_definitions=None, instance_settings=None, scenario_duration=None, gate_vcd_mode='off', prefer_gate_vcd_clock_period=True, rtl_vcd_mode='on',
infer_icg_enable_signals_from_rtl_vcd=False, infer_icg_enable_signals_from_fanin_prop=False, zero_delay_mode=False, scenario_type='Dynamic', design_view=None, current_source_files=None, least_common_period_count=1, process_corner='default_process',
value_change_data=None, target_power_settings=None, no_leakage=False, object_settings={}, virtual_supplies=None, supply_connection_rules=None, transition_time_precedence=None, event_time_precedence=None, probe_sources=None, scan_chain_data=None,
scan_operation='shift', num_shifts=1, limit_net_cap_to_pin_max_cap=False, include_input_only_events=True, default_input_pin_transition_time=1e-12)
Create a dynamic simulation ScenarioView.
create_signal_net_current_view(simulation_view, scenario_view=None, switching_activity_view=None, timing_view=None, voltage_levels=None, external_parasitics=None, recovery_factor=-1, selected_nets=None, temperature=25.0, value_change_data=None,
const_net_overrides=None, options=None, tag='scv')
Create an SignalNetCurrentView in this database.
create_simulation_view(extract_view, tag='sv', exclude_nets=None, include_nets=None, net_type=None, options=None, package=None, sim_type='pg')

Create a SimulationView in this database.
create_switching_activity_view(timing_view, saif_files=None, vcd_files=None, value_change_data=None, propagation_style='propagate_activity', disable_clocks=None, clock_source_toggle_rates=None, use_sta_clock_info=False, settings=None, object_settings={},
time_interval_length=None, rtl_name_map_rules=None, rtl_name_map_files=None, tag='swa', options=None, infer_icg_enable_signals_from_fanin_prop=False, vcd_x_logic_state=None)
Create a SwitchingActivityView object in this database.
create_technology_view(tech_file_name, em_only_tech_file_name=None, supplemental_tech_files=None, tech_connectivity_file=None, em_mission_profile=None, tag='nrc', via_variation=None, options=None)

Create a TechView in this database.
create_thermal_view(pg_em_view=None, signal_em_view=None, sh_file=None, trf_file=None, temperature_environment=0.0, tag='thmv', create_heatmap=True, edge_heatmap_types=['temperature'], instance_heatmap_types=['temperature'],

thermal_calculation_settings=None, context_factors=None, options=None)
Perform thermal analysis.
create_thermal_view_from_files(av=None, av_sigem=None, ev=None, thermal_profile='', tag='thmv', options=None)

Create a ThermalView object from input thermal_profile.
create_timing_view(design_view, process_corner='default_process', path_view=None, tag='tv', sdc_files=None, timing_window_files=None, vcd_files=None, rtl_name_mapping_rules=None, logic_graph=True, settings=None, options=None, ignore_pin_connections={})
Create a TimingView object in this database.
create_user_view(tag='uv', save_to_db=True)
Create a UserView object in this database.
create_value_change_view(design_view, tag='vcv', vcd_files=None, rtl_name_mapping_rules=None, rtl_namemap_files=None, debug_signals=None, vcd_x_logic_state=None, options=None)

Create a ValueChangeView object in this database.
create_voltage_impact_view(simulation_view, timing_view=None, current_source_view=None, select_settings=None, default_switching_factor=0.1, options=None, tag='vim', timing_window_mode=None)

Create voltage impact view.
get(view_name, check_workers=True, wait=0)

Load and return the specified view in this database.
get_num_ppns(simulation_view, options=None)
Retuns number of power partitions that will be used in analysis.

get_view_names(force=False)
Returns a list of available view names in this database.
get_views(force=False, report_incomplete_views=False)
Returns a list of available views in this database.
perform_analysis_with_automatic_presim(simulation_view, scenario_view, scenario_view_for_presim=None, power_view=None, presim_settings=None, analysis_view_arguments=None, create_av_with_package_impact=True, user_view_for_bump_sources=None,

user_defined_presim=False)
Determine stability (presim) with package and create AnalysisView with system response.
perform_effective_resistance_calculation(extract_view, items, options=None, tag='reff')

Perform effective resistance calculation.
perform_missing_via_check(design_view, top_layer=None, bottom_layer=None, nets=None, query_rect=None, via_stack_spec=None, tag='missing_via_check', pitch=[], settings={}, user_min_via_cut=None, exclude_rects=None, exclude_cells=None, exclude_insts=None,
include_gds_cells=False, ignore_finger_geoms=False, via_rule_names=None)
Performs missing via check.
perform_shortest_resistance_path_check(extract_view, tag='spr', options=None, include_ron_in_spr=False, force=False)

Perform shortest resistance path (SPR) check.
perform_signal_em_calculation(extract_view, scenario_view=None, switching_activity_view=None, timing_view=None, voltage_levels=None, external_parasitics=None, recovery_factor=-1, selected_nets=None, mode=None, temperature=None, delta_t=None,
target_life_time='DEFAULT', metal_line_number=None, em_mission_factor=None, value_change_data=None, const_net_overrides=None, options=None)
Performing signal net EM violation check.
run_fx_view(design_view, fx_executable=None, tag='fx', input_tcl_file=None, lib_files=None, vlog_files=None, spef_files=None, sdc_files=None, num_fx_workers=6, distributed=False)
Create an FXView object for the given design view and run FX timing analysis.

View Options
• What option available at each view..
>>> help(SeaScapeDB.create_analysis_view)
create_analysis_view(simulation_view=None, scenario_views=None, tag='av', duration=None, step_size=None, options=None, start_from=None, keep_stats_level=None, ramp_up_nets=None, off_state_nets=None, repeat_simulation_time=None, initial_condition='avg_dc',
Create an AnalysisView in this database.
ARGUMENTS
simulation_view : SimulationView object (type=SimulationView, default_value=None)
scenario_views : List of ScenarioView objects (type=object, default_value=None)
tag : Name of the view (type=str, default_value='av')
duration : Simulation duration (seconds) (type=float, default_behavior='Automatically determined based on scenario current end time')
step_size : Simulation sampling step size (seconds) (type=float, default_behavior='Automatically determined', constraint="step_size must be > 0")
options : View creation options, typically from get_default_options() (type=object, default_value=None)
start_from : Start from the end of specified AnalysisView (type=AnalysisView, default_behavior='Decided based on argument initial_condition')
keep_stats_level : Detail level for simulation statistics and heatmap creation (Zero,Bqm,High,Full,Low,Medium,SystemResponse). Also see help(KeepStats) (type=object, default_value='Medium', constraint="keep_stats_level must be one of Zero, Bqm, High, Full, Low, Medium,
SystemResponse")
ramp_up_nets : Power/Ground nets that are in ramp-up (by power gates) state (type=list, default_behavior='no ramp-up nets')
off_state_nets : Power/Ground nets that are in off (power-gated) state (type=list, default_behavior='no off-state nets')
repeat_simulation_time : Repeat demand current time in seconds (type=float, default_behavior='no repeat')
initial_condition : Specify what initial condition calculation (presim) method to use. This is an umbrella argument that override delay_simulation_start and current_type_for_dc unless they are specified (type=str, default_value='avg_dc', constraint="Valid values are 't0' or 'avg_dc'")
delay_simulation_start : Delay for simulation start in seconds (can be a list for multi-scenario). Alternatively you can specify 'Avg' to shift start to average total demand current of highest energy net (type=object, default_behavior="'Avg' if initial_condition is 'avg_dc', otherwise 0.0")
current_type_for_dc : Set to 'Avg' to use average current for each instance pin at dc (type=str, default_behavior="'Avg' if initial_condition is 'avg_dc', otherwise 't0'", constraint="Valid values are 't0' or 'Avg'")
delay_stats : Delay for statistics collection in seconds (can be a list for multi-scenario) (type=object, default_behavior='Statistics collection starts from simulation time 0')
current_snap_method : Set the time_step snapping method to use for demand currents (type=str, default_value='charge', constraint="Valid values are 'charge' or 'peak' or 'none'")
enable_start_from : When enabled ckt state for the last step gets saved so that a new av can start from this (type=bool, default_value=False)
current_derate_mode : Set voltage derate method in transient simulation (type=str, default_value='off', constraint="one of ['chargebased', 'legacy', 'off']")
battery_levels : Dict of voltage levels supplied for battery in av (type=object, default_behavior='Automatically assigned from Power/Ground net ScenarioView voltage levels', constraint="dict of net name pattern to float")
symmetric_repeat : When demand currents are repeated, use symmetric repeat for demands (type=bool,default_value=False)
simulate_system_response : When turned on a matematical model for chip is hookedupwith package for simulation (type=bool, default_value=False)
scheduler_barrier : When set to True scheduler will make sure to complete thisAnalysisView jobs before executing the jobs after this AnalysisView (type=bool, default_value=True)
DETAILS
initial_condition is used for system DC state at time 0.
When 'avg_dc' is used, the simulation will be advanced to the step where the instantaneous total demand
for the highest power net is equal to the average current for that domain. This allows for the distributed system RLC to be
at proper voltages without introducing a false di/dt event at the first step of the transient solve.
Using 't0' forces the system to use the DC state of time 0 in the ScenarioView.
keep_stats_level controls the data that is saved during simulation.

'Full' : all pin voltage waveforms, instance and instance/pin per cycle voltage stats, current heatmap and histogram, instanc e and node voltage heatmaps and histograms, bump voltage and current waveforms
'High' : instance and instance/pin per cycle voltage stats, instance and node voltage heatmaps and histograms, bump voltage a nd current waveforms
'Medium' : node voltage heatmaps and histograms, bump voltage and current waveforms
'Low' : essentially nothing -- only the worst individual instance power and ground pins over the full simulation-- not recommended to be used

KeepStats
>>> help(KeepStats)
CLASS
KeepStats
Bookkeeping and heatmap control class for AnalysisView.
DETAILS
For more details please run "help(KeepStats.__init__)" .
FUNCTIONS
KeepStats(level, node_stats=None, edge_currents_stats=None, instance_heatmaps=None, node_voltage_heatmaps=None, current_heatmaps=None, bump_voltages=None, bump_currents=None, user_probe_voltages=None, power_gate_currents=None, pin_voltages=None,
cycle_stats=None, fullsim_stats=None, effective_dvd_stats_mode='avg', instance_probes=None, timing_window_stats_mode='full_tw', effective_dvd_in_only_use_delay_filter=None, bump_heatmaps=None, first_event_used_for_effective_dvd=None,
max_num_cycles_in_stats=None, probe_shadow_cell_pins=None, probe_filler_cell_pins=None, probe_decap_cell_pins=None)
Bookkeeping and heatmap control class for AnalysisView.

KeepStats - detail
>>> help(KeepStats.__init__)
>>> help(KeepStats.__init__)
__init__(level, node_stats=None, edge_currents_stats=None, instance_heatmaps=None, node_voltage_heatmaps=None, current_heatmaps=None, bump_voltages=None, bump_currents=None, user_probe_voltages=None, power_gate_currents=None, pin_voltages=None,
cycle_stats=None, fullsim_stats=None, effective_dvd_stats_mode='avg', instance_probes=None, timing_window_stats_mode='full_tw', effective_dvd_in_only_use_delay_filter=None, bump_heatmaps=None, first_event_used_for_effective_dvd=None,
max_num_cycles_in_stats=None, probe_shadow_cell_pins=None, probe_filler_cell_pins=None, probe_decap_cell_pins=None)
ARGUMENTS
level : bundle control setting (type=str, required=True, constraint="level must be one of Zero,Bqm,High,Full,Low,Medium,SystemResponse")
node_stats : Force pg circuit node voltage statistics bookkeeping (type=bool, default_value=None)
edge_currents_stats : Force pg circuit edge current statistics bookkeeping (type=bool, default_value=None)
instance_heatmaps : Force create instance voltage heatmaps (type=bool, default_value=None)
node_voltage_heatmaps : Force create node voltage heatmaps (type=bool, default_value=None)
current_heatmaps : Force create edge current heatmaps (type=bool, default_value=None)
bump_voltages : Force bookkeep transient bump voltages (type=bool, default_value=None)
bump_currents : Force bookkeep transient bump currents (type=bool, default_value=None)
user_probe_voltages : Force bookkeep transient user probe voltages (type=bool, default_value=None)
power_gate_currents : Force bookkeep transient power gate currents (type=bool, default_value=None)
pin_voltages : Force bookkeep transient instance pin voltages (type=bool, default_value=None)
cycle_stats : Force bookkeep cycle stats for instance and pin voltages (type=bool, default_value=None)
fullsim_stats : Force bookkeep statistics for instance and pin voltages (type=bool, default_value=None)
effective_dvd_stats_mode : Defines fullsim effective dvd calculation method (type=str, default_value='avg', constraint="effective_dvd_stats_mode takes one of the ['avg', 'min', 'max']")
instance_probes : List of instances or instance pins for selective probing (type=object, default_value=None)
timing_window_stats_mode : Define timing window stats calculation method (type=str, default_value='full_tw', constraint="timing_window_stats_modetakes one of the ['full_tw', 'sliding_window']")
effective_dvd_in_only_use_delay_filter : Filter effective dvd stats for in_only delay (type=bool, default_value=None)
bump_heatmaps : Force create bump current and voltage heatmaps (type=bool, default_value=None)
first_event_used_for_effective_dvd : Use first event's start time and direction in case of overlapping events for effective dvd stats (type=bool, default_value=None)
max_num_cycles_in_stats : Defines maximum number of cycles in cycle stats (type=int, default_value=128)
probe_shadow_cell_pins : Controls voltage statistics capturing for shadow cell instances (type=bool, default_value=False)
probe_filler_cell_pins : Controls voltage statistics capturing for filler cell instances (type=bool, default_value=False)
probe_decap_cell_pins : Controls voltage statistics capturing for decap cell instances (type=bool, default_value=False)
DETAILS
level provides bundle control of individual bookkeeping or heatmap items.
Valid values are 'Zero','Bqm','High','Full','Low','Medium','SystemResponse'.
To see contents of each setting, please run "print KeepStats(<level>)".
EXAMPLE
# Run at Medium stats level, and force to create current_heatmaps and instance pin transient voltages
av = db.create_analysis_view(..., keep_stats_level=KeepStats('Medium', current_heatmaps=True, pin_voltages=True))
49 © 2018
# RunANSYS, Inc.
at Full stats level, and force to skip bookkeeping for cycle stats ANSYS Confidential
KeepStats : Each Level
>>> print KeepStats('Full') >>> print KeepStats('High') >>> print KeepStats('Medium') >>> print KeepStats('Low')
{'bump_currents_': True, {'bump_currents_': True, {'bump_currents_': True, {'bump_currents_': False,
'bump_heatmaps_': True, 'bump_heatmaps_': True, 'bump_heatmaps_': True, 'bump_heatmaps_': False,
'bump_voltages_': True, 'bump_voltages_': True, 'bump_voltages_': True, 'bump_voltages_': False,
'current_heatmaps_': True, 'current_heatmaps_': True, 'current_heatmaps_': True, 'current_heatmaps_': False,
'cycle_stats_': True, 'cycle_stats_': True, 'cycle_stats_': False, 'cycle_stats_': False,
'drop_stats_': True, 'drop_stats_': True, 'drop_stats_': True, 'drop_stats_': True,
'edge_currents_stats_': True, 'edge_currents_stats_': True, 'edge_currents_stats_': True, 'edge_currents_stats_': False,
'effective_dvd_in_only_use_delay_filter_': False, 'effective_dvd_in_only_use_delay_filter_': False, 'effective_dvd_in_only_use_delay_filter_': False, 'effective_dvd_in_only_use_delay_filter_': False,
'effective_dvd_stats_mode_': 'Avg', 'effective_dvd_stats_mode_': 'Avg', 'effective_dvd_stats_mode_': 'Avg', 'effective_dvd_stats_mode_': 'Avg',
'first_event_used_for_effective_dvd_': None, 'first_event_used_for_effective_dvd_': None, 'first_event_used_for_effective_dvd_': None, 'first_event_used_for_effective_dvd_': None,
'fullsim_stats_': True, 'fullsim_stats_': True, 'fullsim_stats_': True, 'fullsim_stats_': False,
'gui_images_': None, 'gui_images_': None, 'gui_images_': None, 'gui_images_': None,
'instance_heatmaps_': True, 'instance_heatmaps_': True, 'instance_heatmaps_': True, 'instance_heatmaps_': False,
'max_num_cycles_in_stats_': None, 'max_num_cycles_in_stats_': None, 'max_num_cycles_in_stats_': None, 'max_num_cycles_in_stats_': None,
'node_stats_': True, 'node_stats_': True, 'node_stats_': True, 'node_stats_': False,
'node_voltage_heatmaps_': True, 'node_voltage_heatmaps_': True, 'node_voltage_heatmaps_': True, 'node_voltage_heatmaps_': False,
'pin_voltages_': True, 'pin_voltages_': False, 'pin_voltages_': False, 'pin_voltages_': False,
'power_gate_currents_': True, 'power_gate_currents_': False, 'power_gate_currents_': False, 'power_gate_currents_': False,
'probe_decap_cell_pins_': None, 'probe_decap_cell_pins_': None, 'probe_decap_cell_pins_': None, 'probe_decap_cell_pins_': None,
'probe_filler_cell_pins_': None, 'probe_filler_cell_pins_': None, 'probe_filler_cell_pins_': None, 'probe_filler_cell_pins_': None,
'probe_shadow_cell_pins_': None, 'probe_shadow_cell_pins_': None, 'probe_shadow_cell_pins_': None, 'probe_shadow_cell_pins_': None,
'selected_probe_view_': None, 'selected_probe_view_': None, 'selected_probe_view_': None, 'selected_probe_view_': None,
'tw_stats_mode_': 'full_tw', 'tw_stats_mode_': 'full_tw', 'tw_stats_mode_': 'full_tw', 'tw_stats_mode_': 'full_tw',
'user_probe_voltages_': True} 'user_probe_voltages_': True} 'user_probe_voltages_': True} 'user_probe_voltages_': False}

get_stats
>>> dir(av_static)
['add_pickled_view', 'arg_id_', 'barrier_no_', 'barrier_views_', 'build_info_', 'cache_', 'check_and_set_var', 'check_and_translate_input_file', 'check_keep_stats_level', 'ckt_helper_', 'create_post_analysis_heatmaps',
'create_view_object', 'create_view_object_slave', 'current_version_', 'db_name_', 'dbg_level_', 'enable_save_', 'ensure_read_ds', 'get', 'get_attributes', 'get_average_bump_voltages', 'get_average_bump_voltages_by_id',
'get_battery_currents_by_id', 'get_bump_currents_by_id', 'get_bump_groups', 'get_convergence_histogram', 'get_convergence_per_net', 'get_convergence_runtime_histogram', 'get_convergence_stats',
'get_convergence_stats_v2', 'get_current', 'get_current_heatmap', 'get_current_histograms', 'get_current_stats', 'get_current_stats_by_id', 'get_db_name', 'get_decap_stats', 'get_decap_stats_by_id', 'get_ds_name',
'get_ds_out_name', 'get_edge_current_stats', 'get_elapsed_sim_time', 'get_func_views', 'get_info', 'get_input_files', 'get_instance_arc_voltage_stats_by_id', 'get_instance_attributes', 'get_instance_attributes_by_id',
'get_instance_pin_waveform_by_id', 'get_instance_voltage_heatmap', 'get_instance_voltage_histogram', 'get_instance_voltage_stats_by_id', 'get_job_name', 'get_latest_version', 'get_liberty_process_id', 'get_license_flag',
'get_license_key', 'get_matrix_stats', 'get_max_pin_voltage_histograms', 'get_new_tag', 'get_node_stats', 'get_node_voltage_heatmap', 'get_node_voltage_histograms', 'get_options', 'get_partitions',
'get_pin_voltage_stats_by_id', 'get_power_gate_current', 'get_power_gate_currents_by_id', 'get_power_gate_pin_current_by_id', 'get_quiet_state', 'get_read_compatible_version', 'get_related_views', 'get_scenario_views',
'get_simulation_parameters', 'get_simulation_views', 'get_stats', 'get_sv', 'get_tag', 'get_temperature', 'get_total_battery_currents', 'get_total_bump_currents', 'get_total_power_gate_currents',
'get_total_used_demand_currents', 'get_total_used_demand_currents_by_id', 'get_used_demand_current', 'get_used_demand_current_shift', 'get_used_demand_currents', 'get_used_demand_currents_by_id',
'get_used_instance_demand_current_by_id', 'get_var', 'get_var_from_scheduler', 'get_version', 'get_view_name', 'get_view_type', 'get_voltage', 'get_voltage_level_view', 'get_voltage_stats', 'get_waveform_by_id',
'get_worst_drop_stats', 'has_scheduler_barrier',………]
>>> av_static.get_stats()
{'convergence_stats': {'bounce_node_names': ['(node=5, layer=4, xy=Coord(60500000,500000))'],
'bounce_pin_names': ['(instance=1, pin=5)'],
'drop_node_names': ['(node=5, layer=0, xy=Coord(13786704,107802440))'],
'drop_pin_names': ['(instance=0, pin=37614)’],
………………………..
'sim_params': {'begin_time': 0, 'end_time': 0.0, 'hh_step': 5e-12, 'num_time_steps': 0},
'transient_runtime<skip=True>': 0.0},
'decap_stats': {'average_instance_coverage': 0.0,
'cdie': 0.0,
'total_decap': 0.0,
'total_intrinsic_cap': 0.0,
'total_pg_route_cap': 0.0,
'total_pin_load_cap': 0.0,
'total_signal_load_cap': 0.0},
'factorization_stats': {'DC': {'pp0': {'factor_nnz': 67600, 'ncol': 8703, 'nnz': 21301},
'total': {'factor_nnz': 67600, 'ncol': 8703, 'nnz': 21301}}},
'matrix_stats': {'pp0': {'ncol': 8703, 'nnz': 34812, 'nrow': 8703, 'pin_count': 11165}},
'num_power_partitions': 1,
'num_scenarios': 1,
'power_partitions': {'pp0': [(-100, -100), (0, 0)]}}
>>> av_static.get_stats()['power_partitions']
{'pp0': [(-100, -100), (0, 0)]}
>>> av_static.get_stats()['num_power_partitions']
1

BQM
• bqm_currents
• bqm_probes
bqm_currents[0]
bqm_currents
bqm_probes[0] bqm_curr = bqm_currents
write_to_file('bqm.current', bqm_curr)
bqm_probes
>>> b=min(bqm_currents)
>>> print(b)
{'name': 'probe_1000.043639.57', 'value': -0.0}
c=0
for i in bqm_currents:
if i['value']<=0:
c+=['value']

Pin/Phantom Creation Scheme
Phantom (or pin, or current sink, or pininst in RH terminology) creation is another factor which could cause difference on static IR correlation.
Basically, RedHawk-SC has multiple ways to determine where to drop a phantom:
⚫ SingleTop mode
⚫ In SingleTop mode, RHSC will create phantom on largest pin geometry (based on the area) among all pin geometries which are physically conn ected together.
For example, if cell has Pin('VDD') placed on both M1 and M2, and they are connected through LEF via, then only phantom will be created on the largest pin
geometry on M2. If M1 and M2 pin shapes are not connected, then phantom will be created on largest geometries on both M1 and M2. Depend on the size of
the geometries, if smaller than LayoutOptions.max_phantom_distance, one phantom will be created at the center of selected geometries. Otherwise, multiple
phantoms will be created according to specified distance. By default, the distance is set to be 15 microns.
⚫ AllBottom mode
⚫ In opposite to SingleTop mode, AllBottom mode creates phantom on every pin geometries routed on the lowest metal layer for each physically connected LEF
pin geometry group. For example, if cell has Pin('VDD') placed on both M1 and M2, and they are connected through LEF via, the n phantom will be created on
each pin geometry on M1. If M1 and M2 are not connected, then phantom will be created on pin geometries on both M1 and M2. Sa me as SingleTop mode,
LayoutOptions.max_phantom_distance will also be applied here for phantom creation.
⚫ SimpleBottom mode
⚫ SimpleBottom mode is simplified version of AllBottom mode. The only difference is: in SimpleBottom mode, the phantom will NOT be created on "finger" pin
geometries. Finger geometry is small tentacle extended from dominant pin geometry.
⚫ Adaptive mode
⚫ In Adaptive mode, RHSC will check all LEF cellls defined in the design, and determine the medium cell size. If the cell is bigger than medium cell size, AllBottom
mode will be used, otherwise SingleTop mode will be used.
⚫ Combination mode
⚫ Combination mode tries to mimic RH default behavior, and is default mode used in correlation mode " get_default_options(redhawk_mode=True)". In short, if
the cell has only one geometry cross all pin geometries which expand to whole width/length of the cell, then this geometry wi ll be chosen for phantom
creation. If the multiple geometries are found similar to cell size, then any node created on those geometries during parasit ic extraction, those nodes will be
used as phantom.

Power calcuration

• Power Calculation in RHSC

RedHawk-SC
Decoupling Capacitance
Handling
October 2017
57 © 2018 ANSYS, Inc. ANSYS CONFIDENTIAL ANSYS Confidential ANSYS Confidential

Redhawk-SC decap stamping
VDD
Ron (Cload / 2) * quiet_ratio
(Cload / 2) * quiet_ratio = Load factor cap
VSS
quiet_ratio = 1 – total_transition_time/total_time
VDD
total_transition_time is time during simulation that the

ESR Ron
instance is transitioning from 0->1 and 1->0
ESC Load factor cap
Ron = computed from slew and load on the fly

VSS

Redhawk-SC decap and intrinsic cap
Assumes net load capacitances are coupled 50% to power and 50% to ground
The Effective Series Resistance (ESR) and Effective Series Capacitance (ESC) are read
from the APL cdev data.
Note: In reporting the data in the AnalysisView through get_attributes and

get_decap_stats, users will see per Net/Pin data as well as the Total. The per Net
data is based on the Pin ESR/ESC from the APL files while the Total data reports the
true coupled values.

Thank You!

Redhawk-SC ： Check VCD Coverages
from thpkgs.ae_utils import report_block_vcd_annotation as rpt_annotation

r.report_block_vcd_annotation_style_c(vcv,dump_unannotated_inst=['seq'],file_nam
e='vector_annotation',block_list = ['<>','<>','<>','<>’])
help(rpt_annotation.report_block_vcd_annotation_style_c)
vcv.get_coverage()
vcv.get_coverage(report_uncovered_instances=True)

LTCellType
help(LTCellType) is_fall_edge_triggered() is_macro_mmx_view()
CLASS Determine if the cell type is a fall edge-triggered sequential cell. Determine if the cell type is a MMX model.
LTCellType
Characteristics of a Cell. is_filler_cell() is_pad_cell()
Determine if the cell type is a filler cell. Determine if the cell type is a pad.
SEE ALSO
DesignView is_gds_cell() is_power_gate()
Cell Determine if the cell type is a cell from GDS. Determine if the cell type is a power gate cell.
FUNCTIONS is_icg_cell() is_rise_edge_triggered()

is_bank() Determine if the cell type is a integrated clock gate cell. Determine if the cell type is a rise edge-triggered sequential cell.
Determine if the cell type is a multi-bit sequential.
is_lef_cell() is_seq_cell()
is_bump_cell() Determine if the cell type is a cell from LEF. Determine if the cell type is a sequential cell.
Determine if the cell type is a bump.
is_level_sensitive() is_shadow_cell()
is_cmm_macro_cell() Determine if the cell type is a level-sensitive latch. Determine if the cell type is a macro shadow (inner) cell.
Determine if the cell type is a CMM macro.
is_level_sensitive_bank() is_shadow_parent_cell()
is_decap_cell() Determine if the cell type is a level-sensitive multi-bit latch. Determine if the cell type is a macro shadow parent (outer) cell.
Determine if the cell type is a decoupling capacitance cell.
is_level_shifter() is_signal_cell()
is_def_cell() Determine if the cell type is a level shifter. Determine if the cell type is a cell with signal pins.
Determine if the cell type is a cell from DEF.
is_lib_macro_cell() is_std_cell()
is_edge_triggered() Determine if the cell type is a Liberty macro. Determine if the cell type is a standard cell.
Determine if the cell type is a edge-triggered flip-flop.
is_macro_cell_view() is_via_cell()
is_edge_triggered_bank() Determine if the cell type is a cell view model. Determine if the cell type is a via.
Determine if the cell type is a edge-triggered multi-bit flip-flop.

GUI
CLASS open_window(load_init_file=True, width=None, height=None)
LayoutWindow Reopen layout window if closed.
A GUI window for layout viewing.
remove_layer(layer_name)
SEE ALSO Deletes one or more layers from the gui window.
gp.open_layout_window
remove_link(link_gui)
FUNCTIONS Removes a link gui from view port locking.
add_layer(layer_data, layer_name, reverse_colors=None, visible=None)
Adds GUI data to the specified layer. save_layer_attributes(file_name=None)
Save all LayoutConfig to a specific file.
add_link(link_gui)
Adds a link gui for view port locking. save_markers(file_name)
Save all Markers to a specific file.
add_markers(markers)
Adds marker(s). select_instance(instance=None, zoom=True, zoom_radius=5.0)
Selects a leaf instance. Call with no arguments to clear selection.
add_shapes(layer_name, items, visible=True, auto_zoom=True)
Add shapes to a layer. select_net(net=None, all=None, selected=True)
Selects a net. Call with no arguments to clear selection.
add_spr_path(spr_path, layer_name)
Display/Highlight the shortest resistance path. set_attributes(name, visible=True, column=1)
select/deselect selectors's(Heatmaps, Views, Objects,Layers, Nets...) item.
clear_markers()
Delete all current markers. set_layer_attribute(layer_name, color=None, stipple=None, width=None, size=None, alpha=None,
visible=None, selectable=None)
create_layer(layer_name, visible=False) Sets style attributes for a GUI layer.
Creates a new layer in the gui window.
set_layer_colormap(layer_name, coolv=None, hotv=None, alpha=None, cool_is_black=None,
exit() hot_is_black=None, colormap_style=None, stipple_patterns=None, hide_infinity=None, logarithmic=None,
Closes the GUI window. color_range_values=[], flip=False)
Sets heatmap values for cool, hot and alpha.
fit()
Zoom fit. set_mode(rough_image_hot_only=None, rough_image_draw_ellipse=None, rough_image_pixel_size=None,
heatmap_value_display_precision=None, max_boxes_at_level=None, max_boxes_at_detail=None,
get_available_colors() max_image_zoom_level=None, selection_mode=None, query_on_click=None, layer_name=None,
is_always_show_details=None)
Returns available color names. Sets various modes of operation in gui.
get_layer_colormap(layer_name) set_object_attribute(object_name, visible=None)
Returns heatmap colormap cool, hot values and various heatmap display parameters. Sets object attributes.
goto_pos(x_coord, y_coord, zoom_radius=5.0) set_text_filter(name)
Jump to a specified location and zoom. Filters text objects by regex or glob (bumps, markers).
load(view, load_init_file=True, wait_until_ready=True) show_legend(enable)
Loads data from view into the GUI window. control the display of the legend of heatmaps.
load_layer_attributes(file_name=None) snapshot(file_name, panel='LayoutPanel')
Read LayoutConfig from a specific file. Smile! Takes a picture of the layout window and saves in png format.
load_markers(file_name) zoom_coord(coord, zoom_radius=0.5)
Read Markers from a specific file and add them. Zoom to a particular coordinate.
move_layer(layer_name, master_layer_name=None) zoom_rect(rect)
Moves layer under another layer. Zoom to a particular rectangular region.
>>> help(set_config.global_memory_control)
set_config('global_memory_control', (level)
Global memory vs network vs runtime trade-off command.
ARGUMENTS
level : control level (type=str, required=True, constraint="must be one of
'High','Medium','Low'")
DETAILS
This command can be used to decrease memory and/or network consumption with some
runtime penalty
By default, SeaScape executes all of the view's jobs concurrently. Views do not
wait for other views to be
fully completed to start. Moreover, data is kept in resident memory of workers
for fastest execution (not on disk).
Unlike other configs, this one can be used anywhere in script and it will block
execution before changing the tool mode.
Low: default.
Medium: run views one by one to make sure view saves don't happen when other
jobs are running to help network congestion.
High: run views one by one and move worker memory to disk after each view is
completed, to reduce worker peak memory.
High mode is same as inserting move_views_to_disk after every
>>> help(set_config.global_disk_space_control)
set_config('global_disk_space_control', (level)
Global disk space vs runtime trade-off command.
ARGUMENTS
level : control level (type=str, required=True, constraint="must be one of
'High','Medium','Low'")
DETAILS
This command can be used to decrease disk consumption of SC-DB with some runtime
penalty
By default, SeaScape uses a fast compressor for its data storage under DB. This
command can be
used to increase the compression level.
Low: default compression. Optimized for faster runtime.
Medium: use zlib_level6 compression for large data files and zlib_level4 for
regular data files. Decrease heatmap resolution to 800.
High: use zlib_level9 compression for large data files and zlib_level4 for
regular data files. Decrease heatmap resolution to 600.
For more detailed control of compression and heatmap resolution, see
file_compression
65 © 2018 ANSYS, Inc. and image_pixel settings in help(set_config). ANSYS Confidential
Defaultと違うオプションを調べる

Worker追加スクリプト for Socionext
/home/fkambara/work_SH/scripts/socio_utils.py
>>> help(socio_utils.add_workers)
add_workers(file, wait_time=10, remove_list=False)
Create new launcher once a host list is ready.
ARGUMENTS
file : A List of Host (type=str, required=True)
wait_time : Waiting time if the list is not available: Default=10 (type=int,
default_value=10)
remove_list : delete the List of Host after launching workers: Default=False
(type=bool, default_value=False)
DETAILS
Create new launcher once a host list is available, otherwise check a list
availability every 10 sec in default.

V2V Correlation

Comparing Instance DvD Heatmap
>>> help(v2v_heatmap.create_v2v_instance_voltage_heatmap)
create_v2v_instance_voltage_heatmap(golden, new, skip_partial_coverage=True, net=None)
Create V2V Instance voltage Heatmap.
ARGUMENTS
golden : AnalysisView for golden (type=AnalysisView, required=True)
new : AnalysisView for new (type=AnalysisView, required=True)
skip_partial_coverage : Skip instances that are not present in all the hetmaps (type=bool, default_value=True)
net : A Net object to use as a filter (type=Net, default_value=None)
DETAILS
This script can be used to create instance based heatmaps given as golden and new analysisView, and returns a
resultant heatmap.
The heatmap is created by following function:

diff = (golden_dvd - new_dvd)/golden_dvd
User have to add this heatmap layer manually to see on GUI;

%gui.add_layer(hm, 'V2V Instance Voltage')
Comparing Instance DvD Heatmap
Color range is difference

from -1.3% to 2.6%.

Changed rollup_settings
descriptions
Changed rollup_settings descriptions 本設定にて、M1をM2にrollup
最後の記述のみ有効
• 2020_R2.0より、rollup_settingsの記述方法が変更
‐ トップ層より何レイヤー残すかを指定
• e.g.) M1～M15の構成で、M1～M9までをM10にrollupする（M11～M15は影響無） ➔ keep_metals=6
72
ev_rollup = db.create_extract_view(
design_view=dv,
tech_view=nv,
tag ='ev_rollup',
run.py temperature=25,
calculate_spr=True,
rollup_settings=ev_utils.create_rollup_settings(dv,keep_metals=3),
options=options,
)
実行後確認
>>> ev_rollup.get_rollup_settings()
transcript {Instance(''): {'rollup_layer': Layer('metal10')}, Instance('core3'): {'rollup_layer': Layer('metal10')}}
73
Explorer
74
From 2021R2
75
Appendix
76
77

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1 © 2018 ANSYS, Inc. ANSYS Confidential

• Then, it turns on Debug Mode

2 © 2018 ANSYS, Inc. ANSYS Confidential

• For making sure how many PPN created

• For viewing how XT/PP created in GUI

3 © 2018 ANSYS, Inc. ANSYS Confidential

• For making sure how many xt-partition has created

4 © 2018 ANSYS, Inc. ANSYS Confidential

• For making sure how many PPN created

• For viewing how PPN created in GUI

5 © 2018 ANSYS, Inc. ANSYS Confidential

6 © 2018 ANSYS, Inc. ANSYS Confidential

• After pick one of xt-partition, and

7 © 2018 ANSYS, Inc. ANSYS Confidential

8 © 2018 ANSYS, Inc. ANSYS Confidential

for ckt in circuits:

9 © 2018 ANSYS, Inc. ANSYS Confidential

It asks password. Now, it will display how resistance network

11 © 2018 ANSYS, Inc. ANSYS Confidential

plot voltage -name C642/C618092 -sv

12 © 2018 ANSYS, Inc. ANSYS Confidential

Type “gsr set plot_region_no_limit 1”

13 © 2018 ANSYS, Inc. ANSYS Confidential

For Checking Current Waveform..

Select Cell Type

For finding target waveform,

14 © 2018 ANSYS, Inc. ANSYS Confidential

15 © 2018 ANSYS, Inc. ANSYS Confidential

# Plot Instance Waveforms

16 © 2018 ANSYS, Inc. ANSYS Confidential

17 © 2018 ANSYS, Inc. ANSYS Confidential

aplの中のネットID：37517 State：0 を指定してます

18 © 2018 ANSYS, Inc. ANSYS Confidential

Steps for generating one sample (single voltage)

STEP1. covert the APL binary file to text file

aplchk -w current.txt cell.current

perl apl.pl current.txt 0.6

STEP3. again covert back text file to binary

aplchk -a2b <output> <input>

19 © 2018 ANSYS, Inc. ANSYS Confidential

❑ MBFF APL firing time :

21 © 2018 ANSYS, Inc. ANSYS Confidential

❑ We are using “DYNAMIC_LOCAL_GROUND_CURRENT_SCALING 0” in RH to match

22 © 2018 ANSYS, Inc. ANSYS Confidential

23 © 2018 ANSYS, Inc. ANSYS Confidential

If scn is crushed, create scenario view with

24 © 2018 ANSYS, Inc. ANSYS Confidential

25 © 2018 ANSYS, Inc. ANSYS Confidential

For making sure default option value..

26 © 2018 ANSYS, Inc. ANSYS Confidential

27 © 2018 ANSYS, Inc. ANSYS Confidential

28 © 2018 ANSYS, Inc. ANSYS Confidential

>>> gp_dict(options['tech_options'].options_) >>> gp_dict(options['electromigration_options'].options_)

29 © 2018 ANSYS, Inc. ANSYS Confidential

30 © 2018 ANSYS, Inc. ANSYS Confidential

31 © 2018 ANSYS, Inc. ANSYS Confidential