COMPUTER SCIENCE & ENGINEERING Flip Flops and Counters

Experiment 5

FLIP FLOPS & COUNTERS

Objectives
After completing this experiment, you will be able to:
- The operation of flip-flops (JK and D-FFs).
- Analyse and design asynchronous (up/down) counters using JK-Flip Flops.
- Analyse and design a synchronous counter using JK-Flip Flops.

Materials Needed
- 2 INPUT-NAND GATE: IC 74LS00.
- IC 74LS112: 2 JK-FFs.
- IC 74LS74: 2 D-FFs.
- IC 74LS47: BCD to 7-Segment Decoder/Driver
- IC 74LS04: 6 NOT gates.
- IC 74LS00: 4 NAND gates.
- IC 74LS86: 4 XOR gates.
- IC 74LS32: 4 OR gates.
- IC 74LS02: 4 NOR gates.
For further investigation:
Materials to be determined by students.

Presentations and Multisim

On Tuesdays (Group 1: P2b, Group 2: P2c; Group 3: P2a; Group 4: P2d; Group 6: P3)
On Thursdays (Group 1: P2b, Group 2: P2c; Group 3: P2a; Group 4: P2d; Group 5: P3)

Procedures

P1. Flip Flops

a. JK-FF (74LS112)

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COMPUTER SCIENCE & ENGINEERING Flip Flops and Counters

SW0
J K Q Q+
U2A 0 0 0

4
3 5
74LS112 0 1 0

PRE
SW2 J Q LED DISPLAY

SW4/PULSE
1 1 0 0
CLK

1 1 0

CLR
2 6
SW3 K Q LED DISPLAY

15
0 0 1
0 1 1
SW1
1 0 1
Figure 1. JK-Flip flop
1 1 1
Table 1. Truth Table of JK-FF

- Implement the circuit shown in Figure 1

- Check the active state of the signals PRE and CLR :

PRE
CLR
- Verify the operation of JK-FF (fulfill the truth table shown in Table 1)
b. D-FF (7474)
SW0

D Q Q+
U19A
4

2 5
0 0
PRE

CK D Q LED DISPLAY

Pulse SW
3
CLK 1 0
CLR

Q
6
LED DISPLAY 0 1
74LS74
1 1
1

SW1

Figure 2. D-Flip flop Table 2. Truth Table of D-FF

- Implement the circuit shown in Figure 2

- Check the active state of the signals PRE and CLR :

PRE
CLR
- Experiment to verify the operation of D-FF (fulfill the truth table shown in Table 2)

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COMPUTER SCIENCE & ENGINEERING Flip Flops and Counters
P2. Analyse and design asynchronous counters
a. Implement an asynchronous up counter having M = 8 by using IC 74LS112
LED LED LED

SW1

10
4

4
High High
3 5 11 9 3 5

PR

PR

PR
High J Q J Q J Q
1 13 1
Clock CLK CLK CLK
2 6 12 7 2 6
CL

CL

CL
High K QN K QN K QN
15

14

15
High High
SW2
74LS112 74LS112 74LS112

Figure 5 - Logic diagram

- Implement the above circuit in figure 5. Control PR (SW1) and CL (SW2) to make the
circuit operate.
- Observe and explain the results.
b. Design an asynchronous up counter having M = 6 by using IC 74LS112
- Show the way to design:

- Build the circuit

f(C,B,A) = CBA(1,3,5,6)

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COMPUTER SCIENCE & ENGINEERING Flip Flops and Counters

c. Implement an asynchronous 3-bit down counter having M = 8 by using IC 74LS112.

LED LED LED

SW1

10
4

4
High High
3 5 11 9 3 5

PR

PR

PR
High J Q J Q J Q
1 13 1
Clock CLK CLK CLK
2 6 12 7 2 6
CL

CL

CL
High K QN K QN K QN
15

14

15
High High
SW2
74LS112 74LS112 74LS112

Figure 7 - Asynchronous 3-bit down counter having M=8

- Implement the above circuit shown in figure 7. The PR (SW1) and CL (SW2) inputs
are in the appropriate states to make the circuit operate:
PR :

CL :
- Observe the results and give conclusions:
d. Implement an asynchronous 3-bit counter having M = 8, with a control for up/down
counting
LED LED LED

SW1
10
4

4
High High
3 5 11 9 3 5
PR

PR

PR

High J Q 1 J Q 1 J Q
1 3 13 3 1
Clock CLK 2 CLK 2 CLK
2 6 12 7 2 6
CL

CL

CL

High K QN K QN K QN
74LS86 74LS86
15

14

15

High
High
SW2
74LS112 74LS112 74LS112

SW3-Control

Figure 8 – Asynchronous 3-bit up counter having M = 8

- Implement the above circuit shown in figure 8 (using IC74LS112 and 74LS86). The

PR (SW1) and CL (SW2) inputs are in the appropriate states to make the circuit
operate:
PR :

CL :

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COMPUTER SCIENCE & ENGINEERING Flip Flops and Counters
- Observe the results when C = 0 and C = 1 and give conclusions

P3. Analyse and design synchronous counters

SW

1
3

10
4

4
Q0 Q0 Q1 Q1 2 Q2 Q2
3 5 11 9 3 5
PR

PR

PR
J Q J Q J Q
74LS08
1 13 1
CLK CK CLK
2 6 12 7 2 6
CL

CL

CL
K /Q K /Q K /Q
74LS112 74LS112 74LS112
15

14

15
SW
Clock
Figure 9
- Implement the circuit shown in figure 9. The K inputs of FF0 and FF2 are connected to

High level. The PR (SW1) and CL (SW2) inputs are in the appropriate states to make
the circuit operate.
- When the clock is active:

- Write the excitation (trigger) input equations of all flip-flops:

J0 = …………………...............; K0 = ….……………...............
J1 = …………………...............; K1 = ….……………...............
J2 = …………………...............; K2 = ….……………...............
- Draw the state diagram of the counter in Figure 10:

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