COMPUTER SCIENCE & ENGINEERING Shift Register

Experiment 7

SHIFT REGISTER
Objectives
After completing this experiment, you will be able to:
- Understand the operation of specialized registers
- Analyse some circuits using shift registers: 74LS164 and 74LS194
- Design circuits using shift registers: 74LS164 and 74LS194

Materials Needed
- 8-Bit Serial-Input/Parallel-Output Shift Register: 74LS164
- 4-Bit Bidirectional Universal Shift Register: 74LS194
For further investigation:
Materials to be determined by student.

Presentation and Multisim:

On Tuesdays (Group 1: P1b; Group 3: P1c; Group 4: P2b; Group 5: P2c; Group 6: P2d)
On Thursdays (Group 1: P2a; Group 2: P1; Group 3: P2b; Group 4: P2c; Group 5: P2d)

Procedures

P1. 8-bit serial input/parallel –output shift register 74LS164

The 74LS164 is an 8 bit shift register with serial data entry and an output from each of the
eight stages. Data is entered serially through one of two inputs (A or B), either of these inputs
can be used as an active high enable for data entry through the other input. An unused input
must be high, or both inputs connected together.

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Figure 1: Shift register 74LS164

a. The operation of shift register 74LS164

74LS164

SW1 1
A Q0
3
SW2 2
B Q1
4
5
Q2
1Hz 8
CLK Q3
6
10
Q4
SW3 9
CLR Q5
11
12
Q6 13
Q7

Figure 2: The operation of shift register 74LS164

- Implement the circuit shown in Figure 2:

 Connect A, B, CLR to switches

 Connect CLK to clock signal 1Hz

 Connect outputs to LEDs

- Check the active state of the signal CLR :

- Observe and explain the results:

- Draw the waveforms of the outputs when control SW1 = SW2 =1 in Figure 3

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CLK
1

CLR 0

1
Q0 0

Q1 0

Q2 0

Q3 0

Q4 0

Q5 0

Q6 0

Q7 0

Figure 3

b. Analyse the circuit using an IC 74LS164 and a NOT gate

74LS164

3
Q0 4
Q1
1Hz 8
CLK Q2
5
6
Q3
SW1 9
CLR Q4
10
11
Q5
SW2 1
A Q6
12
2 13
B Q7

0
74LS04

2 1

Figure 4
- Implement the circuit shown in Figure 4. Control SW1 to make the circuit operate.

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- Observe and explain the results:

c. Analyse the circuit using two IC 74LS164 and a NOT gate shown

74LS164 74LS164

3 3
Q0 Q0
1Hz 8
CLK Q1
4 8
CLK Q1
4
5 5
Q2 Q2
SW1 9
CLR Q3
6 SW3 9
CLR Q3
6
10 10
Q4 Q4
SW2 1
A Q5
11 SW4 1
A Q5
11
12 12
2 Q6 13 2 Q6 13
B Q7 B Q7

0 0
74LS04

2 1

Figure 5
- Implement the circuit shown in Figure 5. Control SW1, SW3 to make the circuit operate.
- Observe and explain the result:

P2. 4-Bit bidirectional universal shift register 74LS194

Figure 6: Connection diagram of 74LS164

This bidirectional shift register is designed to incorporate virtually all of the features a
system designer may want in a shift register; they feature parallel inputs, parallel outputs, right-
shift and left-shift serial inputs, operating-mode-control inputs, and a clear input.
The register has four distinct modes of operation:
 Parallel (broadside)
 Load Shift right (in the direction QA toward QD)

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 Shift left (in the direction QD toward QA)
 Inhibit clock (do nothing)
Synchronous parallel loading is accomplished by applying the four bits of data and taking
both mode control inputs: S0 = S1 = HIGH. The data is loaded into the associated flip-flops and
appear at the outputs after the positive transition of the clock input. During loading, serial data
flow is inhibited.
Shift right is accomplished synchronously with the rising edge of the clock pulse when S 0 =
HIGH and S1 = LOW. Serial data for this mode is entered at the shift-right data input.
When S0 = LOW and S1 = HIGH, data shifts left synchronously and new data is entered at
the shift-left serial input.
When S0 = LOW and S1 = LOW, the register will be in the fourth mode: inhibit clock means
that do nothing.

Table 1

- H stands for HIGH Level (steady state)

- L describes LOW Level (steady state)
- X means Don’t Care (any input or transitions)
- indicates transition from LOW-to-HIGH level
- abcd are the level of steady state inputs ABC D, respectively.
- QA0 QB0 QC0 QD0 is the level of QA QB QC QD, respectively, before the indicated steady
state input conditions were established.
- QAn QBn QCn QDn is the level of QA QB QC QD, respectively, before the most-recent
transition of the clock.
The sample timing diagram for a 74LS194 shift registers is shown in Figure 7
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Figure 7: Sample timing diagram for a 74LS194 shift register

a. The operation of shift register 74LS194

74LS194

SW5 7
SL QA
15
SW6 2
SR QB
14
13
QC
SW1 3
A QD
12
SW2 4
B
SW3 5
C
SW4 6
D 0
1Hz 11
CLK
SW7 1
CLR
SW8 9
S0
SW9 10
S1

Figure 8: The operation of shift register 74LS194

- Implement the circuit shown in Figure 8 as follows

 The outputs QAQBQCQD are connected to LEDs
 Connect CLK to clock signal 1Hz

 CLR , S0, and S1 are connected to switches for controlling the operation.
 Set inputs ABCD on 0001, respectively.
 Verify the functions: Hold, Load, Shift Left, and Shift Right.
- Hold:

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- Load:
- Shift Left:
- Shift Right:

b. Ring counter using shift register 74LS194

- Implement the shift right circuit as the ring counter shown in Figure 9
 Set inputs DCBA on 0001, respectively.

11
CLOCK 1 CLK 15
SW1 CLR QA 14
3 QB 13
4 A QC 12
5 B QD
6 C
SW4,5,6,7 D
7 LED_DISPLAY
2 SL
SR
10
SW2 9 S1
SW3 S0

74LS194

Figure 9: Ring counter using shift register 74LS194

- Present the way to control S0 and S1 so as to the circuit can reset or load data into the
register and shift data to the right.

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- Draw the output waveforms QD QC QB QA in Figure 10

CLK

QA

QB

QC

QD

Figure 10

c. Johnson counter using shift register 74LS194

U26A 7404
2 1

U25
11
CLK SW CLK 15
7 QA
2 SL 14
SR QB
13
SW 2-5 QC
3
4 A 12
5 B QD
6 C
D LED DISPLAY
74194

9
SW6 S0
10
CLR

SW7 S1
1

SW8

Figure 11: Johnson counter using shift register

- Implement the circuit shown in Figure 11
- Load ABCD are equal to 0000, respectively.

- Control the inputs CLR , S1, S0 in order to the circuit operate properly
- Observe and explain the results

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- Draw the output waveforms QD QC QB QA in Figure 12

CLK

QA

QB

QC

QD

Figure 12

d. Shift-register 74LS194 with XOR feedback function

- Set the register in the shift right operation.
- Implement the shift register having feedback function ffb = QD  QA
- Draw the circuit appropriately in Figure 13

Figure 13: Shift register with XOR feedback function

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- Draw the state diagram of the circuit in Figure 14

0001

Figure 14

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