Hi3798M V200 Data Sheet 01-General Information

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Hi3798M V200 Data Sheet

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General Information
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Copyright © HiSilicon Technologies Co., Ltd. 2017. All rights reserved.
No part of this document may be reproduced or transmitted in any form or by any means without prior
written consent of HiSilicon Technologies Co., Ltd.
Trademarks and Permissions
, , and other HiSilicon icons are trademarks of HiSilicon Technologies Co., Ltd.
All other trademarks and trade names mentioned in this document are the property of their respective
holders.
Notice
The purchased products, services and features are stipulated by the contract made between HiSilicon and
the customer. All or part of the products, services and features described in this document may not be
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within the purchase scope or the usage scope. Unless otherwise specified in the contract, all statements,
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information, and recommendations in this document are provided "AS IS" without warranties, guarantees
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or representations of any kind, either express or implied.
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The information in this document is subject to change without notice. Every effort has been made in the
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preparation of this document to ensure accuracy of the contents, but all statements, information, and
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recommendations in this document do not constitute a warranty of any kind, express or implied.
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HiSilicon Technologies Co., Ltd.

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Address: New R&D Center, Wuhe Road,

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Bantian, Longgang District,

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Shenzhen 518129 P. R. China

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Website: http://www.hisilicon.com
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Email: support@hisilicon.com
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General Information About This Document
About This Document
Purpose
The following table describes the content of the Hi3798M V200 Data Sheet. The highlighted
portion outlines information contained in this document.
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Document No. Document Name Description
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Hi3798M V200 Data Sheet 01 General Information Product Overview
02
z
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z Boot Mode
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z Address Space Mapping
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z Soldering Process
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z Moisture-Sensitive Specifications
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z Ordering Information
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z Acronyms and Abbreviations
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Hi3798M V200 Data Sheet 02 Hardware z Package and Pins
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z Electrical Characteristics
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z Recommendations on Schematic
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z PCB Design Recommendations

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z Thermal Design Recommendations

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z Interface Timings
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Hi3798M V200 Data Sheet 03 System z Processor Subsystem

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z Security Subsystem
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z Always-on area subsystem

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z Power Management and Low-Power

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Control
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z Reset
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Clock
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z System Controller
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z Interrupt System
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z Timer
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z 64-bit Timer
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z WDG
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HiSilicon Proprietary and Confidential

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Copyright © HiSilicon Technologies Co., Ltd.

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Document No. Document Name Description

z DMAC
Hi3798M V200 Data Sheet 04 Peripherals z DDRC
z FMC
z MMC/SD/SDIO Controller
z GPIO
z UART
z I2C
z IR
z KEYLED
z SCI
z SPI
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z USB 2.0
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z USB 3.0
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z PCIe
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z SATA
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z LSDAC
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Hi3798M V200 Data Sheet 05 Data Stream/Graphics z ETH
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Processing/Audio/Vide
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z GMAC
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z Video Encoder
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z Video Decoder
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z HWC
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z HDMI TX
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Related Version
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The following table lists the product version related to this document.
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Product Name Version

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Hi3798M V2XX
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Intended Audience
This document is intended for:
z Technical support engineers
z Software development engineers
Change History
Changes between document issues are cumulative. Therefore, the latest document issue
contains all changes made in previous issues.
Issue 00B03 (2017-02-28)

This issue is the third draft release, which incorporates the following change:
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modified.
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Issue 00B02 (2017-01-15)
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This issue is the second draft release, which incorporates the following changes:
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Chapter 4 and chapter 5 are modified.
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This issue is the first draft release.

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General Information Contents
Contents
About This Document ......................................................................................................................i

1 Product Overview ......................................................................................................................... 1
1.1 Application Scenario ........................................................................................................................................ 1
1.2 Architecture ...................................................................................................................................................... 2
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1.2.1 Master Processor ..................................................................................................................................... 2
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1.2.2 3D Engine ............................................................................................................................................... 3
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1.2.3 Security Processing ................................................................................................................................. 3
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1.2.4 Memory Interfaces .................................................................................................................................. 3
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1.2.5 Data Stream Interfaces ............................................................................................................................ 4
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1.2.6 Video Codec (HiVXE 2.0 Processing Engine) ........................................................................................ 5
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1.2.7 Graphics and Display Processing (Imprex 2.0 Processing Engine) ........................................................ 5
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1.2.8 Audio/Video Interfaces ........................................................................................................................... 6
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1.2.9 Peripheral Interfaces ............................................................................................................................... 6
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1.2.10 Low-Power Control .............................................................................................................................. 8

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2 Boot Mode ...................................................................................................................................... 9

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3 Address Space Mapping ............................................................................................................ 11

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4 Soldering Process Recommendations ..................................................................................... 16

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4.1 Overview ........................................................................................................................................................ 16

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4.2 Requirements on Parameters of the Lead-Free Reflow Soldering Process .................................................... 16

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4.3 Requirements of Mixing Reflow Soldering ................................................................................................... 19

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5 Moisture-Sensitive Specifications ........................................................................................... 21

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5.1 Overview ........................................................................................................................................................ 21

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5.2 HiSilicon Moisture-Proof Packaging ............................................................................................................. 21

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5.2.1 Basic Information.................................................................................................................................. 21

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5.2.2 Incoming Inspection.............................................................................................................................. 22

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5.3 Storage and Usage .......................................................................................................................................... 22

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5.4 Rebaking ........................................................................................................................................................ 23

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6 Ordering Information................................................................................................................. 25
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7 Acronyms and Abbreviations ................................................................................................... 27

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General Information Figures
Figures
Figure 1-1 Application block diagram ................................................................................................................... 2

Figure 2-1 Boot process ...................................................................................................................................... 10
Figure 4-1 Curve of the lead-free reflow soldering process ................................................................................ 17
Figure 4-2 Measuring the package temperature .................................................................................................. 19
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Figure 5-1 Vacuum packaging materials ............................................................................................................. 22
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Figure 6-1 Chip mark naming convention ........................................................................................................... 25
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General Information Tables
Tables
Table 3-1 Address space mapping ....................................................................................................................... 11

Table 4-1 Parameters of the lead-free reflow soldering process .......................................................................... 17
Table 4-2 Temperature resistance standard for the lead-free package according to IPC/JEDEC 020D ............... 18
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Table 4-3 Mixing reflow soldering parameters .................................................................................................... 19
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Table 4-4 Thermal resistance standard for the lead package ............................................................................... 20
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Table 5-1 Floor life .............................................................................................................................................. 23
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Table 5-2 Rebaking reference.............................................................................................................................. 23
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Table 6-1 Packages .............................................................................................................................................. 26
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General Information 1 Product Overview
1 Product Overview
1.1 Application Scenario
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Hi3798M V200 is a full-4K high-performance SoC that supports 4Kp60 decoding for the
Internet Protocol television (IPTV)/over-the-top (OTT) STB markets. It integrates the 4-core
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64-bit high-performance Cortex A53 processor and multi-core high-performance 2D/3D
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acceleration engine. Besides, it supports H.265 4K x 2K@P60 10-bit ultra-HD video
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decoding, high-performance H.265 HD video encoding, HDR video decoding and display,
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HDR-to-SDR conversion, and BT.2020, Dolby, and DTS audio processing. Hi3798M V200
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also provides rich internal peripheral interfaces, such as USB 2.0, USB 3.0, SDIO 3.0, and
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PCIe 2.0 interfaces. These features help customers implement full-4K service deployment,
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and enable Hi3798M V200 to provide the best user experience in the industry in terms of
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picture quality, stream compatibility, video playback smoothness, and STB performance and
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meet the requirements of continuously increasing value-added services such as video
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communication, karaoke, cloud game, and multi-screen interaction.

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Figure 1-1 Application block diagram
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1.2 Architecture
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Hi3798M V200 has the following features:

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z Master processor
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z 3D engine
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z Security processing
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z Memory interfaces
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z Data stream interfaces

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z Video codec
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z Graphics and display processing

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z Audio/Video interfaces
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z Peripheral interfaces
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z Low-power control
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1.2.1 Master Processor

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Hi3798M V200 integrates a quad-core ARM Cortex A53 processor as the master CPU to
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implement system functions and some audio and video processing tasks. This processor has
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the following features:

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z Independent 32 KB I-cache and 32 KB D-cache, 512 KB shared L2 cache

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z Integrated NEON
z Dynamic power consumption reduction such as dynamic voltage and frequency scaling
(DVFS) and adaptive voltage scaling (AVS)
1.2.2 3D Engine
Hi3798M V200 integrates the high-performance quad-core Mali GPU to process 3D graphics
and videos.
z OpenGL ES 2.0/1.1/1.0
z OpenVG 1.1
z 1080p30 UI processing capability
z 1080p@30 gaming applications
1.2.3 Security Processing
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Hi3798M V200 has the following advanced security features:
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z Trusted execution environment (TEE)
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z Secure video path (SVP)
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z Secure storage
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z Secure upgrade
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z Protection for Joint Test Action Group (JTAG) and other debugging ports
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z One-time programmable (OTP)
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z Digital rights management (DRM)
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z Downloadable conditional access (CA) (DCAS)

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z HDCP 2.2/1.4 protection for HDMI outputs

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1.2.4 Memory Interfaces

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Hi3798M V200 provides the DDR SDRAM controller (DDRC), SDIO/MMC controller, and
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flash memory controller (FMC) that supports the SPI NOR, SPI NAND, and NAND flash.
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DDRC
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The DDRC controls the access to the dynamic DDR3/DDR3L/DDR4 SDRAM. It supports
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the following features:

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z Maximum 2 GB capacity
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z 32-bit memory
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z Maximum 1066 MHz frequency

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z Standby power-down
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The FMC provides memory controller interfaces for connecting to external SPI NAND flash,
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SPI NOR flash, or synchronous and asynchronous NAND flash to access data. It supports the
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following features:
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z Supports one external CS (SPI NAND flash, SPI NOR flash, or NAND flash).
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z Supports the SPI NOR flash, SPI NAND flash, and NAND flash.
z Supports five types of SPIs, including the standard SPI, dual-output/dual-input SPI,
quad-output/quad-input SPI, dual I/O SPI, and quad I/O SPI.
z Supports the SPI NAND flash with the following specifications:
− 2 KB or 4 KB page size
− 64/128 pages/block
z Supports the NAND flash with the following specifications:
− 2 KB, 4 KB, 8 KB, or 16 KB page size
− 64/128/256/512 pages/block
− 8-bit width
− Components with the DDR interface or asynchronous interface, and Toggle 1.0/2.0,
ONFI 2.3, and ONFI 3.0 components
z Supports the error checking and correction (ECC) function for the SPI NAND flash and
NAND flash.
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− 8-bit/1 KB, 16-bit/1 KB, 24-bit/1 KB, 28-bit/1 KB, 40-bit/1 KB, and 64-bit/1 KB
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Bose-Chaudhuri-Hocquenghem (BCH) code ECC (1 KB means the 1 KB level but
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not exactly 1024 bytes.)
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Enable and disable of the ECC function and ECC code generation
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z Supports the randomizer only in non-ECC0 mode when the page size is 8 KB or 16 KB.
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It is disabled in other modes.
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MMC/SD/SDIO Controller
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Hi3798M V200 integrates three high-speed large-capacity SDIO 3.0/MMC 5.0 controllers to
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control the access to the MMC/SD card. Extended peripherals such as Bluetooth and Wi-Fi
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devices can be connected over the SDIO interface.

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Two controllers support the 1-/4-bit mode, and the other one supports the 1-/4-/8-bit mode for
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booting from the eMMC.

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1.2.5 Data Stream Interfaces

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The data stream interfaces of Hi3798M V200 include the Ethernet port and transport stream
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interface (TSI).
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Ethernet Port
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Hi3798M V200 provides one Ethernet controller (ETH for short), integrates one 10 Mbit/s or
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100 Mbit/s PHY, and provides a megabit Ethernet media access control (MAC) and a gigabit
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Ethernet MAC.
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One 10/100 Mbit/s PHY interface or one RGMII/RMII

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z 10/100/1000 Mbit/s (gigabit MAC), half-duplex or full-duplex mode

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z Embedded 10/100 Mbit/s PHY, supporting the EEE function

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z Configurable destination MAC address filtering table, which filters the input frames of
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the Ethernet port

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z Traffic control of the CPU interface, protecting the CPU against heavy traffic
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TSI
Hi3798M V200 integrates a TSI controller, which has the following features:
z Parsing and demultiplexing of MPEG2 TSs complying with the standards of the ISO
13818-1 (GB 17975-1) system layer
z At most one external standard serial TS input and one external standard serial TS
input/output
z Playback of 3-channel TSs from the memory
z Maximum 96 hardware PID channels, processing at most 5-channel TSs at the same time
1.2.6 Video Codec (HiVXE 2.0 Processing Engine)

Hi3798M V200 integrates the HD video and graphics codec that supports various protocols
(H.265/VP9/H.264/AVS+/MVC/VC-1/MPEG-2/MPEG-4/AVS/VP6/VP8/JPEG/PNG),
providing powerful video and graphics encoding and decoding capabilities.
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z H.265/HEVC Main/Main 10 Profile@Level 5.1 high-tier, maximum 4K x 2K@60 fps
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decoding capability
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z H.264/AVC BP/MP/HP@Level 5.1; H.264/AVC MVC, maximum 4K x 2K@30 fps
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decoding capability
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z Maximum 4K x 2K@60 fps 10-bit VP9 decoding capability
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z Maximum 1080p@60 fps VP6/8 decoding capability
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z Maximum 1080p@60 fps MPEG-1 decoding capability
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z Maximum 1080p@60 fps MPEG-2 SP@ML, MP@HL decoding capability
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MPEG-4 SP@Levels 0–3, ASP@Levels 0–5, GMC, short header format, maximum
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1080p@60 fps decoding capability
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z AVS Baseline Profile@Level 6.0, AVS-P16 (AVS+), maximum 1080p@60 fps decoding
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capability
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z VC-1 SP@ML, MP@HL, AP@Levels 0–3, maximum 1080p@60 fps decoding

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capability
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z Maximum 1080p@60 fps Real8/9/10 decoding capability

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z Full HD JPEG Baseline decoding, up to 64 megapixels

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z MJPEG Baseline decoding, maximum 1080p@40 fps decoding capability

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z PNG decoding, maximum 64 megapixels

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H.265 MP@Level 5.1 and H.264 BP/MP/HP@Level 4.2 video encoding, maximum
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1080p@30 fps encoding or 2-channel 720p@30 fps encoding capability
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z JPEG Baseline encoding, maximum 1080p@30 fps encoding capability

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z VBR or CBR mode for video encoding

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1.2.7 Graphics and Display Processing (Imprex 2.0 Processing

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Engine)
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Hi3798M V200 integrates the dedicated two dimensional engine (TDE), dedicated multi-layer
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graphics or video overlaying engine (hardware composer engine), and dedicated display
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processing engine.
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z Hardware overlaying of multiple graphics and video inputs

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z 3-layer on-screen display (OSD) and three video layers

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z Maximum 4K x 2K image output

z Mosaic and multi-region display
z Mirroring
z 16-bit or 32-bit color depth
z Graphics and video rotation
z LetterBox and PanScan
z 3D video processing and display
z Multi-order vertical and horizontal scaling of videos and graphics as well as free scaling
z Low-delay display
z Enhanced full-hardware TDE
z Full-hardware anti-aliasing and anti-flicker
z Color space conversion (CSC) with configurable coefficients (including BT.2020)
z Image enhancement and noise reduction
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z De-interlacing
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z Sharpening
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z Chrominance, luminance, contrast, and saturation adjustment
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z Db/Dr processing for graphics and videos
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z HDR
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1.2.8 Audio/Video Interfaces
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Hi3798M V200 integrates various audio/video input/output interfaces, providing rich
audio/video input/output capabilities.
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Video Output Interfaces

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z One 4Kp60 or 1920 x 1080p@60 fps output+one SD output from the same source
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z One HDMI 2.0a TX output, supporting HDCP 2.2/1.4, maximum 4K x 2K resolution

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z One embedded digital-to-analog converter (DAC), supporting one composite video

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broadcast signal (CVBS) output

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Rovi and vertical blanking interval (VBI) video output

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Audio Input and Output Interfaces

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z Sony/Philips digital interface format (S/PDIF) audio output interface

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z One embedded DAC, which supports audio-left and audio-right channels (output
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interface of the RCA type, low impedance, and imbalance)

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z One inter-IC sound (I2S) or pulse code modulation (PCM) digital audio inputs/output
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z One HDMI TX audio output

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1.2.9 Peripheral Interfaces

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Hi3798M V200 integrates diverse peripheral interfaces for connecting to various peripherals
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or extending system functions.

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IR Interface
Hi3798M V200 integrates a dedicated infrared (IR) remote control RX unit, which receives
IR data through an IR interface and has the following features:
z Flexible configuration for decoding data in various formats
z Error check on received data
z IR remote wakeup
z One input interface
LED/Keypad Controller
Hi3798M V200 integrates the LED/keypad controller for controlling the LED display and key
scanning.
USB Controller
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Hi3798M V200 integrates two USB 2.0 controllers and supports one USB 3.0 controller.
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z The USB 2.0 controller supports the host function and Android debug bridge (ADB)
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debugging (USB0).
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z The USB 2.0 controller support the low-speed and high-speed modes and extended hub.
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z The USB 3.0 controller is backward compatible with USB 2.0.
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PCIe Controller
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Hi3798M V200 integrates one PCIe controller (PCIe for short) for extending the Wi-Fi
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devices.
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SATA Controller
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Hi3798M V200 integrates one SATA 3.0 controller for connecting to the SATA hard disk or
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extending the eSATA device.

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GPIO Controller
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Hi3798M V200 integrates multiple groups of GPIO controllers. Each group provides eight
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programmable input/output pins.

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z Each GPIO pin can be configured as an input or output.

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z As an input pin, the GPIO can act as an interrupt source.

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As an output pin, the GPIO can be independently set to 1 or 0.

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z
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UART
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Hi3798M V200 integrates three universal asynchronous receiver transmitters (UARTs) for
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debugging, controlling, or extending external devices, such as the Bluetooth and keyboard.
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One of them is a 2-line interface, and the other two are 4-line interfaces.
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I2C Controller
Hi3798M V200 integrates three inter-integrated circuit (I2C) controllers, which serve as
standard master I2C devices to transmit/receive data to/from the slave devices over the I2C bus.
SCI
Hi3798M V200 integrates a smart card interface (SCI) controller and provides two SCIs that
support the ISO/IEC 7816-3, ISO/IEC 7816-10 protocols and T0, T1, and T14 asynchronous
transmission protocols. The CPU reads data from or writes data to the smart card through the
SCI and implements serial-to-parallel conversion (when it reads data from the smart card) and
parallel-to-serial conversion (when it writes data to the smart card).
1.2.10 Low-Power Control

Hi3798M V200 supports various low-power modes to dynamically reduce power
consumption.
圳
1深
z Various system operating modes, including the normal mode, light standby mode, and
deep standby mode
02
PC
z Module-level low-power control
0S
z DVFS based on CPU load monitoring
C0
01
z AVS based on CPU timing monitoring
R0
z Ultra-low-power standby design, including various standby wakeup modes, such as
00
remote control wakeup and key wakeup
V8
id
ro
nd
BA
ST
Hi
司
公
限
有
技
科
诺
淇
圳
1深
02
PC
0S
C0
01
R0
00
V8
id
ro
nd
BA
ST
Hi
司
公
限
有
技

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Issue 00B03 (2017-02-28) 8

诺

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圳
深
General Information 2 Boot Mode
2 Boot Mode
After the chip is powered on, the system is reset. After the reset is deasserted, the CPU jumps
to the internal BOOTROM space to execute the boot process. After the internal BOOTROM
圳
boot program is executed, if the external pin USB_BOOT is low level, the chip directly boots
1深
from the USB port; otherwise, the chip boots from an external memory.
02
PC
Hi3798M V200 can store the U-boot program in any of the following off-chip memories:
0S
C0
z SPI NOR flash
01
z Asynchronous NAND flash
R0
00
z Synchronous NAND flash
V8
z SPI NAND flash
id
ro
z eMMC nd
BA
ST
Hi
司
公
限
有
The USB_BOOT pin is pulled high by using its internal resistor by default.
技
科
The boot_sel pin determines the flash memory from which the chip boots. Figure 2-1 shows
诺
the process.
淇
圳
1深
02
PC
0S
C0
01
R0
00
V8
id
ro
nd
BA
ST
Hi
司
公
限
有
技

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Issue 00B03 (2017-02-28) 9

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淇
圳
深
General Information 2 Boot Mode
Figure 2-1 Boot process
Power on the chip.
The CPU starts to execute the

instructions after the reset is
deasserted.
Execute the boot program in the

on-chip BOOTROM.
Is USB_BOOT 0?
No
Boot from the Does the chip boot from an
Yes
eMMC. off-chip eMMC?
圳
No
1深
Yes
02
SPI NOR flash. off-chip SPI NOR flash?
PC
Yes
No
0S
C0
Yes
01
SPI NAND flash. off-chip SPI NAND flash?
R0
00
No
V8
id
ro
nd
BA
Boot from the NAND flash.

ST
Hi
司
公
The boot process is

限
USB bootstrap
complete.
有
技
科
诺
淇
圳
1深
02
PC
0S
C0
01
R0
00
V8
id
ro
nd
BA
ST
Hi
司
公
限
有
技

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Issue 00B03 (2017-02-28) 10

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淇
圳
深
General Information 3 Address Space Mapping
3 Address Space Mapping
Table 3-1 describes the address space mapping of Hi3798M V200.
圳
1深
Table 3-1 Address space mapping
02
Start Address End Address Object Size (Unit: Byte) Remarks
PC
0S
0x0000_0000 0x7FFF_FFFF DRAM 2G -
C0
01
0x8000_0000 0xEFFF_FFFF Reserved space 1.75G
R0
00
0xF000_0000 0xF000_1FFF PCIe0 register space 8K
V8
id
0xF000_2000 0xF0FF_FFFF Reserved space 16376K
ro
nd
Generic interrupt controller
0xF100_0000 0xF100_FFFF 64K
BA
(GIC) register space

ST
Hi
0xF101_0000 0xF1FF_FFFF Reserved space 16320K

司
公
PCIe0 memory and

0xF200_0000 0xF4FF_FFFF 48M
限
configuration space
有
技
0xF500_0000 0xF7FF_FFFF Reserved space 48M

科
诺
0xF800_0000 0xF800_0FFF System control register 4K -

淇
圳
0xF800_1000 0xF800_1FFF IR register 4K -

1深
0xF800_2000 0xF800_2FFF Timer 0/Timer 1 register 4K -

02
PC
0xF800_3000 0xF800_3FFF LEDC register 4K -

0S
C0
0xF800_4000 0xF800_4FFF GPIO5 register 4K -

01
R0
0xF800_5000 0xF800_7FFF Reserved space 12K -

00
V8
0xF800_8000 0xF800_8FFF SEC timer 0/timer 1 register 4K

id
ro
0xF800_9000 0xF800_9FFF SEC timer 2/timer 3 register 4K

nd
BA
0xF800_A000 0xF83F_FFFF Reserved space 4056K -

ST
Hi
0xF840_0000 0xF840_FFFF 8051 local RAM 64K -

司
公
限
有
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Issue 00B03 (2017-02-28) 11

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圳
深
0xF841_0000 0xF8A1_FFFF Reserved space 6208K

0xF8A2_0000 0xF8A2_0FFF PERI_CTRL register 4K -
0xF8A2_1000 0xF8A2_1FFF IO_CONFIG register 4K -
0xF8A2_2000 0xF8A2_2FFF CRG register 4K -
0xF8A2_3000 0xF8A2_3FFF PMC register 4K -
0xF8A2_4000 0xF8A2_8FFF Reserved space 20K
0xF8A2_9000 0xF8A2_9FFF Timer 2/Timer 3 register 4K -
0xF8A2_A000 0xF8A2_AFFF Timer 4/Timer 5 register 4K -
0xF8A2_B000 0xF8A2_BFFF Timer 6/Timer 7 register 4K -
圳
0xF8A2_C000 0xF8A2_CFFF WDG0 register 4K -
1深
02
0xF8A2_D000 0xF8A2_DFFF WDG1 register 4K -
PC
0S
0xF8A2_E000 0xF8A2_FFFF Reserved space 8K
C0
01
0xF8A3_0000 0xF8A3_FFFF MDDRC0 register 64K -
R0
00
0xF8A4_0000 0xF8A7_FFFF Reserved space 256K
V8
id
0xF8A8_0000 0xF8A8_0FFF SEC_CFG register 4K -
ro
nd
0xF8A8_1000 0xF8A8_1FFF Reserved space 4K -
BA
ST
PASTC register (only

Hi
0xF8A8_2000 0xF8A8_2FFF opened in the internal 4K

司
version)
公
限
0xF8A8_3000 0xF8A8_FFFF Reserved space 52K

有
技
0xF8A9_0000 0xF8A9_FFFF MKL 64K -

科
诺
0xF8AA_0000 0xF8AA_FFFF Reserved space 64K

淇
圳
0xF8AB_0000 0xF8AB_FFFF OTP register 64K -

1深
0xF8AC_0000 0xF8AF_FFFF Reserved space 256K

02
PC
0xF8B0_0000 0xF8B0_0FFF UART0 register 4K -

0S
C0
0xF8B0_1000 0xF8B0_1FFF Reserved space 4K -

01
R0

00
V8

id
ro
0xF8B0_4000 0xF8B0_FFFF Reserved space 48K -

nd
BA
0xF8B1_0000 0xF8B1_0FFF I2C0 4K -

ST
Hi
0xF8B1_1000 0xF8B1_1FFF I2C1 4K -

司
公
2
0xF8B1_2000 0xF8B1_2FFF I C2 4K -
限
有
技

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Issue 00B03 (2017-02-28) 12

诺

淇
圳
深
0xF8B1_3000 0xF8B1_7FFF Reserved space 20K -

0xF8B1_8000 0xF8B1_8FFF SCI0 register 4K -
0xF8B1_9000 0xF8B1_9FFF SCI1 register 4K -
0xF8B1_A000 0xF8B1_AFFF SPI0 register 4K
0xF8B1_B000 0xF8B1_FFFF Reserved space 20K
0xF8B2_0000 0xF8B2_0FFF GPIO0 register 4K -
圳
1深
02
0xF8B2_5000 0xF8B2_5FFF Reserved space 4K
PC
0S
C0
01
R0
00
V8
id
ro
nd
0xF8B2_A000 0xF8B3_6FFF Reserved space 48K
BA
ST
0xF8B3_7000 0xF8B3_FFFF Reserved space 36K

Hi
0xF8B4_0000 0xF8B4_FFFF GZIP register 64K

司
公
0xF8B5_0000 0xF8BA_FFFF Reserved space 384K

限
有
0xF8BB_0000 0xF8BB_FFFF System count register 64K

技
科
0xF8BC_0000 0xF8C0_FFFF Reserved space 320K

诺
淇
0xF8C1_0000 0xF8C1_EFFF TDE register 60K -

圳
1深
0xF8C1_F000 0xF8C1_FFFF TDE MMU register 4K

02
PC
0xF8C2_0000 0xF8C2_FFFF Reserved space 64K

0S
C0
Video decoder for high-

0xF8C3_0000 0xF8C3_EFFF 60K
01
definition (VDH) register

R0
00
0xF8C3_F000 0xF8C3_FFFF VDH MMU register 4K

V8
id
0xF8C4_0000 0xF8C4_EFFF JPGD0 register 60K -

ro
nd
0xF8C4_F000 0xF8C4_FFFF JPGD0 MMU register 4K -

BA
ST
0xF8C5_0000 0xF8C6_FFFF Reserved space 128K

Hi
司
0xF8C7_0000 0xF8C7_EFFF PGD register 60K -

公
限
有
技

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Issue 00B03 (2017-02-28) 13

诺

淇
圳
深
0xF8C7_F000 0xF8C7_FFFF PGD MMU register 4K -

Video encoding/decoding -
0xF8C8_0000 0xF8C8_EFFF 60K
unit (VEDU) register
0xF8C8_F000 0xF8C8_FFFF VEDU MMU register 4K -
JPEG encoder (JPGE) -
0xF8C9_0000 0xF8C9_FFFF 64K
register
0xF8CA_0000 0xF8CA_FFFF Reserved space 64K
0xF8CB_0000 0xF8CB_EFFF VPSS0 register 60K -
0xF8CB_F000 0xF8CB_FFFF VPSS0 MMU register 4K -
Video display processor -
0xF8CC_0000 0xF8CC_EFFF 60K
圳
(VDP) register
1深
0xF8CC_F000 0xF8CC_FFFF VDP MMU register 4K -
02
PC
0xF8CD_0000 0xF8CD_FFFF AIAO register 64K -
0S
C0
0xF8CE_0000 0xF8CF_FFFF HDMI_TX register 128K -
01
R0
0xF8D0_0000 0xF8D2_FFFF Reserved space 192K -
00
V8
0xF8D3_0000 0xF8D3_0FFF HDMI_TX PHY register 4K
id
ro
0xF8D3_0000 0xF91F_FFFF Reserved space 4924K nd
BA
0xF920_0000 0xF923_FFFF GPU register 256K

ST
Hi
0xF924_0000 0xF981_FFFF Reserved space 6012K

司
公
0xF982_0000 0xF982_FFFF SDIO0 register 64K -

限
有
SDIO2/eMMC/SD card -
0xF983_0000 0xF983_FFFF 64K
技
register
科
诺
0xF984_0000 0xF984_FFFF GMAC register 64K -

淇
圳

1深
PCIe0 protection control

02
0xF986_0000 0xF986_0FFF 4K
PC
register
0S
C0
0xF986_1000 0xF986_4FFF Reserved space 16K

01
0xF986_5000 0xF986_5FFF USB2 PHY01 register 4K

R0
00
0xF986_6000 0xF986_FFFF Reserved space 40K -

V8
id
0xF987_0000 0xF987_FFFF DMAC register 64K

ro
nd
USB2 host0 open host -

BA
ST
0xF988_0000 0xF988_FFFF controller interface (OHCI) 64K

Hi
register
司
公
限
有
技

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Issue 00B03 (2017-02-28) 14

诺

淇
圳
深
USB2 host0 enhanced host -

0xF989_0000 0xF989_FFFF controller interface (EHCI) 64K
register
0xF98A_0000 0xF98A_FFFF USB3_0 register 64K -
0xF98B_0000 0xF98B_FFFF Reserved space 64K -
0xF98C_0000 0xF98F_FFFF USB2 OTG0 register 256K -
0xF990_0000 0xF990_FFFF SATA register 64K
0xF995_0000 0xF995_FFFF FMC register 64K -
0xF996_0000 0xF996_0FFF USB2 PHY2 register 4K
圳
1深
0xF996_1000 0xF99E_FFFF Reserved space 572K -
02
0xF99F_0000 0xF99F_0FFF Multi-cipher MMU register 4K -
PC
0S
0xF99F_1000 0xF99F_FFFF Reserved space 60K -
C0
01
0xF9A0_0000 0xF9A0_FFFF Multi-cipher register 64K -
R0
00
0xF9A1_0000 0xF9A1_FFFF SHA1 (secure) register 64K -
V8
id
0xF9A2_0000 0xF9A2_FFFF SHA2 (non-secure) register 64K -
ro
nd
0xF9A3_0000 0xF9A3_0FFF RSA register 4K
BA
ST
0xF9A3_1000 0xF9BF_FFFF Reserved space 1916K

Hi
司
Personal video recording 0 -

0xF9C0_0000 0xF9C0_FFFF 64K
公
(PVR0) register
限
有
0xF9C1_0000 0xF9C2_FFFF Reserved space 128K -

技
科
0xF9C3_0000 0xF9C3_FFFF ETH register 64K -

诺
淇
0xF9C4_0000 0xF9C4_FFFF SDIO1 register 64K -

圳
1深
0xF9C5_0000 0xFE1F_FFFF Reserved space 69M -

02
0xFE20_0000 0xFE2F_FFFF FMC memory space register 1M

PC
0S
0xFE30_0000 0xFFFD_FFFF Reserved space 29654K

C0
01
BOOTRAM register (in -

R0
0xFFFE_0000 0xFFFE_FFFF remap mode) or reserved (in 64K

00
remap clear mode)

V8
id
BOOTROM register (in -

ro
nd
0xFFFF_0000 0xFFFF_FFFF remap mode) or BOOTRAM 64K

BA
(in remap clear mode)

ST
Hi
司
公
限
有
技

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Issue 00B03 (2017-02-28) 15

诺

淇
圳
深
General Information 4 Soldering Process Recommendations
4 Soldering Process Recommendations
4.1 Overview
圳
1深
[Objective]
02
This chapter provides the recommendations on basic settings of the zone temperatures when
PC
the surface mounting technology (SMT) of the HiSilicon chip is used on the client.
0S
C0
[Application Scope]
01
R0
HiSilicon Hi3798M V200
00
V8
[Basic Information]
id
ro
All HiSilicon products provided for clients comply with the Restriction of Hazardous
nd
Substances (RoHS). In the part number format HixxxxRBCVxxx, the letter R indicates RoHS.
BA
These products are lead-free. The lead-free technology and mixing technology are used for
ST
process control when the HiSilicon chip is used for reflow soldering on the client.
Hi
司
[Process Control for Reflow Soldering]

公
限
The definitions are as follows:

有
技
z HiSilicon chip: All HiSilicon chips provided for customers are lead-free RoHS-
科
compliant products.
诺
淇
z Lead-free technology: A technology in which the solder paste and all components
圳
(including the board, all ICs, capacitors, and resistors) are lead-free.
1深
02
PC
4.2 Requirements on Parameters of the Lead-Free Reflow

0S
C0
Soldering Process
01
R0
00
Figure 4-1 shows the curve of the lead-free reflow soldering process.
V8
id
ro
nd
BA
ST
Hi
司
公
限
有
技

科
Issue 00B03 (2017-02-28) 16

诺

淇
圳
深
Figure 4-1 Curve of the lead-free reflow soldering process
圳
1深
02
PC
0S
C0
01
R0
Table 4-1 describes parameters of the lead-free reflow soldering process.
00
V8
id
Table 4-1 Parameters of the lead-free reflow soldering process
ro
nd
Zone Duration Heating Rate Peak Cooling Rate
BA
Temperature
ST
Hi
Preheat zone (40°C– 60s–150s ≤ 2.0ºC/s (≤ - -

司
150°C or 104°F–302°F) 36ºF/s)

公
限
Uniform temperature 60s–120s < 1.0ºC/s (< - -

有
zone (150°C–200°C or 34ºF/s)

技
302°F–392°F)
科
诺
Reflow zone (greater than 60s–90s - 230ºC−260ºC -

淇
217°C or 423°F) (446ºF−500ºF)

圳
1深
Cooling zone (Tmax to - - - 1.0ºC/s (34ºF/s) ≤ Slope ≤

02
180°C or 356°F) 4.0ºC/s (39ºF/s)

PC
0S
C0
01
Note the following:

R0
00
z Preheat zone: The temperature range is 40°C–150°C (104°F–302°F), the heating rate is
V8
about 2°C/s (36°F/s), and the duration of this temperature zone is 60s–150s.
id
ro
z Uniform temperature zone: The temperature range is 150°C–200°C (302°F–392°F), the

nd
temperature is increased steadily, the heating rate is less than 1°C/s (34°F/s), and the
BA
zone duration is 60s–120s. (Note: Slow heating is required for this zone. Otherwise,
ST
improper soldering easily occurs.)

Hi
司
z Reflow zone: The temperature increases from 217°C (423°F) to Tmax, and then
公
decreases from Tmax to 217°C (423°F). The zone duration is 60s–90s.

限
有
技

科
Issue 00B03 (2017-02-28) 17

诺

淇
圳
深
z Cooling zone: The temperature decreases from Tmax to 180°C (356°F). The maximum
cooling rate is 4°C/s (39°F/s).
z It should take no more than 6 minutes for the temperature to increase from the 25°C
(77°F) ambient temperature to 250°C (482°F).
z The values on the reflow soldering curve shown in Figure 4-1 are recommended values.
The values need to be adjusted on the client as required.
z Typically, the duration of the reflow zone is 60s–90s. For the boards with great heat
capacity, the duration can be prolonged to 120s. For details about the requirements on
package thermal resistance, see the IPC/JEDEC J-STD-020D standard. For details about
the method of measuring the package temperature, see the JEP 140 standard.
Table 4-2 describes the temperature resistance standard for the lead-free package according to
IPC/JEDEC 020D.
Table 4-2 Temperature resistance standard for the lead-free package according to IPC/JEDEC
020D
圳
Package Temperature 1 Temperature 2 Temperature 3
1深
Thickness (Package Volume (Package Volume (Package Volume >
02
< 350 mm3 or 0.02 = 350–2000 mm3 or 2000 mm3 or 0.12
PC
in.3) 0.02–0.12 in.3) in.3)
0S
C0
< 1.6 mm (0.06 260°C (500°F) 260°C (500°F) 260°C (500°F)
01
R0
in.)
00
1.6 mm to 2.5 mm 260°C (500°F) 250°C (482°F) 245°C (473°F)
V8
id
(0.06 in. to 0.10
ro
in.) nd
BA
> 2.5 mm (0.10 250°C (482°F) 245°C (473°F) 245°C (473°F)

ST
in.)
Hi
司
公
限
The component soldering terminals (such as the solder ball and pin) and external heat sinks
有
are not considered for volume calculation.

技
科
The method of measuring the reflow soldering process curve is as follows:

诺
淇
According to the JEP140 standard, to measure the package temperature, you are advised to
圳
place the temperature measuring probe of the thermocouple close to the chip surface if the
1深
chip package is thin, or to drill a hole on the package surface and place the temperature
02
measuring probe of the thermocouple into the hole if the chip package is thick. The second
PC
method is recommended for all components because of the requirement on quantizing the
0S
component thickness. However, this method is not applicable if the chip package is too thin to
C0
drill a hole. See Figure 4-2.

01
R0
00
V8
id
ro
nd
BA
ST
Hi
司
公
限
有
技

科
Issue 00B03 (2017-02-28) 18

诺

淇
圳
深
Figure 4-2 Measuring the package temperature
Package temperature
measuring probe
BGA locations
To measure the temperature of the QFP-packaged chip, place the temperature measuring probe close to
pins.
圳
1深
4.3 Requirements of Mixing Reflow Soldering
02
PC
Lead-free components must be properly soldered during mixing reflow soldering. Table 4-3
0S
C0
describes mixing reflow soldering parameters.
01
R0
Table 4-3 Mixing reflow soldering parameters
00
V8
Zone Lead BGA Lead-free BGA Other Components
id
Preheat zone (40°C– Duration 60s–150s
ro
nd
150°C or 104°F–
BA
302°F) Heating up slope < 2.5°C/s (37°F/s)

ST
Hi
Uniform temperature Duration 30–90s

司
公
zone (150°C–183°C
Heating up slope < 1.0°C/s (34°F/s)
限
or 302°F–361°F)
有
技
Reflow zone (greater Peak temperature 210°C–240°C 220°C–240°C 210°C–245°C (410°F–

科
than 183°C or 361°F) (410°F–464°F) (428°F–464°F) 473°F)

诺
淇
Duration 30s–120s 60s–120s 30s–120s

圳
1深
Cooling zone (Tmax Cooling down slope 1.0ºC/s (34ºF/s) ≤ Slope ≤ 4.0ºC/s (39ºF/s)
to 150°C or 302°F)
02
PC
0S
C0
01
R0
The preceding parameter values are provided based on the soldering joint temperature. The maximum
00
and minimum soldering joint temperatures for the board must meet the requirements described in Table
V8
4-3.
id
ro
When the soldering curve is adjusted, the package thermal resistance requirements on the
nd
board components must be met. For details about the requirements on package thermal
BA
resistance, see the IPC/JEDEC J-STD-020D standard. For details about the method of
ST
measuring the package temperature, see the JEP 140 standard.

Hi
司
公
限
有
技

科
Issue 00B03 (2017-02-28) 19

诺

淇
圳
深
Table 4-4 describes the thermal resistance standard for the lead package according to the
IPC/JEDEC 020D standard.
Table 4-4 Thermal resistance standard for the lead package

Package Thickness Temperature 1 (Package Volume < Temperature 1 (Package Volume ≥
350 mm3 or 0.02 in.3) 350 mm3 or 0.02 in.3)
< 2.5 mm (0.10 in.) 235°C (455°F) 220°C (428°F)

≥ 2.5 mm (0.10 in.) 220°C (428°F) 220°C (428°F)
The component soldering terminals (such as the solder ball and pin) and external heat sinks
are not considered for volume calculation.
According to the JEP 140 standard, the method of measuring the temperature of the package
soldered with the mixing technology is the same as that for measuring the temperature of the
圳
1深
package soldered with the lead-free technology. For details, see section 4.2 "Requirements on
Parameters of the Lead-Free Reflow Soldering Process."
02
PC
0S
C0
01
R0
00
V8
id
ro
nd
BA
ST
Hi
司
公
限
有
技
科
诺
淇
圳
1深
02
PC
0S
C0
01
R0
00
V8
id
ro
nd
BA
ST
Hi
司
公
限
有
技

科
Issue 00B03 (2017-02-28) 20

诺

淇
圳
深
General Information 5 Moisture-Sensitive Specifications
5 Moisture-Sensitive Specifications
5.1 Overview
圳
1深
[Objective]
02
This chapter defines the usage principles for moisture-sensitive ICs to ensure that ICs are
PC
properly used.
0S
C0
[Application Scope]
01
R0
All HiSilicon products for external customers
00
V8
[Terminology]
id
ro
z Floor life: longest period during which a HiSilicon chip can be stored in the workshop
nd
below 30°C (86°F) and 60% relative humidity (RH), that is, the time from moisture
BA
barrier bag (MBB) unpacking to reflow soldering

ST
Hi
z Desiccant: a material for absorbing moisture and keeping the product dry
司
z Humidity indicator card (HIC): a card that indicates the humidity status
公
限
z Moisture sensitivity level (MSL): a level for measuring the moisture degree. The MSL of
有
this product is 3.
技
z MBB: a vacuum bag for protecting products against moisture

科
诺
z Solder reflow: reflow soldering

淇
z Shelf life: normal storage period of a product with the MBB

圳
1深
02
PC
5.2 HiSilicon Moisture-Proof Packaging

0S
C0
01
5.2.1 Basic Information

R0
00
The vacuum packaging materials include:

V8
id
z An HIC
ro
nd
z An MBB
BA
z Desiccant
ST
Hi
司
公
限
有
技

科
Issue 00B03 (2017-02-28) 21

诺

淇
圳
深
Figure 5-1 Vacuum packaging materials
圳
1深
02
PC
0S
5.2.2 Incoming Inspection
C0
01
R0
When the vacuum bag is unpacked before SMT in the factories of customers or outsourcing
00
vendors:
V8
id
z If the largest indicator dot of the HIC is not in blue or khaki, rebake the product by
ro
referring to Table 5-2. nd
z If the 10% RH dot of the HIC is in blue or khaki, the product is dry. In this case, replace
BA
ST
the desiccant and pack the product into a vacuum bag.

Hi
z If the 10% RH dot of the HIC is not in blue or khaki and the 5% RH dot is in red or light
司
green, the product has become damp. In this case, rebake the product according to Table
公
5-2.
限
有
技
科
5.3 Storage and Usage

诺
淇
圳
[Storage Environment]
1深
You are advised to use vacuum packaging for the product and store it below 30°C (86°F) and
02
PC
60% RH.
0S
[Shelf Life]
C0
01
Normal storage period of a product with the MBB

R0
00
Below 30°C (86°F) and 60% RH, the shelf life of the product with vacuum packaging is less
V8
than or equal to 12 months.

id
ro
[Floor Life]
nd
BA
Table 5-1 describes the floor life below 30°C (86°F) and 60% RH.
ST
Hi
司
公
限
有
技

科
Issue 00B03 (2017-02-28) 22

诺

淇
圳
深
Table 5-1 Floor life
MSL Floor Life (Out of Bag) at Factory Ambient ≤ 30°C (86°F)/60% RH or As

Stated
1 Unlimited at 30°C (86°F) or lower and at most 85% RH

2 1 year
2a 4 weeks
3 168 hours
4 72 hours
5 48 hours
5a 24 hours
6 Mandatory bake before use. After bake, the product must be reflowed within the
圳
time limit specified on the label.
1深
02
PC
0S
[Usage of Moisture-Sensitive Products]
C0
01
z If the product has been exposed to air for more than 2 hours at 30°C (86°F) or lower and
R0
at most 60% RH, rebake it and pack it into a vacuum bag.
00
If the product has been exposed to air for no more than 2 hours at 30°C (86°F) or lower
V8
z
id
and at most 60% RH, replace the desiccant and pack the chip into a vacuum bag.
ro
For details about other storage and usage rules, see the JEDEC J-STD-033A standard.
nd
BA
ST
Hi
5.4 Rebaking
司
公
限
[Applicable Product]
有
技
All moisture-sensitive ICs of HiSilicon

科
诺
[Application Scope]
淇
圳
All moisture-sensitive ICs that need to be rebaked

1深
[Rebaking Reference]
02
PC
0S
Table 5-2 Rebaking reference

C0
01
Body Level Baking at Baking at 90°C Baking at 40°C

R0
Thickness 125°C (257°F) (194°F) ≤ 5% RH (104°F) ≤ 5% RH

00
V8
≤ 1.4 mm 2a 3 hours 11 hours 5 days

id
(0.06 in.)
ro
3 7 hours 23 hours 9 days

nd
BA

ST
Hi

司
公
限
有
技

科
Issue 00B03 (2017-02-28) 23

诺

淇
圳
深
Body Level Baking at Baking at 90°C Baking at 40°C

Thickness 125°C (257°F) (194°F) ≤ 5% RH (104°F) ≤ 5% RH
5a 10 hours 24 hours 10 days

≤ 2.0 mm 2a 16 hours 2 days 22 days
(0.08 in.)
3 17 hours 2 days 23 days
5a 40 hours 6 days 56 days
≤ 4.5 mm 2a 48 hours 7 days 67 days
(0.18 in.)
圳
1深
02
PC
5a 48 hours 10 days 67 days
0S
C0
01
R0
Note the following:
00
V8
z Table 5-2 lists the minimum rebaking time required for damp products.
id
ro
z Low-temperature rebaking is recommended. nd
z For details, see the JEDEC standard.
BA
ST
Hi
司
公
限
有
技
科
诺
淇
圳
1深
02
PC
0S
C0
01
R0
00
V8
id
ro
nd
BA
ST
Hi
司
公
限
有
技

科
Issue 00B03 (2017-02-28) 24

诺

淇
圳
深
General Information 6 Ordering Information
6 Ordering Information
Figure 6-1 illustrates the mark naming convention of Hi3798M V200.
圳
HiXXXX indicates the 6-digit product model before the part number.
1深
02
Figure 6-1 Chip mark naming convention
PC
0S
C0
01
R0
00
V8
id
ro
nd
BA
ST
Hi
司
公
限
有
技
科
诺
淇
圳
1深
02
PC
0S
C0
01
R0
00
V8
id
ro
nd
BA
ST
Hi
司
公
限
有
技

科
Issue 00B03 (2017-02-28) 25

诺

淇
圳
深
General Information 6 Ordering Information
The letter X in the part number indicates a digit that may vary and is only for internal use. For
details about the corresponding rules of the advanced CA bit fields, consult HiSilicon
technical engineers.
Table 6-1 Packages

Part Number Package Type Package Dimension Pitch
Hi3798 MRBC TFBGA 14 mm x 14 mm (0.55 in. x 0.65 mm

V20XXXXXX 0.55 in.) (0.03 in.)
For example, if the part number is Hi3798MRBCV2010D000, the chip supports Dolby but
not Macrovision (Rovi) and DTS and has no internal DDR SDRAM.
圳
1深
02
PC
0S
C0
According to the technical agreement between HiSilicon and providers of third-party software,
01
HiSilicon has no rights and is not obliged to provide technical samples of the third-party
R0
software for other parties. Therefore, if the third-party software or chips that are provided for
00
only authorized users are involved (including but not limited to DD+ and DTS), ensure that
V8
id
you have obtained authorization from the third party when you place an order for the
ro
HiSilicon chip. nd
BA
ST
Hi
司
公
限
有
技
科
诺
淇
圳
1深
02
PC
0S
C0
01
R0
00
V8
id
ro
nd
BA
ST
Hi
司
公
限
有
技

科
Issue 00B03 (2017-02-28) 26

诺

淇
圳
深
General Information 7 Acronyms and Abbreviations
7 Acronyms and Abbreviations
圳
AAF anti-aliasing digital filter
1深
02
AC alternating current
PC
automatic contrast control
0S
ACC
C0
auto command done
01
ACD
R0
ACL access control list
00
V8
ACLUT44 alpha 4 and color lookup table 4
id
ro
ACLUT88 alpha 8 and color lookup table 8 nd
BA
ACLUTn alpha n and color lookup table n

ST
Hi
ACM automatic color management

司
公
ACT activation
限
有
ADAC audio digital-to-analog converter

技
analog-to-digital converter
科
ADC
诺
address
淇
ADDR
圳
AES Advanced Encryption Standard

1深
02
AF adaptation field
PC
0S
AGC automatic gain control

C0
address generation unit

01
AGU
R0
advanced high-performance bus

00
AHB
V8
ALU arithmetic logic unit

id
ro
AMBA advanced microcontroller bus architecture

nd
BA
ST
AMP asymmetric multi-processing

Hi
司
AO audio output
公
限
有
技

科
Issue 00B03 (2017-02-28) 27

诺

淇
圳
深
AP auto precharge
APB advanced peripheral bus
API application programming interface
AQ asynchronism queue
AREF auto refresh
ARGB alpha red green blue
ARGB1555 alpha 1 bit red 5 bits green 5 bits blue 5 bits
ARGB4444 alpha 4 bits red 4 bits green 4 bits blue 4 bits
ARGB8565 alpha 8 bits red 5 bits green 6 bits blue 5 bits
圳
alpha 8 bits red 8 bits green 8 bits blue 8 bits
1深
ARGB8888
02
ARM ARM
PC
0S
ARP Address Resolution Protocol
C0
01
ASCII American Standard Code for Information Interchange
R0
00
advanced technology attachment
V8
ATA
id
ATAH ATA host controller
ro
nd
ATE acceptance test environment
BA
ST
ATR answer to reset

Hi
司
AV audio & video

公
限
AXI advanced eXtensible interface

有
技
AYCbCr alpha YCbCr

科
诺
AYCbCr8888 alpha YCbCr8888

淇
圳
1深
B
02
PC
BA bank address
0S
C0
BA buffer assigner
01
R0
BER bit error rate

00
ball grid array

V8
BGA
id
Border Gateway Protocol

ro
BGP
nd
BIST build-in self test

BA
ST
BL4/BL8 burst length is 4/burst length is 8

Hi
司
BLOCK block
公
限
有
技

科
Issue 00B03 (2017-02-28) 28

诺

淇
圳
深
BM buffer management
BMC bi-phase mark coding
BRC bank-row- column
BRG bridge
BS barrel-shift
BVACT bottom vertical active area
BVBB bottom vertical back blank
BVFB bottom vertical front blank
BW bandwidth
圳
C
1深
CA conditional access
02
PC
CAR committed access rate
0S
C0
CAS column active select
01
channel associated signaling
R0
CAS
00
cipher block chaining
V8
CBC
id
CBR constant bit rate
ro
nd
CC continuity counter
BA
ST
CCITT International Telegraph And Telephone Consultative Committee

Hi
司
公
CDR clock data recovery

限
有
CFB cipher feedback

技
科
CFG configuration register

诺
淇
CGMS copy generation management system

圳
CAS latency
1深
CL
02
ClassI class I
PC
0S
ClassII class II
C0
01
CLK clock
R0
00
CLUT color lookup table

V8
command
id
CMD
ro
current mode logic

nd
CML
BA
CMU clock multiply unit

ST
Hi
CODEC coder decoder

司
公
限
有
技

科
Issue 00B03 (2017-02-28) 29

诺

淇
圳
深
COEF coefficient
CoS class of service
CPU central processing unit
CRC cyclic redundancy check
CRS completion retry request
CS chip select
CSA common scrambling algorithm
CSC color space conversion
CVBS composite video blanking synchronization
CW cipher word
圳
1深
D
02
PC
DAC digital-to-analog converter
0S
C0
DATE digital part of analog TV encoder
01
DMA of audio and video
R0
DAV
00
dynamic bandwidth assign
V8
DBA
id
DC direct current
ro
nd
DCKO -
BA
ST
DCRC data CRC error

Hi
司
DCT discrete cosine transform

公
限
DDC digital down convert

有
技
DDR double data rate SDRAM

科
诺
DDRC DDR controller

淇
圳
DEC decoder
1深
DECC data ECC

02
PC
DEMUX de-multiplexing
0S
C0
DHCP Dynamic Host Configuration Protocol

01
R0
DHD display high definition

00
delay locked loop

V8
DLL
id
direct memory access

ro
DMA
nd
DMAC direct memory access controller

BA
ST
DOZE doze
Hi
司
DRTO data read timeout

公
限
有
技

科
Issue 00B03 (2017-02-28) 30

诺

淇
圳
深
DRM digital rights management

DSD display standard definition
DSP digital signal processor
DTO data transfer over
DTV digital TV
DVB digital video broadcasting
DVB-C digital video broadcasting cable
DVD digital versatile disc
DVI digital video interactive (Intel)
DW data width
圳
1深
E
02
end to end
PC
E2E
0S
EAV end of active video
C0
01
EB eviction buffer
R0
00
EBE end-bit error
V8
id
EBI external bus interface
ro
nd
ECB electronic codebook
BA
ST
ECC error checking and correction

Hi
司
ECRC end-to-end 32-bit CRC

公
embedded CPU subsystem

限
ECS
有
enhanced data out

技
EDO
科
EHCI Enhanced Host Controller Interface

诺
淇
EMAC Ethernet MAC

圳
1深
EMC electromagnetic compatibility

02
end of packet
PC
EOP
0S
end-to-end TLP is poisoned

C0
EP
01
ERR error
R0
00
ES element stream
V8
id
ESD electro static discharge

ro
nd
ETH Ethernet
BA
ST
ETU elementary time unit

Hi
司
公
限
有
技

科
Issue 00B03 (2017-02-28) 31

诺

淇
圳
深
F
FCB frame control block
FCS frame check sequence
FE fast Ethernet
FEC forward error correction
FID function identifier

FIFO first in first out
FIQ fast interrupt request
FIR finite impulse response
flash memory
圳
FLASH
1深
FPGA field programmable gate array
02
PC
FRUN FIFO underrun/overrun error
0S
C0
01
R0
G
00
guo biao
V8
GB
id
gigabit Ethernet
ro
GE nd
GIC generic interrupt controller
BA
ST
GIF graphics interchange format

Hi
司
GMII gigabit media independent interface

公
限
GND ground
有
技
GPIO general purpose input/output

科
诺
GPON gigabit-capable passive optical network

淇
圳
GPU graphics processing unit

1深
GTC GPON transmission convergence

02
PC
0S
C0
H
01
R0
H2P AHB bus translate into APB bus

00
V8
HAC Huffman AC
id
horizontal active area

ro
HACT
nd
high definition
BA
HDC
ST
HDR high-dynamic range

Hi
司
HDMI high definition multimedia interface

公
限
有
技

科
Issue 00B03 (2017-02-28) 32

诺

淇
圳
深
HF horizontal filter
HFB horizontal front blank
HGU home gateway
HL high level
HP high performance
HPW horizontal pulse width
HW highway
I
I2C inter-integrated circuit
I2S inter-IC sound
圳
1深
IBIS I/O buffer information specification
02
PC
ICMP Internet Control Message Protocol
0S
C0
ICU image capture unit
01
identity
R0
ID
00
inverse discrete cosine transform
V8
IDCT
id
IDLE idle
ro
nd
IEC International Electrotechnical Commission
BA
ST
IEEE Institute of Electrical and Electronics Engineers

Hi
司
公
IGMP Internet Group Management Protocol

限
有
INS instruction
技
科
INT interrupt
诺
淇
IO input output
圳
input output configuration

1深
IOCFG
02
IP Internet Protocol
PC
0S
IPG inter-packet gap

C0
01
IPTV Internet Protocol television

R0
00
IPv6 Internet Protocol version 6

V8
infrared remoter
id
IR
ro
interrupt request line

nd
IRQ
BA
ISO International Standard Organization

ST
Hi
ISR interrupt service routine

司
公
限
有
技

科
Issue 00B03 (2017-02-28) 33

诺

淇
圳
深
ITCM instruction tightly coupled memory

ITU International Telecommunications Union
ITU-R International Telecommunication Union-Radiocommunication
Sector
ITU-T International Telecommunication Union-Telecommunication
Standardization Sector
IV initialization vector
J
JEDEC Joint Electron Device Engineering Council
JESD79 JEDEC Standard Document 79
圳
JPEG Join Picture Expert Group
1深
JTAG Joint Test Action Group
02
PC
0S
C0
L
01
R0
LAN local area network
00
V8
LateCollision late collision
id
ro
LCD liquid crystal display nd
BA
LDO low dropout regulator
ST
light emitting diode

Hi
LED
司
line fill buffer

公
LFB
限
LL low level
有
技
LLI linked list item

科
诺
LMR load mode register

淇
圳
1深
LOS loss of signal

02
LP low performance
PC
0S
LRB line read buffer

C0
01
LS late start time

R0
00
LSN logic sector number

V8
id
LSW LAN switch

ro
lookup table
nd
LUT
BA
low voltage complementary metal oxide semiconductor transistor

ST
LVCMOS
Hi
司
公
限
有
技

科
Issue 00B03 (2017-02-28) 34

诺

淇
圳
深
M
MAC media access control
MAP address mapping
MAU multiply accumulate unit
MAX maximum
MCU multi-point control unit
MDDRC multi-port DDR/SDR controller
MDIO management data input/output
MEM memory
MII media independent interface
minimum
圳
MIN
1深
MIS management-information-system
02
PC
ML main level
0S
C0
MLC multi-level cell
01
R0
MLF malformed
00
V8
MMC multi-media card
id
ro
MMU memory management unit nd
BA
MOD modulation
ST
Hi
MP main profile
司
公
MPCP Multi-Point Control Protocol

限
有
MPI MPEG physical interface

技
most significant bit

科
MSB
诺
message
淇
MSG
圳
MSL moisture sensitivity level

1深
02
MTU maximum transmission unit

PC
0S
C0
01
N
R0
NA not applicable
00
V8
NADDR next address

id
ro
NANDC NAND flash controller

nd
BA
NAPT network address port translation

ST
Hi
NAT network address translation

司
公
NEC Nippon Electric Company

限
有
技

科
Issue 00B03 (2017-02-28) 35

诺

淇
圳
深
NFC NAND flash controller

NTSC National Television System Committee
O
OAM operation, administration and maintenance
ODT on-die termination
OFB output feedback
OFST offset
OHCI Open Host Controller Interface
ONT optical network termination
圳
optical network unit
1深
ONU
02
OOB out-of-band
PC
0S
OP operating mode
C0
01
OpenGL -
R0
-
00
OpenVG1.1
V8
on-the-go
id
OTG
ro
nd
BA
P
ST
Hi
P2P point to point

司
公
PackageYUYV package YUYV

限
有
技
科
PAD packet assembler/disassembler

诺
淇
PAL phase alternation line

圳
1深
PCB physical control block

02
physical control block downstream

PC
PCBd
0S
PCI Peripheral Component Interconnect

C0
01
PCIE PCI express

R0
00
PCM pulse code modulation

V8
id
PCR program clock reference

ro
nd
PES packetized elementary stream

BA
ST
PGD PNG and GIF decoder

Hi
司
PFI payload FCS identifier

公
限
有
技

科
Issue 00B03 (2017-02-28) 36

诺

淇
圳
深
PHY physical sublayer & physical layer

PID packet identifier
PLI payload length indicator
PLL phase-locked loop
PLOAM physical layer OAM
PMC packet memory controller
PMU power management unit
PNG portable network graphics
PON passive optical network
POR power on reset
plain old telephone service
圳
POTS
1深
page program
02
PP
PC
parts per million
0S
PPM
C0
PPPoE point-to-point protocol over ethernet
01
R0
PRBS pseudo-random binary sequence
00
V8
PSRAM pseudo static random access memory
id
ro
PTS presentation time stamp nd
BA
PUSI payload unit start indicator

ST
Hi
PVR personal video record

司
公
PWM pulse width modulation

限
有
技
科
Q
诺
quadrature amplitude modulation

淇
QAM
圳
QinQ 802.1q in 802.1q

1深
02
QoS quality of service

PC
0S
C0
01
R
R0
RANK rank
00
V8
RB ready or busy
id
ro
RBC row-bank-column
nd
BA
RC readable only and self cleaning after reading

ST
Hi
司
RCRC response CRC error

公
限
有
技

科
Issue 00B03 (2017-02-28) 37

诺

淇
圳
深
RD read
RE response error
REQ request
RES resume
RF radio frequency
RGB red green blue
RGB444 red 4 bits green 4 bits blue 4 bits
relative humidity
圳
RH
1深
RIP Routing Information Protocol
02
PC
RIS remote installation services
0S
C0
RISC reduced instruction set computer
01
reduced media independent interface
R0
RMII
00
read only
V8
RO
id
ROM read-only memory
ro
nd
ROP raster operation
BA
ST
RPT report
Hi
司
RS reed solomon
公
限
RST reset
有
技
RSZ resize
科
诺
RTL register transfer logic

淇
圳
RTO response timeout

1深
RW read and write

02
PC
RX reception
0S
C0
RXDR receive FIFO data request

01
R0
00
V8
S
id
serial advanced technology attachment

ro
SATA
nd
SBE start-bit error

BA
ST
SBU single business unit

Hi
司
SC system controller
公
限
有
技

科
Issue 00B03 (2017-02-28) 38

诺

淇
圳
深
SCD start code detect

SCI smart card interface
SCL serial clock line
SCR system clock reference
SCU snoop control unit
SD secure digital
SDA serial data and address
SDK software development kit
SDRAM synchronous dynamic random access memory
SECC -
圳
-
1深
Semi-Planar
02
PC
0S
SerDes serializer/deserializer
C0
01
SET secure electronic transaction
R0
00
SF switch fabric
V8
id
SFD start frame delimiter field
ro
nd
SFU single family unit
BA
sonic input/output
ST
SIO
Hi
session initiation request

司
SIR
公
SLA service level agreement

限
有
SLC single-level cell

技
科
SLEAD simple lead

诺
淇
SLEADE simple lead end

圳
1深
SLIC subscriber line interface circuit

02
SMP symmetric multi-processing

PC
0S
SNAP sub network access point

C0
01
SNR signal-to-noise ratio

R0
00
SoC system on chip

V8
id
SOP start of PES

ro
nd
SP simple profile
BA
ST
SPDIF Sony/Philips digital interface

Hi
serial peripheral interface

司
SPI
公
限
有
技

科
Issue 00B03 (2017-02-28) 39

诺

淇
圳
深
SPS seamless-pause-start
SQ synchronization queue
SR self-refresh
SRAM static random access memory
SSMC static memory controller
SSP synchronous serial protocol
SSTL stub series terminated logic
STA status
STA static timing analysis
STAT status
software item
圳
SW
1深
SYNC synchronization
02
PC
0S
C0
T
01
target
R0
TAR
00
traffic class
V8
TC
id
TCM tightly coupled memory
ro
nd
TCONT transmission container
BA
ST
TCP Transmission Control Protocol

Hi
司
TDE two dimension engine

公
限
TDM time division multiplexing

有
技
TEI transmit error indicator

科
诺
TIMER timer
淇
圳
TLP transaction layer packet

1深
TPIT TS packet index table

02
PC
TS target and source

0S
C0
TS transport stream
01
R0
TT teletext
00
television
V8
TV
id
top vertical active area

ro
TVACT
nd
TVBB top vertical back blank

BA
ST
TVFB top vertical front blank

Hi
司
TXDR transmit FIFO data request

公
限
有
技

科
Issue 00B03 (2017-02-28) 40

诺

淇
圳
深
U
UART universal asynchronous receiver transmitter
UC unexpected completion
UDP User Datagram Protocol
UI user interface
ULPI UTMI+ low-pin interface
UNI user network interface
UR unsupported request
USB universal serial bus
圳
USB 2.0 transceiver macrocell interface
1深
UTMI
02
UXGA ultra extended graphics array
PC
0S
C0
01
V
R0
vertical active area
00
VACT
V8
video advance high-performance bus
id
VAHB
VBB vertical back blank
ro
nd
BA
VBI vertical blanking interval

ST
Hi
VBR variable bit rate

司
公
VC virtual channel
限
有
VCO voltage controlled oscillator

技
科
VCOEF vertical coefficient

诺
淇
VCXO voltage control crystal oscillator

圳
video decoder high definition

1深
VDH
02
VEDU video encoder unit

PC
0S
VER version
C0
01
VF vertical filter
R0
00
VFB vertical front blank

V8
video firmware
id
VFMW
ro
video graphics array

nd
VGA
BA
VHB video high-performance bus

ST
Hi
VI video input
司
公
限
有
技

科
Issue 00B03 (2017-02-28) 41

诺

淇
圳
深
VIC vector interrupt controller

VID VLAN ID
VIU video input unit
VLAN virtual local area network
VLC variable length code
VLD variable length decoding
VO video output
VoIP voice over IP
VDP video display processor
VSD video for standard definition
圳
1深
W
02
PC
W1C write 1 to clear 0
0S
C0
WB write buffer
01
write back channel
R0
WBC
00
write to clear
V8
WC
id
WDG watchdog
ro
nd
WDT watchdog timer
BA
ST
WFE wait for event

Hi
司
WFI wait for interrupt

公
限
WIP write in progress

有
技
WO write only
科
诺
WRA wrap
淇
圳
WRED weighted random early drop

1深
WRR weighted round robin

02
PC
WSS wide screen signaling

0S
C0
01
R0
X
00
AXI bus translate into AHB bus

V8
X2H
id
AXI bus translate into APB bus

ro
X2P
nd
BA
ST
Y
Hi
司
YC luma and chroma

公
限
有
技

科
Issue 00B03 (2017-02-28) 42

诺

淇
圳
深
YCbCr YCbCr
YCbCr400MB YCbCr400 macro block
YCbCr422 YCbCr422
YCbCr422MB YCbCr422MB
YCbCr422MBH YCbCr422 macro block horizontal
YCbCr422MBV YCbCr422 macro block vertical
YCbCr888 YCbCr888
YUV YUV
YUV400
圳
YUV400
1深
YUV420 YUV420
02
PC
YUV422 YUV422
0S
C0
YUV444 YUV444
01
R0
00
V8
Z
id
ZME zoom engine
ro
nd
ZQCL ZQ calibration long
BA
ST
ZQCS ZQ calibration short

Hi
司
公
限
有
技
科
诺
淇
圳
1深
02
PC
0S
C0
01
R0
00
V8
id
ro
nd
BA
ST
Hi
司
公
限
有
技

科
Issue 00B03 (2017-02-28) 43

诺

淇
圳
深

Hi3798M V200 Data Sheet 01-General Information

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Hi3798M V200 Data Sheet

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HiSilicon Technologies Co., Ltd.

Address: New R&D Center, Wuhe Road,

Bantian, Longgang District,

Shenzhen 518129 P. R. China

About This Document

z PCB Design Recommendations

z Thermal Design Recommendations

Hi3798M V200 Data Sheet 03 System z Processor Subsystem

z Always-on area subsystem

z Power Management and Low-Power

HiSilicon Proprietary and Confidential

Issue 00B03 (2017-02-28) i

Copyright © HiSilicon Technologies Co., Ltd.

Document No. Document Name Description

Product Name Version

HiSilicon Proprietary and Confidential

Issue 00B03 (2017-02-28) ii

Copyright © HiSilicon Technologies Co., Ltd.

Issue 00B03 (2017-02-28)

This issue is the first draft release.

HiSilicon Proprietary and Confidential

Issue 00B03 (2017-02-28) iii

Copyright © HiSilicon Technologies Co., Ltd.

About This Document ......................................................................................................................i

1.2.10 Low-Power Control .............................................................................................................................. 8

2 Boot Mode ...................................................................................................................................... 9

3 Address Space Mapping ............................................................................................................ 11

4 Soldering Process Recommendations ..................................................................................... 16

4.1 Overview ........................................................................................................................................................ 16

4.2 Requirements on Parameters of the Lead-Free Reflow Soldering Process .................................................... 16

4.3 Requirements of Mixing Reflow Soldering ................................................................................................... 19

5 Moisture-Sensitive Specifications ........................................................................................... 21

5.1 Overview ........................................................................................................................................................ 21

5.2 HiSilicon Moisture-Proof Packaging ............................................................................................................. 21

5.2.1 Basic Information.................................................................................................................................. 21

5.2.2 Incoming Inspection.............................................................................................................................. 22

5.3 Storage and Usage .......................................................................................................................................... 22

5.4 Rebaking ........................................................................................................................................................ 23

7 Acronyms and Abbreviations ................................................................................................... 27

HiSilicon Proprietary and Confidential

Issue 00B03 (2017-02-28) v

Copyright © HiSilicon Technologies Co., Ltd.

Figure 1-1 Application block diagram ................................................................................................................... 2

HiSilicon Proprietary and Confidential

Issue 00B03 (2017-02-28) vi

Copyright © HiSilicon Technologies Co., Ltd.

Table 3-1 Address space mapping ....................................................................................................................... 11

HiSilicon Proprietary and Confidential

Issue 00B03 (2017-02-28) vii

Copyright © HiSilicon Technologies Co., Ltd.

1.1 Application Scenario

communication, karaoke, cloud game, and multi-screen interaction.

HiSilicon Proprietary and Confidential

Issue 00B03 (2017-02-28) 1

Copyright © HiSilicon Technologies Co., Ltd.

Figure 1-1 Application block diagram

Hi3798M V200 has the following features:

z Data stream interfaces

z Graphics and display processing

1.2.1 Master Processor

the following features: