HCMC University of Technology and Education

Faculty of Electrical & Electronic Engineering

Lecture:
DIGITAL SYSTEMS
Chapter 4:
Asynchronous Down/Up Counters

Assoc. Prof. Nguyen Thanh Hai, PhD

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HCMC University of Technology and Education
Faculty of Electrical & Electronic Engineering

Asynchronous Up/Down Counters

Up counter Q4Q3Q2Q1 with the 1000b (8) start, not 0000 (0) and
1111b (15) end and recount.
Vcc (1)
J PRE Q1 J PRE Q 2 J PRE Q 3 J PRE Q4

CLK CLK CLK CLK CLK

Vcc K CLR
K CLR Q1 K CLR Q 2 K CLR Q 3 Q4

- When supplying Vcc=+5V, Capacitor C charged Vcc (1)

fully, Press K, C discharged and Clear = 0, all
K Qs of FF =0, K opened, outputs to zero. When
C recharged fully, Clear = 1

Representation of charging
and discharging on Capacitor
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Assoc. Prof. Nguyen Thanh Hai, PhD
HCMC University of Technology and Education
Faculty of Electrical & Electronic Engineering

Asynchronous Up/Down Counters

Up counter Q4Q3Q2Q1 with the 1000b (8) start and 1111b (15) end
Vcc (1)
J PRE Q1 J PRE Q 2 J PRE Q 3 J PRE Q4

CLK CLK CLK CLK CLK

Vcc K CLR
K CLR Q1 K CLR Q 2 K CLR Q 3 Q4

- When K close, Clear = 0 and Preset = 1, Q1Q2Q3 Vcc (1)

outputs =0, while FF4 has Clear=1 and Preset=0, the
output Q4=1 always, states Q4Q3Q2Q1 (1000) starts
K counting
- When K open, Clear = 1 and Preset = 1, Q1Q2Q3
count like asynchronous counters and Q4 is nearly
fixed to be level 1. Thus the counter will count from
1000b (8) to 1111b (15) and return to recount 3
Assoc. Prof. Nguyen Thanh Hai, PhD
HCMC University of Technology and Education
Faculty of Electrical & Electronic Engineering

Asynchronous Up/Down Counters

EX: Determine counting states of the following circuit and draw its
truth table with sates and inputs, in which Preset of Q1=Q3=Q4=1 and
Clear of Q2=1, and Preset of Q2 and Clear of Q1,Q3, Q4 are
connected together to Start circuit with Contact K.

Vcc (1)
J PRE Q1 J PRE Q 2 J PRE Q 3 J PRE Q4

CLK CLK CLK CLK CLK

Vcc K CLR
K CLR Q1 K CLR Q 2 K CLR Q 3 Q4

Vcc (1)

K
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Assoc. Prof. Nguyen Thanh Hai, PhD
HCMC University of Technology and Education
Faculty of Electrical & Electronic Engineering

Asynchronous Up/Down Counters

Down counter Q4Q3Q2Q1 with the 1111b (15) start and 1000b (8) end

Vcc (1)
J PRE Q1 J PRE Q 2 J PRE Q 3 J PRE Q4

CLK CLK CLK CLK CLK

Vcc K CLR Q1 K CLR
K CLR Q 2 K CLR Q 3 Q4

Vcc (1)
- The operation of this down counter is similar to the up
counter and it is just different from clock connection. In
K particular, CK is connected to FF1 and the output of
Q1 (inverting) is connected to Ck2 of FF2 and etc.
From this connection, we have the down counter from
1111b (15) to 1000b (8) and return to recount

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Assoc. Prof. Nguyen Thanh Hai, PhD
HCMC University of Technology and Education
Faculty of Electrical & Electronic Engineering

Asynchronous Up/Down Counters

The End

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Assoc. Prof. Nguyen Thanh Hai, PhD