Chapter 4 - Synchronous Counters

HCMC University of Technology and Education
Faculty of Electrical & Electronic Engineering
Lecture:
DIGITAL SYSTEMS
Chapter 4:
Synchronous Counters
Assoc. Prof. Nguyen Thanh Hai, PhD

1
This is a synchronous Counter which we
can understand based on explaining step
by step as described bellow. Q1
Q1Q 2 Q3
CLR  PRE  1, Q2
Q1
J1  K1  1  Q1 : Toggle,
Q2 Q3
Q2, Q3, Q4 : regard of CLK
1
J1 Q1 J2 Q2 J3 Q3 J4 Q4
CLK CLK CLK CLK

CLK
K1 Q1 K2 Q2 K3 Q3 K4 Q4
- T1=J1=K1=1 - Ck1, T2=Q1=0, T3=Q1Q2=0, T4=Q1Q2Q3=0
- T2=J2=K2=Q1 - Ck2, T2=Q1=1, Q2=0, T3=Q1Q2=0, T4=Q1Q2Q3=0
- T3=J3=K3=Q1Q2 - Ck3, T2=Q1=0, Q2=1, T3=Q1Q2=0, T4=Q1Q2Q3=0
- T4=J4=K4=Q1Q2Q3 - Ck4, T2=Q1=1, Q2=1, T3=Q1Q2=1, Q3=0, 2

Assoc. Prof. Nguyen Thanh Hai, PhD T4=Q1Q2Q3=0
Synchronous Up Counter Design
A counter can be designed to count from state 0 to end

state with a synchronous clock pulse.
For example, an counter may be design using 3 FFs (3
bits) to count from 000, 001, 011, 100, 101, 110.
In techniques to make the synchronous counter, FF-JK and
FF-D are often used.
In design of the counter, one needs to know the table og
present and next states based on the type of FF (-JK or -D)
3
This is FF-JK/D-FF tables - c1: k=x=0, no change;
k=x=1, state of JK
- c2: k=x=1, toggles; k=x=0,
state of JK
- c3: J=x=1, toggles; J=x=0,
state of JK
- c4: J=x=0, no change;
J=x=1, state of JK
Explain excitation tables

corresponding to J,K and
D to present/next states
4
Design steps as follows:
1. Based on state diagram to know all desired states for
designing synchronous counter
2. Determine FF numbers and MOD counter procedure
3. Show truth tables with all present and next states and add J,K
columns corresponding to each present state and address
next state corresponding to the J,K inputs of each FF
4. Maybe use K-map for determining the minimum expression
5. Draw a logic circuit based on the logic expression
5
Step-1: Design a synchronous up counter with 3 bits, 000, 001,
…, 111 as in the below Figure
Step-2: Based on this diagram, we need 3 FFs and can

choose FF-JK or FF-D for designing the synchronous up
counter. 6
Step-3: show the excitation truth table with all present and next
states corresponding to the J, K inputs
No Pre-State Next-state Inputs
St Q3 Q2 Q1 Q3 Q2 Q1 J3 K3 J2 K2 J1 K1
0 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 0 0 X 1 X X 1
2 0 1 0 0 1 1 0 X X 0 1 X
3 0 1 1 1 0 0 1 X X 1 X 1
4 1 0 0 1 0 1 X 0 0 X 1 X
5 1 0 1 1 1 0 X 0 1 X X 1
6 1 1 0 1 1 1 X 0 X 0 1 X
7 1 1 1 0 0 0 X 1 X 1 X 1
According to this counting procedure, the counter is from 000 to

111, so we will use 3 FFs-JK.
7
Q1 Q1 Q1 Q1 Q1 Q1
Step 4: Design
Q3 Q2 00 01 Q3 Q2 X0 X1 Q3 Q2 10 X1 a logic circuit to
Q3 Q2 0 2 1 3 Q3 Q2 X2 X3 Q3 Q2 1 2 X3 create the
Q3Q2 X6 X7 Q3Q2 06 1 7 Q3Q2 16 X7 correct logic
Q3 Q2 X4 X5 Q3 Q2 0 4 05 Q3 Q2 1 4 X5 level at each J,K
input using
J 3  Q1Q2 K 3  Q1Q2 J1  1 Karnaugh maps
for each one of
Q1 Q1 Q1 Q1 Q1 Q1
inputs, then
Q3 Q2 00 11 Q3 Q2 X0 X1 Q3 Q2 X0 11
simplify the
Q3 Q2 X2 X3 Q3 Q2 0 2 1 3 Q3 Q2 X2 1 3 Boolean
Q3Q2 X6 X7 Q3Q2 06 1 7 Q3Q2 X6 1 7 expression as in
Q3 Q2 0 4 15 Q3 Q2 X4 X5 Q3 Q2 X4 15 Figures (a), (b),
…, (f)
J 2  Q1 K 2  Q1 K1  1
8
Step 5: From the minimum expressions, one may draw the
following logic circuit:
J1  1 J 2  Q1 J 3  Q1Q2
K1  1 K 2  Q1 K 3  Q1Q2 Q1
Q2
1
1
J 1 PRE Q J 2 PRE Q J 3 PRE Q
1 2 3
CLK CLK CLK

K 1 CLR Q 1 K 2 CLR Q 2 K 3 CLR Q 3
After determining the expressions of JK following Q1Q2Q3, we

easily draw the logic circuit as shown in figure.
9
Step 3: show the excitation truth table with all present and next
states corresponding to the D input
No Pre-State Next-state Inputs
St Q3 Q2 Q1 Q3 Q2 Q1 D3 D2 D1
0 0 0 0 0 0 1 0 0 1
1 0 0 1 0 1 0 0 1 0
2 0 1 0 0 1 1 0 1 1
3 0 1 1 1 0 0 1 0 0
4 1 0 0 1 0 1 1 0 1
5 1 0 1 1 1 0 1 1 0
6 1 1 0 1 1 1 1 1 1
7 1 1 1 0 0 0 0 0 0
10
Q1 Q1 Q1 Q1
Step 4: Design a logic
Q3 Q2 00 01 Q3 Q2 00 11
circuit to create the
Q3 Q2 0 2 1 3 Q3 Q2 1 2 0 3 correct logic level at
Q3Q2 16 0 7 Q3Q2 16 0 7 each D input using
Q3 Q2 1 4 15 Q3 Q2 0 4 15 Karnaugh maps for each
one of inputs, then
D 3  Q3Q2  Q1Q3  Q1Q2Q3 D 2  Q1Q2  Q1Q2
simplify the Boolean
expression as in Figures
Q1 Q1
(a), (b), …, (f)
Q3 Q2 10 01
Q3 Q2 1 2 0 3
Q3Q2 16 0 7
Q3 Q2 1 4 05
D1  Q1
11
The End
12

Chapter 4 - Synchronous Counters

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HCMC University of Technology and Education

Faculty of Electrical & Electronic Engineering

Assoc. Prof. Nguyen Thanh Hai, PhD

CLK CLK CLK CLK

- T1=J1=K1=1 - Ck1, T2=Q1=0, T3=Q1Q2=0, T4=Q1Q2Q3=0

- T2=J2=K2=Q1 - Ck2, T2=Q1=1, Q2=0, T3=Q1Q2=0, T4=Q1Q2Q3=0

- T3=J3=K3=Q1Q2 - Ck3, T2=Q1=0, Q2=1, T3=Q1Q2=0, T4=Q1Q2Q3=0

- T4=J4=K4=Q1Q2Q3 - Ck4, T2=Q1=1, Q2=1, T3=Q1Q2=1, Q3=0, 2

A counter can be designed to count from state 0 to end

Explain excitation tables

Step-2: Based on this diagram, we need 3 FFs and can

According to this counting procedure, the counter is from 000 to

CLK CLK CLK

After determining the expressions of JK following Q1Q2Q3, we

No Pre-State Next-state Inputs

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