University Technological of Altamira

Mechatronics Career

Subject: Digital Electronic

Master: Oscar Martínez Hernández.

Activity: Homework 2

21/01/2023
 Group: MEC 4A

Team: Workaholics

Members:

-Bautista Cruz Leo.

- Castillo Saldierna Kevin Yael.
- Delgado Maldonado Jan Emmanuel.
- Diaz Madrigales Jessica.
- Méndez García Osiris Dalai.
- Rosas Castillo Joshua Gabriel.
- Sánchez Hernández Jesús Gerardo.
GAL programming
of the PDL
 One type of the PLD’s

The PLD GAL was chosen, which shares properties with the PAL type that only
allow programming the AND matrix, so they cost less but are limited in terms
of the maximum number of minterms per output, but with the addition that
they can be deleted and reprogrammed Therefore, it is considered as a better
option.
 GAL
GAL (Generic Array Logic), in Spanish Generic Logical Arrangement, is a type of
integrated circuit, registered trademarked by Lattice Semiconductor, which has been
designed with the purpose of replacing most PALs, maintaining the compatibility of
its terminals. El GAL destaca por su bajo precio y versatilidad por lo que lo
describiremos en el siguiente punto.

It uses an EEPROM memory matrix instead so it can be programmed several times.

A GAL in its basic form is a PLD with a reprogrammable AND matrix, a fixed OR matrix
and a output logic programmable by means of a macrocell. This structure allows you
to implement any logical function as a sum of products with a defined number of
terms. The GAL is basically made up of a reprogrammable AND array and a fixed OR
array with programmable configuration of outputs and/or inputs.
The Generic Array Logic (GAL) device was an innovation of the PAL and was invented
by Lattice Semiconductor. The GAL was an improvement on the PAL because one
device type was able to take the place of many PAL device types or could even have
functionality not covered by the original range of PAL devices. Its primary benefit,
however, was that it was eraseable and re-programmable, making prototyping and
design changes easier for engineers.

PALs and GALs are available only in small sizes, equivalent to

a few hundred logic
gates. For bigger logic circuits, complex programmable logic
device (CPLD) can be
used. These contain the equivalent of several PALs linked by
programmable
interconnections, all in one integrated circuit. CPLDs can
replace thousands, or even
hundreds of thousands, of logic gates.
 Software and Hardware PLDs
Software

The software used to program PLDs is called logic compilers. There are several
programs on the market, some of them are: ABEL CUPL, OrCAD-PLD. All programs
generate an output file called a JEDEC (cell map or fuse map) file for the device
programmer. The advantage of the software is that a complete simulation and
debugging of the logical design can be done before proceeding to the physical
fabrication of the circuit (if not, imagine how many circuits would be lost if this option
could not be realized).
For example:

• PLD programming software Wincupl (Logic

Compiler).
• Software to simulate or check PLD programming
WinSim.
• Software to simulate or check circuit and
programming of a PLD Proteus.
Hardware programmable.

A programmable device is an electronic component that allows the implementation

of functions by combining and reconnecting simpler elements. They are made up of
discrete elements and reconfigurable interconnection logic. Unlike fixed hardware, it
does not implement a certain functionality. The function is programmed into the
device after it is manufactured.

In this context, for an embedded system design it is necessary to determine that

functionality: It is implemented on fixed hardware, It is implemented in
programmable hardware, It is implemented in software The introduction of
programmable hardware blurs the lines between the development of software and
hardware development.
Programmable Hardware Categories.

• Simple Programmable Logic Devices (SPLDs)

• Complex Programmable Logic Devices (CPLDs)
• Field Programmable Gate Arrays (FPGAs)
• Certain functionality can be implemented in more than one of these
categories (overlap).
• The most complex PLDs can implement any functionality, but not it is always
convenient.
 Advantages
1. Has the function of being electrically erasable. It is made of erasable CMOS, which can
be erased with a voltage signal and can be reprogrammed, which overcomes the
shortcoming of using fuse technology to program only once, and the number of times it
can be rewritten exceeds 100 times;
2. Due to the use of the output macrocell structure, users can configure it according to
their needs. A GAL device can realize the logic function of the PAL device output structure
of various configurations, which brings great convenience to the circuit design;
3. With the function of encryption, protecting intellectual property rights;
4. A storage area is set up in the device to store the identification mark, that is, the
function of the electronic label.
 Programming

Typically, some high-level language (such as CUPL or ABEL) is used that describes the
desired logic equations, and then compiled (through optimization and minimization
steps) into a JEDEC file, which has the information about which internal fuses to burn. A
free development and simulation environment is WinCUPL from Microchip (formerly
Atmel).
GAL structures are PAL structures built with CMOS technology, and
were first commercialized in 1984 by Lattice Semiconductor. As
mentioned, they are programmable and electrically erasable. They
are reprogrammable and more flexible, at the output of the AND/OR
matrix there is a more complex circuit with selectors and flip-flops
that allow more complex equations to be implemented. There are
different architectures depending on the manufacturer's version.

GALs are used for simple and medium complexity logic circuits.
The macrocell, in the English language is by its acronym OLMC
(OutputLogicMacrocells). And they are logic macrocells containing
OR gates and programmable logic, logic circuits that can be
programmed as combinational logic or sequential logic (flip-flops,
counters and registers).
The programming software takes care of these details in a user-friendly way. The
complete logic diagram of the GAL 16V8. This device has eight dedicated input
terminals (terminals 2-9), two with special functions (1 and 11), and eight (12-19)
that can be used as inputs or outputs.

The flexibility of the GAL 16V8 lies in its programmable output logic macrocell. Eight
different products (outputs of the AND gates) are applied as inputs to each of the
eight macro cells. Within each macro the products are sent to an OR gate at the
same time to generate the sum of products (SOP).