DIGITAL ELECTRONICS LAB WORKSHEET

Experiment Title – 4
Student Name: Branch:
Errolla Pragnya cse aiml
Section/Group:109-B
UID 22BAI71029 Subject Name: Digital
Subject Code: 22ECH-101 Electronics
Date of Perf.: 11/03/2023

Aim:
Design and realize a given function using K-maps and verify its
performance.

Requirements:
7486 (XOR) IC, 5V Power Supply, Breadboard, connecting wires,
Simulation software, slide Switch, LED, Resistance.
Circuit diagram/ Block diagram:

An XOR Gate is a combination of two NOT Gates, two AND Gates, and
one OR Gate. The output of an Exclusive-OR gate ONLY goes “HIGH”
when its two input terminals are at “DIFFERENT” logic levels with
respect to each other.

Canonical Forms (Normal Forms): Any Boolean function can be

written in disjunctive normal form (sum of min-terms) or conjunctive
normal form (product of max-terms). A Boolean function can be
represented by a Karnaugh map in which each cell corresponds to a
min-term. The cells are arranged in such a way that any two immediately
adjacent cells correspond to two min-terms of distance 1. There is more
than one way to construct a map with this property.
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2- Variable K-Map

The number of cells in 2 variables K-map is four, since thenumber

of variables is two.

There is only one possibility of grouping 4 adjacent min terms.

3- Variable K-Map

The number of cells in 3 variable K-map is eight, since thenumber

of variables is three.

There is only one possibility of grouping 8 adjacent min terms.

4- Variable K-Map

The number of cells in 4 variables K-map is sixteen, since thenumber

of variables is four.

There is only one possibility of grouping 16 adjacent min terms.

DIGITAL ELECTRONICS LAB
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DIGITAL ELECTRONICS LAB
WORKSHEET
 DIGITAL ELECTRONICS LAB
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PROCEDURE:

Check the components for their working. Insert the appropriateIC into
the IC base. Make connections as shown in the circuit diagram. Provide
the input data via the input switches and observe the output-on-output
LEDs. Verify the Truth Table.

Result:
Simplified and verified the Boolean function using basic gatesand
universal gates.

Evaluation Grid:
Sr. Parameters Marks Maximum
No Obtaine Marks
. d
1. Worksheet completion including 12
writing learning
objectives/Outcomes. (To be
submitted at the end of the day).

2. Viva 8
3. Student Engagement in 10
Simulation/Demonstration/Performance
and Controls/Pre-Lab Questions.
Signature of Faculty (with Date): Total
Marks
Obtained: