Computer Organization and

Architecture(CS 2006)

Bindu Agarwalla

1
 COA
1. Computer??
2. Organization??
3. Architecture??

A Computer is an electronic device that accepts input from the outside world and
processes them according to some predefined instructions and prooduces output for
the outside world.
 Computer
1. Input Devices
2. Memory
3.Processor
4. Output Devices
 Memory
2. Memory
Primary Memory: RAM and ROM
Meaning of Memory capacity
bit
byte
nibble
word
Secondary memory

A processor is connected to a 128GX32 memory module. What is the width

of its address bus and data bus?
 Processor
2. CPU
ALU
REGISTER SET
CONTROL UNIT

One instruction requires 7 clock cycle to complete its execution. How much time
is required for that instruction if the processor speed is 5 GHz?
 Registers
1. Dedicated:
PC
MAR
MDR
IR
SP

PC: Program counter. It points to the next instruction to be executed.

MAR: Memory Address Register. It contains the address of the memory

location from where any read/ write operation is going to take place.

MDR: Memory Data Register. It contains the data that is being read from
memory/ the data that is being written into memory during a write operation.

IR: Instruction Register. It contains the current instruction being executed.

 Registers
SP: Stack Pointer: It points to the top of the stack. stack grows
downward in the memory. For push operation, SP is first
decremented and for opo operation, SP is incremented after the
operation.

General Purpose Registers:

R0.......RN-1
These are programmer visible registers that can be used as operands in an
instruction.
Basic Operational Concept
How an instruction is being executed?
 Basic Operational Concept
Instruction Cycle: It consists of:
a. Fetch the instruction pointed by PC into IR
b. Decode the instruction.
c. Fetch the operands (if required)
d. Execute the instruction.
e. Store the result into memory( if required)
Here steps <c> and <d> are optional.

a.Fetch the instruction pointed by PC into IR:

i. [PC]→ MAR
ii. Generate the 'Read' Signal.
iii. Wait for the MFC(Memory Function to Complete)
iv. [MDR]→ IR

b. Decode the instruction: Decoder is connected to IR. Hence, the

instruction is decoded immediately and what is the operation to be
performed is found out.
 Basic Operational Concept
Example1 : ADD R1, R2
Steps:
1. [PC]→ MAR
2. Generate the 'Read' Signal.

3. Wait for the MFC(Memory Function to Complete)

4. [MDR]→ IR
5. Decode the instruction.

6. Execute the instruction.

ALU will perform the addition on the contents of R1 and R2 and
result of addition will be stored into R2.
 Basic Operational Concept
Example1 : ADD A, R1
Steps:
1. [PC]→ MAR
2. Generate the 'Read' Signal.

3. Wait for the MFC(Memory Function to Complete)

4. [MDR]→ IR
5. Decode the instruction.

6. Fetch the operand stored at memory location A

I. Address part of IR→ MAR
II. Generate the 'Read' Signal.
III. Wait for the MFC(Memory Function to Complete)
IV. [MDR]→ Input of ALU
 Basic Operational Concept
Example1 : ADD A, R1
Steps:[Continued]

7. Execute the instruction.

ALU will perform the addition on the contents of memory
location A and R1 and result of addition will be stored into R1.

How many times the memory is referred to execute the instruction:

ADD A, R1

2 times.
1. To fetch the instruction.
2. To fetch the operand from memory location A
 Basic Operational Concept
Example1 : ADD R1, A
Steps:
1. [PC]→ MAR
2. Generate the 'Read' Signal.

3. Wait for the MFC(Memory Function to Complete)

4. [MDR]→ IR
5. Decode the instruction.

6. Fetch the operand stored at memory location A

I. Address part of IR→ MAR
II. Generate the 'Read' Signal.
III. Wait for the MFC(Memory Function to Complete)
IV. [MDR]→ Input of ALU
 Basic Operational Concept
Example1 : ADD R1, A
Steps:[Continued]

7. Execute the instruction.

ALU will perform the addition on the contents of memory
location A and R1.

7. Store the result into the memory location A.

I. Address part of IR→ MAR

II. MDR← Result from ALU

III. Generate the 'Write' Signal.

IV. Wait for the MFC(Memory Function to Complete)

 Basic Operational Concept
How many times the memory is referred to execute the instruction:
ADD R1, A

3 times.
1. To fetch the instruction.
2. To fetch the operand from memory location A
3. To store the result into memory location A

How many times the memory is referred to execute the instruction:

ADD R1, R2
Answer: 1

How many times the memory is referred to execute the instruction:

MOV R1, A
Answer: 2
How many times the memory is referred to execute the instruction:
MOV A, R1
Answer: 2
 Bus Structures
What is Bus??
Types:(Based on Number)
Single Bus
Multibus

Types:(Based on type of information carrying)

Address Bus
Data bus
Control Bus
 Bus Structures
Types:(Based on Connection)
Internal Bus
External bus
 Concept of Interrupt
INTR
INTA
ISR
 Questions
A processor is connected to a 4G×32 bit memory module . A program is
kept in 100th address of the memory and the maximum length of each
instruction of the program is of 32 bits. Then find out size of MAR,MDR
, IR and also the content of PC?

A processor has 48-bit instructions composed of two fields: the first two bytes
contain the opcode and the remainder a memory operand address.How many bits
are needed for the Program Counter and the Instruction Register ?
 Questions
a)At the end of a memory read operation, the MDR is loaded with a
binary combination, how that combination is interpreted as an instruction
or an operand to an instruction?

If the memory operation is initiated by sending the contents of PC to

MAR, then the content of MDR will be interpreted as an instruction else
as an operand.
Thank You