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Japanese Journal of Applied Physics 61, SM0802 (2022) PROGRESS REVIEW
https://doi.org/10.35848/1347-4065/ac665d

Ta/HfO2 memristors: from device physics to neural networks

Hao Jiang1*, Can Li2*, and Qiangfei Xia3*
1
Frontier Institute of Chip and System, Fudan University, Shanghai, People’s Republic of China
2
Department of Electrical and Electronic Engineering, The University of Hong Kong, Hong Kong, People’s Republic of China
3
Department of Electrical and Computer Engineering, University of Massachusetts Amherst, Amherst, MA 01003, United States of America
*
E-mail: haoj@fudan.edu.cn; canl@hku.hk; qxia@umass.edu
Received January 26, 2022; revised March 13, 2022; accepted April 10, 2022; published online June 21, 2022

Hardware implementation of neural networks with memristors can break the “von-Neumann bottleneck,” offer massive parallelism, and hence
substantially boost computing throughput and energy efficiency. In this review, we first explain the design principles and switching mechanism of a
Ta/HfO2 memristor. We show that the device meets most key requirements on device properties for in-memory computing. We then introduce the
integration of the memristor with foundry-made metal-oxide-semiconductor transistors and the programming of the one-transistor-one-resistance
switch (1T1R) arrays. We demonstrate that the crossbar arrays can be used in various neural networks. Finally, we discuss the remaining
challenges of scaling up the memristive neural networks for larger scale real-world problems. © 2022 The Author(s). Published on behalf of The
Japan Society of Applied Physics by IOP Publishing Ltd

temperature, an essential requirement for inference opera-

1. Introduction
Conventional digital computers based on von-Neumann
architecture require frequent data transmission between the
physically separated processing and memory units. Their
basic building block, namely, metal-oxide-semiconductor
field-effect transistors is approaching its scaling limit. As a
result, they have limited energy and speed efficiencies,
especially for data-centric applications, including artificial
intelligence. Hardware built with emerging devices capable
of computation at the site where data is stored by using
physical laws offers an attractive solution to these issues. A
memristor, a two-terminal resistance switch whose behavior
is based on the ionic motion under an electric field, is one of
the promising candidate devices.1–3) Built into large-scale
arrays, memristors perform in-memory computing with their
multilevel conductance states as the synaptic weights.4–21) In
a crossbar array, a current is generated at each cell when
voltages are applied at row wires based on Ohm’s Law,
implementing multiplication in the physical domain. The
current along each column wire sums up according to
Kirchhoff’s Current Law, realizing the summation operation.
Such implementation of the vector-matrix multiplication
(VMM), an essential but resource-hungry computing opera-
tion in various artificial neural networks, can be efficiently
performed by memristor crossbar arrays in one step.
Although computing hardware based on memristors is
promising for a broad spectrum of applications such as
computer vision, speech recognition, and autonomous vehi-
cles, building such hardware is a challenging task.17)
Going from a discrete device to a large-scale array and
eventually to a memristive neural network capable of solving
real-world problems (Fig. 1) requires multidisciplinary ex-
pertise and a deep understanding of device physics, circuits,
architecture, and algorithms. From the device property
perspective, a reasonably wide conductance range with
multiple conductance states is required to represent analog
synaptic weights in many neural network algorithms. Each
conductance state should be stable against drift with time or
tions. The device must be able to switch enough times for
adequate conductance programming cycles during the
training. The preferred operational conductance should be
low to reduce the power consumption. Still, a linear current–
voltage (IV) relationship is desired at the same time to
directly utilize Ohm’s Law for the VMM. Moreover, a linear
and symmetric weight updating is critical for efficient in situ
training of neural networks, which means the device con-
ductance should increase or decrease at the same pace when
external stimuli of the same amplitude, but opposite polarity
are applied.
Herein we review our progress in developing a Ta/HfO2
memristor and in-memory computing applications. We de-
signed the device based on the requirements in critical
metrics such as multilevel conductance, retention, endurance,
etc. We proposed that the continuous modulation of the
chemical composition in the conduction channel and the
thermodynamic properties of the mobile species are respon-
sible for the device’s behavior. We built a large-scale 1T1R
array by back-end-of-the-line integration of the memristors
with foundry-made transistor arrays. We introduced the
programming and operation of the array from the perspec-
tives of both the semiconductor devices physics and mixed-
signal circuits. We implemented memristive neural networks
with software- and hardware-based activation functions and
demonstrated their applications in typical machine learning
tasks. Finally, we discussed the challenges and opportunities
of the emerging hardware and identified some key areas that
need intensive research and development to push the
memristive neural networks as a low-power hardware plat-
form for larger scale real-world machine learning applica-
tions.
2. Device design principles
To design a memristive device with multiple resistance states
that can be tuned in an analog fashion, it is essential to
understand the fundamental mechanism underpinning the
switching behavior. Figure 2 schematically illustrates three

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Fig. 1. (Color online) The two-terminal memristor device, usually with a switching layer sandwiched between two electrodes, has multilevel conductance
modulated by an electric stimulus. Organized into a crossbar architecture, they can perform analog vector-matrix multiplication within the array using physical
laws. With necessary supporting peripheral circuits, they implemented a neural network that can solve real-world problems.17)

Fig. 2. (Color online) The schematics with exemplary TEM images showing three typical mechanisms responsible for conductance tuning in conduction-
channel based memristors, including the modulation of the width of a conduction-channel, the gap between the channel and an electrode, and the composition
of the conduction-channel. Reprinted from Ref. 17.

typical resistance switching mechanisms in conduction-
channel-based memristors.17) The device conductance could
be changed by modulating the diameter of a conduction-
channel, e.g. in the conduction-bridge type memristor by
applying different levels of compliance.22) However, in such
a case, the reset step is usually strong and abrupt due to the
existence of a metallic bridge. In addition, efficient contin-
uous conductance tuning could be achieved by modulating
the distance of a tunneling gap between the conduction
channel and an electrode.23–25) Since the conduction me-
chanism is tunneling-dominated, the IV relationship of each
state is nonlinear. Consequently, the most promising ap-
proach to obtaining multiple conductance states with the
linear IV behavior is the modulation of the conduction-
channel composition.26–28) In choosing the matrix material, a
simple binary system with only a conductive and an
insulating phase at the switching temperature is beneficial
for higher endurance.26) Based on these principles, we
designed a Ta/HfO2 memristor device that operates on the
motion of mobile species (oxygen vacancies and tantalum
ions) in an amorphous HfO2 matrix, with the analog
switching behavior enabled by the modulation of Ta:O ratio
in the localized conduction channel.
The composition change during the switching is confirmed
with electron energy loss spectroscopy (EELS) of a sub-10
nm Ta-rich and O-deficient conduction channel. As shown in
SM0802-2
Fig. 3. The composition analysis of the conduction channel
suggests that Ta has moved inside of the HfO2 matrix, and
oxygen vacancy is also playing a critical role.
Consequently, the electronic conduction mechanism at the
high-resistance and low-resistance states are distinctly dif-
ferent. As shown in Fig. 4(a), both LRS and HRS showed a
linear I–V relationship at low voltages, indicating no tun-
neling gap between electrodes and the conduction channel,
which is different from the well-studied TiOx−based devices
where a tunneling gap was present and responsible for the
switching behavior. Although the linear I–V relationship can
also be achieved for a metal/insulator/metal (MIM) junction
j
when the applied voltage is very small (≈0 V or = e , where
j is the barrier height and e is the charge of the electron),29) it
is highly unlikely for our case here since the current is
relatively high for our device even at HRS.25) We measured
the device resistance as a function of temperature at both
HRS and LRS. The device at LRS showed a typical metal-
like behavior as its resistance linearly increased with tem-
perature. In contrast, the device at HRS showed a typical
behavior for non-metallic materials in that the resistance
increased with temperature [Fig. 4(b)]. The measured tem-
perature coefficients of resistance (TCR) were 8.75 × 10−4/K
and −4.37 × 10−4/K for LRS and HRS, respectively. The
different signs of the TCR at LRS and HRS suggest that the
modulation of the chemical composition in the conduction
© 2022 The Author(s). Published on behalf of
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Jpn. J. Appl. Phys. 61, SM0802 (2022) PROGRESS REVIEW

(a) (b)

Fig. 3. (Color online) Direct observation of a Ta-rich and O-deficient conduction channel. (a) Comparison of core-loss EELS spectra collected at the pristine
HfO2 layer, conduction channel region and Ta electrode. It indicates the conduction channel is Ta-rich. (b) O-K edge EELS spectra taken at three areas, which
clearly show the conduction channel is also O-deficient.28)

(a) (b)

Fig. 4. (Color online) (a) Linear IV curves for the device at both LRS and HRS. (b) The dependence of the normalized resistance change
(ΔR = (R−R(300 K))/R(300 K)) on temperatures, from where the TCR is measured to be 8.75 × 10−4/K for LRS and −4.37 × 10−4/K for HRS. Reprinted from Ref. 28.

channel rather than the size should be responsible for the
switching in our Ta/HfO2 memristor. The continuous mod-
ulation of the conduction-channel composition leads to
multiple resistance states. It should be noted that if the reset
step is too strong, we may achieve a HRS with a much lower
conductance but poor IV linearity, which is not within the
interested conductance range in our current studies.
Since the most suitable application for a memristor-based
AI accelerator is inference, we chose mobile species with
reasonably high activation energy in our device design.
Table I lists the activation energy of a few ionic species in
different transition metal oxides. Higher activation energy
means the mobile species will not move around once set into
a particular position, suggesting high stability of the resis-
tance state. Although a relatively higher program voltage
may be needed during programming, an inference system is
not trained intensively, so the overall energy footprint is still
low.
3. Electrical properties of the Ta/HfO2 memristors
Our Ta/HfO2 memristor has a simple MIM consisting of an
inert metal Pt (or Pd/Ru) as the bottom electrode (BE), Ta as
the top electrode (TE). A 5 nm atomic layer deposition
prepared HfO2 blanket layer is sandwiched in between as
the switching material. The device exhibits typical resistance
switching behavior under quasi-DC voltage sweeps after an
electrical forming step, turning on when a positive voltage is
applied to the Ta electrode and off when the voltage polarity
switches [Fig. 5(a)]. With a smaller device size, the opera-
tional current of the device is much reduced [Fig. 5(b)]. We
first achieved multiple conductance states from the Ta/HfO2
memristor using different compliance currents and stop
voltages during SET and RESET, respectively, as shown in
Fig. 5(c). In addition, like the potentiation/depression beha-
vior of a biological synapse, we can gradually increase and
decrease the device conductance with a train of electrical
pulses. For example, Fig. 5(d) plots the conductance change
of the Ta/HfO2 memristor in response to 39 electric pulses
(pulse width: 100 ns), including 26 consecutive positive
pulses with the amplitude increased from 0.75 to 1 V, and
13 consecutive negative ones with the amplitude decreased
from −1.05 to −1.17 V (step size: 10 mV step).
The different resistance states are all stable even at higher
temperatures. We programmed the device into eight states
using different compliance currents to examine the stability
of different conductance states. They showed no evident
current fluctuation and drift for over 104 s at 150 °C
[Fig. 6(a)]. To fully evaluate the retention properties,
temperature (T) dependent retention measurements were
performed, and the device failure time (t) at HRS was

Table I. The activation energy of typical mobile species in different oxide matrices.

Mobile species Ag Ag W VO VO VO VO/Ta2+

Host material SiOx a-Si WOx TaOx HfO2 HfAlOx HfO2

Activation energy (eV) 0.27 0.87 0.6–1 1.6 0.7–1.8 1.09 1.55
References 30 31 32 33 34 35 28
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Jpn. J. Appl. Phys. 61, SM0802 (2022) PROGRESS REVIEW

(a) (b)

(c) (d)

Fig. 5. (Color online) (a) Typical IV curves for the Ta/HfO2 device by quasi-DC voltage sweeps (step size: 50 mV) after an electrical forming step (at 2 V)
for a 10 μm device and (b) 100 nm device. The black arrows indicate the switching polarity. (c) Analog resistance tuning in the 10 μm device achieved by
using quasi-DC voltage sweeps with different compliance currents. (d) The gradual modulation of the device conductance can also be achieved using pulse
train consisting of 26 positive pulses (100 ns, 0.75 to 1 V, 10 mV step) and 13 negative pulses (100 ns, −1.05 to −1.17 V, 10 mV step), akin to the potentiation
and depression behavior of a biological synapse.28) The results of (c) and (d) are from the 10 μm devices.

(a) (b)

Fig. 6. (Color online) (a) Retention of eight different conductance states at 150 °C for over 104 s. (b) The fitting plot of measured HRS retention time at
250 °C, 275 °C, 300 °C, 325 °C and 350 °C with the Arrhenius equation (red line). The activation energy of mobile species (Ea) is extrapolated to be 1.55 eV and
the extrapolated retention time is 70258 years at 85 °C and 10 years at 162 °C. Reprinted from Ref. 28. The results here were measured from the 10 μm devices.

2.7 × 105, 7.5 × 104, 1.4 × 104, 2.7 × 103, and 1.3 × 103 s at
250, 275, 300, 325, and 350 °C, respectively [Fig. 6(b)]. The
Arrhenius equation can well fit the t–T relation. The extra-
polated retention time was 7 × 104 years at 85 °C, and
beyond 10 years even at 162 °C. The exceptional stability
was attributed to the relatively higher activation energy of
mobile species (1.55 eV) extrapolated from our Ta/HfO2
when compared with other material systems, as listed in
Table I.
The device also exhibits high endurance, ensuring suffi-
cient programming cycles for the training for many applica-
tions. As shown in Fig. 7, over 1.2 × 1011 open-loop digital
Fig. 7. (Color online) Over 1011 billion digital switching cycles achieved
switching cycles were achieved from the device without any from the Ta/HfO2 memristor with pulses of 1.3 V/100 ns for SET and
feedback or power-limiting circuits, which is the highest −3.05 V/100 ns for RESET. The device states were read at 0.1 V. Reprinted
reported endurance for a single-oxide-layer memristive from Ref. 28. The results here were measured from a 10 × 10 μm2 device.
© 2022 The Author(s). Published on behalf of
SM0802-4 The Japan Society of Applied Physics by IOP Publishing Ltd
Jpn. J. Appl. Phys. 61, SM0802 (2022)
device to the best of our knowledge. The high endurance
likely results from the simple material system with only two
stable solid phases (conductive and insulating at the tem-
perature at which switching occurs.36,37) We expect the
endurance to be improved if measured with a closed-loop
system equipped with a feedback mechanism for the applied
pulses.
The IV linearity of the device depends on the resistance
range. The memristor device has a nonlinear IV behavior,
especially at a high resistance range, and the linear IV usually
occurs at high conductance states. To utilize Ohm’s Law
directly for multiplication, we choose an operation range of
1–11 kiloohms for the proof-of-concept VMM demonstra-
tion. Our device exhibits IV linearity in this range (Fig. 8). It
is worth pointing out that the current level is higher than we
wanted but sufficient for operating the demo array. Future
work is needed to reduce the current level by one or even two
orders of magnitude to suit the array for much larger datasets.
4. Programming of 1T1R single cells and arrays
Access devices or selectors are necessary to precisely
program individual memristors and avoid the sneak path
problem in large-scale arrays. Among the reported options,
transistors are the most mature ones to date. The targeted
memristors can be selected by turning on/off the serially
connected transistor. By controlling the applied gate voltage
of the transistor, a precisely controlled voltage can be
delivered to the memristor for high precision programming.
During inference, all transistors are turned on, and the VMM
of the input voltage vector and the conductance matrix stored
in the memristor array can be performed parallelly in one
step. On the other hand, a two-terminal selector is expected to
yield a smaller cell footprint. However, it still requires further
device engineering on performances, including nonlinearity,
endurance, speed, current density, and variation among
devices and cycles. For example, the requirement for the
endurance of selectors is even higher than memristors since
selectors must be switched during both inference and
training. Furthermore, lacking a designated control port
makes it inconvenient for all two-terminal selectors in a
large array to stay at the on state during the computing since
each connected memristor could be at a different conductance
state. As a result, the one-selector-one-resistance switch
Fig. 8. (Color online) Linear IV occurs at a relatively higher conductance
range for the device. Future engineering will have to reduce the current but
still maintain other properties for VMM.6) The results here were measured by
quasi-DC sweeps with a step size of 50 mV. Device size: 4 × 4 μm2.
SM0802-5
PROGRESS REVIEW
(a)
(b)
Fig. 9. (Color online) (a) The schematic illustration of a 1T1R single-cell
and (b) the band diagrams under different bias conditions. To avoid the
transistor’s body effect, a proper voltage polarity needs to be chosen during
the programming. In this case, a positive VTE sets the device while a positive
VBE resets the device. The PN junctions between the source or drain and the
silicon bulk is reversely biased, avoiding leakage current to the bulk.
(1S1R) architecture is unsuitable, if all possible, for com-
puting purposes, in particular in the analog domain.
4.1. Programming of a single 1T1R cell
Figure 9(a) shows the schematics of a 1T1R single cell with
the memristor BE connected to the source of an NMOS
transistor and the body/substrate grounded. During SET, a
positive voltage of different amplitudes (VTE) is applied to the
memristor TE with the transistor drain grounded (VBE). As
mentioned earlier, positive gate voltages (VGate) of different
amplitudes can enable various current compliances from the
access transistor. To RESET the memristor in the 1T1R cell,
instead of applying a negative VTE as widely practiced in
individual bipolar memristors, a positive VBE to the drain is
used, with TE grounded. With this scheme, the PN junctions
between the source or drain and the substrate are always
reversely biased, avoiding undesired current leakage to the
silicon bulk [Fig. 9(b)]. Using only positive voltages for
programming is also consistent with the availability of
voltage polarity in an integrated circuit, in which the voltages
are usually positive.
4.2. Programming scheme for ex situ training of a
1T1R array
For inference purposes, the conductance of each memristor in
the 1T1R array must be programmed to the target value with
high precision. A write-verify scheme with [Fig. 10(a)] is
adopted for this purpose. After each writing cycle, the device
conductance is read out and compared with the targeted value
to determine if a set or reset step is required next. If the
previous pulse does not increase the device conductance
enough towards the target, the VTE amplitude will be raised
for the next pulse. On the other hand, if the previous pulse
increases the conductance over the target, a reset pulse will
be applied on the BE, and the transistor gate voltage
increased to allow for an efficient conductance reduction.
Each cell in the array will be programmed with multiple read/
write cycles until the difference between the final and target
conductance (Gfinal – Gtarget) is within the defined tolerance.
Figure 10(b) plots a histogram of the Gfinal – Gtarget for the
8,192 devices in a 128 × 64 1T1R array. It exhibits a normal
distribution centering at −4.7 μS with a standard deviation
© 2022 The Author(s). Published on behalf of
The Japan Society of Applied Physics by IOP Publishing Ltd
Jpn. J. Appl. Phys. 61, SM0802 (2022)
(a)
Fig. 10. (Color online) (a) A typical example of programming our Ta/HfO2 memristor to a desired conductance with the feedback tuning algorithm.9) (b) The
histogram of the writing error (the difference between target conductance value and final value) with a standard deviation of 6 μS when the writing tolerance of
±10 μS was used. (c) Experimental conductance writing result of the discrete-cosine transform (DCT) pattern into a 64 × 64 array. Device size: 4 × 4 μm2.
Reprinted from Ref. 6.
(σ) of 6 μS when the writing tolerance of ±10 μS was used to
program the array. The small σ value suggests that more than
64 conductance levels or 6 bits of digital precision can be
achieved from our Ta/HfO2 devices within a device con-
ductance range of 100–900 μS, sufficient for many edge
computing tasks. The equivalent bit-precision, primarily
limited by the intrinsic device noise, could be further
increased by defining a narrower tolerance during program-
ming and/or using a larger number of closed-loop iteration
cycles. With the write-verify scheme, arbitrary conductance
maps corresponding to different algorithms can be written
into the 1T1R array with high precision. For example,
Fig. 10(c) shows the conductance map of a 64 × 64 array
after the discrete-cosine transform (DCT) algorithm was
successfully written.
4.3. Programming scheme for in situ training of a
1T1R array
While an inference system can afford multiple pulses at each
cell during programming because once trained, the system
can be used for a long time, making the overall energy
landscape reasonable. However, for a system that needs
frequent training, one-shot programming is desired to reduce
power consumption. Furthermore, to better map machine
learning algorithms into the conductance map of the array,
linear and symmetric weight updating is essential. This is
SM0802-6
PROGRESS REVIEW
(b)
(c)
difficult for most two-terminal memristive devices because of
the intrinsic device nonlinearity and that conductance change
is history-dependent. With the 1T1R architecture, linear and
symmetric weight updating with one-shot programming
becomes feasible. As shown in Fig. 11(a), two synchronized
electric pulses (VTE/VBE to memristors and Vgate to transis-
tors) are applied, with the VTE staying the same while the gate
voltage increases in each set cycle. For the reset operation, a
large reset pulse is first applied on the BE with the transistor
gate open, and the following conductance tuning is imple-
mented with the VTE and a decreasing transistor gate voltage
[Fig. 11(b)]. With this scheme, the device conductance can be
linearly increased with the gate voltage for Vgate between
0.6 and 1.6 V [Fig. 11(c)]. The linear and symmetric weight
updating with our developed scheme also reduces cycle-to-
cycle and device-to-device variations [Figs. 11(d), 11(e)],
demonstrating it is a reliable scheme for in situ training.
A simple model can be built to understand the linear and
symmetric weight updating.38) When the voltage across a
R
memristor (Vmem = R mem VAppl ) in the 1T1R cell drops
mem + Rtrans
below a threshold voltage (Vmin), the switching process
terminates. Here, Rmem , Rtrans, and VAppl is memristor resis-
tance, transistor channel resistance, and the total applied
voltage, respectively. The assumption is similar to the theory
proposed by Ulrich B. et al. recently.39) After the 1T1R
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The Japan Society of Applied Physics by IOP Publishing Ltd
Jpn. J. Appl. Phys. 61, SM0802 (2022) PROGRESS REVIEW

(a) (b)

(c) (d)

(e)

Fig. 11. (Color online) The developed two-pulse scheme to gradually (a) set and (b) reset the device. (c) 20 cycles of linear and symmetric weight updating
from a representative cell and each cycle contains 200 pulses. (d) Single such weight updating cycle collected from all responsive devices in the array and the
median conductance is indicated by the yellow line. (e) Over 20 such weight updating cycles from all responsive devices in the array. Device size: 4 × 4 μm2.
Reprinted from Ref. 7.

system stabilized, we have Rmem = Rtrans / VAppl - 1 or ( V

) 4.4. Parallel programming of the 1T1R array
V
( )
equivalently Gmem = Gtrans VAppl - 1 , where Gmem and
min
min

Gtrans are memristor and transistor channel conductance. As

VAppl
Vmin
is a constant, the final Gmem should be linearly dependent
on Gtrans and hence on the gate voltage when VGate > Vth
(transistor threshold voltage).
It should be noted that with the one-shot programming, the
conductance tuning may not be as accurate as in the write-
verify approach. However, the advantage in energy con-
sumption is evident. Furthermore, for machine learning
algorithms based on stochastic gradient descent optimization,
the error in programming will be compensated by the
neighboring cells, as proved by our previous studies,7)
suggesting the importance of device-circuit-architecture-al-
gorithm co-design. The device requirements for in situ
training are more relaxed than those for inference or a
memory system, indicating that the memristor device is a
better candidate for neural computing than memory applica-
tions, as the device variation is considered a roadblock for
their wide adoption in memory products.
It is critical to develop schemes that can program the array
with high throughputs. With the 1T1R configuration, it is
possible to set or reset a crossbar array in a row-by-row or
column-by-column fashion. Figure 12 illustrates how such
parallel programming is implemented. During the reset
process, a reset pulse is applied to the BEs of the entire
column with all the transistors in the same column open. The
voltage on the TEs dictates which memristors will be reset.
For a set process, on the other hand, a voltage pulse is applied
to all the TEs of memristors on the same row, and the gate
voltages for the serial transistors vary, leading to the tuning
of the conductance states of the memristors on the same row
simultaneously.
5. Memristive neural networks
The superior energy efficiency and computing throughputs
enabled by physical computing in the crossbar make the
1T1R array an ideal module for neural networks, especially
for the VMM operations that are usually resource-hungry in

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Jpn. J. Appl. Phys. 61, SM0802 (2022) PROGRESS REVIEW

(a) (b)

Fig. 12. (Color online) Column or row-wise parallel programming of the 1T1R crossbar array. (a) During reset, a reset pulse is applied to the bottom
electrodes of an entire column simultaneously, while the top-electrode voltages control which devices are reset. (b) For the set process, a set pulse is applied on
the top electrodes of an entire row, and the different transistor gate voltages determine the how much each memristor’s conductance is changed.7)

most typical neural network topographies. However, such
neural networks are mixed-signal systems, which would not
be possible without peripheral circuitry such as DACs
(digital-analog converters) for generating driving pulses and
ADCs (analog-digital converters) for collecting the measure-
ment data. Sample and hold circuits may be used to
synchronize all the output signals better, and trans-impedance
amplifiers to convert the sensed current into a voltage signal.
Figure 13 shows an exemplary system that also has a digital
computer and a microcontroller, in which the computer is
used to run scripts from different algorithms, and the
microcontroller controls all the circuit components. These
peripheral circuit components are critical to ensure the
synchronization of the signals (such as the voltages on the
memristor electrodes and transistor gates), and a professional

Fig. 13. (Color online) An exemplary system consisting of a 1T1R memristor crossbar array and peripheral circuitry that supports the operation. The proper
design of such a system calls for both device knowledge and mixed-signal circuit expertise. Reprinted from Ref. 7.
© 2022 The Author(s). Published on behalf of
SM0802-8 The Japan Society of Applied Physics by IOP Publishing Ltd
Jpn. J. Appl. Phys. 61, SM0802 (2022)
design is required to utilize the advantages of both the
traditional and emerging technologies.
To implement neural networks with more than one layer,
the data flow is a critical issue. Previously we have used
different partitions of the same array as separate layers in a
neural network. For example, by partitioning a 128 × 64
array into two layers, we built a two-layer perceptron that
was used to classify MNIST handwritten digits with high
accuracy.7) By partitioning the array into three fully con-
nected layers, we implemented the reinforcement learning
algorithm.12) Similar techniques were adopted to demonstrate
recurrent neural networks with long short-term memory units
for time-sequence data analysis8) and convolutional recurrent
neural networks.40)
For the aforementioned multilayer networks, the output of
one layer should be nonlinearly activated before being fed to
the subsequent layer. This could be implemented in software,
in which the analog signals from the earlier layer are
converted to digital before they can be nonlinearly activated.
This step usually is a bottleneck that limits the system
performance. To address this issue, a two-layer perceptron
with both hardware neurons and synapses was designed and
built (Fig. 14).41) In this proof-of-concept system, two
128 × 64 1T1R arrays were used as the first and second
fully connected layers in the perceptron, connected by a stack
Fig. 14. (Color online) A two-layer all hardware perceptron. The upper panel shows the circuit schematic of the perceptron. The lower panel shows the
optical images of a 1T1R crossbar for the first layer, a stack of PCBs of the hidden neurons (ReLUs), and a second crossbar for the second fully connected
layer. The hardware neurons contain a total of 64 channels of ReLU activation functions and 64 inverters to support 64 differential pairs for the second layer.
Scale bar, 1 mm. Reprinted from Ref. 41.
SM0802-9
PROGRESS REVIEW
of printed circuit boards (PCBs) that contain the hardware
neurons built with off-the-shelf electronic components. The
fully hardware-based neural network was used in demon-
strating high-accuracy object classification. By substantially
reducing the resource-demanding data shuttling and analog-
digital conversions, it delivers much-improved power and
area efficiencies, as estimated based on the 65 nm CMOS
node.
6. Summary and perspective
Guided by the fundamental physical principle and the
required device properties for computing, we have developed
a Ta/HfO2 memristor that meets most of the requirements for
in-memory computing in artificial neural networks. The
device exhibits stable multilevel conductance states, analog
tunability, high endurance, long retention, and decent IV
linearity within certain conductance ranges. Integrated with a
transistor into a 1T1R crossbar array, the conductance of each
cell can be precisely tuned for an inference system and
modulated linearly and symmetrically with one-shot pro-
gramming for an online training system. Taking the resource-
demanding tasks, the vector-matrix operation, the 1T1R
memristor crossbar array brings advancement in energy
efficiency and computing throughput, owing to the capability
of parallel analog computing in the physical domain.
© 2022 The Author(s). Published on behalf of
The Japan Society of Applied Physics by IOP Publishing Ltd
Jpn. J. Appl. Phys. 61, SM0802 (2022)
Despite the demonstrated potential in implementing var-
ious neural networks, extensive future work spanning from
fundamental device physics to algorithms is needed to fully
unleash this technology’s potential. Understanding the under-
lying mechanism of the nonlinear switching behavior in
amorphous/crystalline heterogeneous systems is essential to
achieving controllable memristive behavior. The defects in
the switching layer dictate the device behavior, and how the
ions and charges interplay at these sites remains unsolved.
New characterization techniques are yet to be developed to
better understand the device’s physics, especially at the
atomic scale. Analog systems are usually more susceptible
to noise. In addition to figuring out the noise source and
characteristics, it is essential to understand the fundamental
limits of such noises on the computing capability of an array.
The knowledge gained in this aspect will lead to a better-
designed system with better-utilized analog properties.
To the end of device engineering, a lower operational
current is desired to reduce the power consumption.
However, a question mark is whether other critical metrics
such as multilevel conductance, stability of resistance levels,
and IV linearity will be preserved for a low-current device.
Other longstanding problems for the filamentary type of
memristors are the requirement of an electrical forming step,
which can be power consumption and even destructive, and
the cycle-to-cycle and device-to-device variability. Also
lacking on the device level is a two-terminal selector with
very high performance, especially endurance. Even when
such a device becomes available, plenty of work needs to be
done to properly use them, if possible, in computing
applications.
Low power peripheral circuits for memristive neural net-
works are vital on the circuit level. It was estimated that data
conversation consumes most of the power in memristor-
based deep learning accelerators. As a result, there is a great
need to balance the bit-precision of the DAC/ADCs and the
final computing requirements for a specific task. Given that
we use two 1T1R cells at different rows (a differential pair) to
represent synaptic weight, the physical array is usually
asymmetric (more rows than columns). As such, it is very
challenging to implement the backpropagation algorithm that
is critical in training. Creative circuit design with symmetric
topography and negative weight capability is imperative.
From the algorithm perspective, analog error-correction42)
will help mitigate and even compensate for the performance
degradation resulting from the device variation and circuit
defects. One example is the voltage drop from the left to the
right of the array when the array size becomes huge and the
wire resistance is significant. A compensation algorithm
could improve the computing accuracy.43) Given that some
other defects are not predictable, a more flexible correction or
compensation algorithm should be developed.
Nevertheless, the device has shown great potential,
although challenges remain. Experts across disciplines must
work together, taking a co-design and co-optimization
approach to take the technology to the market, with the
promised energy efficiency and computing throughput.
SM0802-10
PROGRESS REVIEW
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