SOUTHERN UNIVERSITY COLLEGE

SEMESTER C

YEAR 2020 / 2021

FINAL EXAM

BALS3033 LOGIC SYSTEM DESIGN

DATE : 20/1/2021 DURATION : 2 HOURS 30 MINUTES

BACHELOR OF ENGINEERING (HONOURS) IN ELECTRONIC ENGINEERING

YEAR THREE

Instruction to Candidates :

1. Answer ALL questions. All questions carry equal marks.

2. All answers must be written on the answer sheet with pen.
3. Begin to answer each new question on a new page.
4. Programmable and Semi-Programmable Scientific Calculators are PROHIBITED to use.
5. Return the question paper together with your answer booklet.

This question paper consists of 4 questions on 5 printed pages.

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BALS3033 LOGIC SYSTEM DESIGN

Q1. (a) Justify why the Hardware Description Language Design is more reliable
compare to Schematic Design. (6 marks)

(b)

Figure 1

(i) Write the structural Verilog code for the combinational circuit shown
in Figure 1. (12 marks)

(ii) Write the behavioral Verilog code for the combinational circuit
shown in Figure 1. (7 marks)
[Total : 25 marks]

Q2. (a) Determine if there are differences if the following two modules are
synthesized. (4 marks)

module reg1(Q1,Q2,Q3,Q4,A,CLK); module reg1(Q1,Q2,Q3,Q4,A,CLK);

input A; input A;
input CLK; input CLK;
output Q1, Q2, Q3, Q4; output Q1, Q2, Q3, Q4;
reg Q1, Q2, Q3, Q4; reg Q1, Q2, Q3, Q4;
always @(posedge CLK) always @(posedge CLK)
begin begin
Q1<=A; Q4<=Q3;
Q2<=Q1; Q3<=Q2;
Q3<=Q2; Q2<=Q1;
Q4<=Q3; Q1<=A;
end end
endmodule endmodule

This question paper consists of 4 questions on 5 printed pages.

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BALS3033 LOGIC SYSTEM DESIGN

Q2. (Continued)

(b) A 4-to-1 multiplexer (as shown in Figure 2) has an inherent delay that causes
the change in output to occur 10ns after a change in input.

Figure 2

(i) Write a conditional signal assignment statement to represent the 4-to-1

MUX. (2 marks)

(ii) Repeat (i) using an if-else statement. (5 marks)

(iii) Repeat (i) using a case statement. (6 marks)

(c) Construct a Verilog code to implement the circuit in Figure 3. (8 marks)

X1
X2
Inpu U1 U2
T Q T Q T Q T Q
Q[0] Q[1] Q[2] Q[3]
t T0 T1 T2 T3
Clock Qbar Qbar Qbar Qbar

reset

Figure 3

[Total : 25 marks]

This question paper consists of 4 questions on 5 printed pages.

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BALS3033 LOGIC SYSTEM DESIGN

Q3. (a) (i) Determine the state table and state diagram using a Moore system
whose output changes whenever it detects a sequence 110, as shown in
the table. Assume that initially, the output is 0.

x 0 0 1 0 1 1 1 0 1 1 0 0 1 1 0 1 0 1 - -
z 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 1
(6 marks)

(ii) Consider a sequence detector that receives a bit-serial input Y and

asserts an output Z=1 if and only if there have been exactly four 1’s
detected consequently in a row. Use symbolic states with letters such
as A, B and etc. Assume that “A” is start state, in which the machine
can start out or reset. Develop the state table by using Mealy machine
state diagram (8 marks)

(b) Figure 4 shows the Finite State Machine (FSM), where C is an input, and a
and b are output.

Figure 4

(i) Construct a next-state table for the FSM circuit. (4 marks)

(ii) Develop the next-state equations and output equations. (3 marks)

(iii) Develop the Finite State Diagram (4 marks)

[Total : 25 marks]

This question paper consists of 4 questions on 5 printed pages.

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BALS3033 LOGIC SYSTEM DESIGN

Q4. A4 4 keypad scanner for the keypad layout is shown in Figure 5.

Figure 5

(a) Assuming only one key can be pressed at a time, interpret the equations for a
number decoder given , , , and , , , , whose output
corresponds to the binary value of the key. For example, the F key will return
1111 in binary, or 15. (5 marks)

(b) Design a debouncing circuit that detects whether a key has been pressed or
depressed. Assume switch bounce will die in one or two clock cycles/ when a
key has been pressed, K=1 and Kd is the debounced signal. (2 marks)

(c) Draw a state diagram that performs the keyscan and issues a valid pulse when
a valid key has been pressed using inputs from (b). (4 marks)

(d) Write a Verilog code for your keypad scanner and include the decoder, the
debouncing circuit, and the scanner. (14 marks)
[Total : 25 marks]

________________________________________

This question paper consists of 4 questions on 5 printed pages.