PES University

(Established Under Karnataka Act 16 of 2013)

100-ft Ring Road, BSK 3rd Stage, Bangalore – 560085

Department of Electronics and Communication Engineering

Digital VLSI Design Lab

Jan – May 2023

EXPERIMENT - 7
CMOS Master Slave JK Flip Flop using 2 input NOR gates
 EXPERIMENT-7
CMOS Master Slave JK Flip Flop using 2 input NOR gates
Design and determine:
Power Results, Delay and verify the truth tables from the waveforms obtained

Theory:
The input latch called the "master," is activated when the clock pulse is high. During this
phase, the inputs J and K allow data to be entered into the flip-flop, and the first-stage
outputs are set according to the primary inputs. When the clock pulse goes to zero, the
master latch becomes inactive and the second-stage latch, called the "slave," becomes
active. The output levels of the flip-flop circuit are determined during this second phase,
based on the master-stage outputs set in the previous phase. Since the master and the slave
stages are effectively decoupled from each other with the opposite clocking scheme, the
circuit is never transparent, i.e., a change occurring in the primary inputs is never reflected
directly to the outputs. Because the master and the slave stages are decoupled from each
other, the circuit allows for toggling when J = K = "1," but it eliminates the possibility of
uncontrolled oscillations since only one stage is active at any given time.

Working of a master slave flip flop :

1. When the clock pulse goes to 1, the slave is isolated; J and K inputs may affect the state of
the system. The slave flip-flop is isolated until the CLK goes to 0. When the CLK goes back to
0, information is passed from the master flip-flop to the slave and output is obtained.
2. Firstly the master flip flop is positive level triggered and the slave flip flop is negative level
triggered, so the master responds before the slave.
3. If J=0 and K=1, the high Q’ output of the master goes to the K input of the slave and the
clock forces the slave to reset, thus the slave copies the master.
4. If J=1 and K=0, the high Q output of the master goes to the J input of the slave and the
Negative transition of the clock sets the slave, copying the master.
5. If J=1 and K=1, it toggles on the positive transition of the clock and thus the slave toggles
on the negative transition of the clock. 6. If J=0 and K=0, the flip flop is disabled and Q
remains unchanged.
This makes the Master-Slave J-K flip flop a Synchronous device as it only passes data with
the timing of the clock signal.
Testbench Schematic:
 Note: Add Tran_NONINVERTING_DELAY and Power_voltageSourcePrint
probes as well. And make sure to use V pulse instead of random bit generator.

Transient analysis:

MS JK FF

Power Results

Delay

Verify the truth tables with their respective transient analysis waveforms

Student Name:

Student SRN:

Faculty Signature with date: