PES University

(Established Under Karnataka Act 16 of 2013)

100-ft Ring Road, BSK 3rd Stage, Bangalore – 560085

Department of Electronics and Communication Engineering

Digital VLSI Design Lab

Jan – May 2023

EXPERIMENT - 8
Asynchronous and Synchronous counters (3-bit) using D FF
 EXPERIMENT-8
Asynchronous and Synchronous counters (3-bit) using D FF
Design and determine:
Power Results, Delay and verify the truth tables from the waveforms obtained

Theory:
Asynchronous counter: Asynchronous counters are those whose output is free from the clock
signal. Because the flip flops in asynchronous counters are supplied with different clock
signals, there may be delay in producing output. The output of system clock is applied as clock
signal only to first flip-flop. The remaining flip-flops receive the clock signal from output of its
previous stage flip-flop.
The required number of logic gates to design asynchronous counters is very less. So, they are
simple in design. Another name for Asynchronous counters is “Ripple counters”.
The number of flip flops used in a ripple counter is depends up on the number of states of
counter (ex: Mod 4, Mod 2 etc). The number of output states of counter is called “Modulus”
or “MOD” of the counter. The maximum number of states that a counter can have is 2n where
n represents the number of flip flops used in counter.

Asynchronous 3-bit up counter: The clock inputs of all flip flops are cascaded and the D input
(DATA input) of each flip flop is connected to a state output of the flip flop.
That means the flip flops will toggle at each active edge or positive edge of the clock signal.
The clock input is connected to first flip flop. The other flip flops in counter receive the clock
signal input from Q’ output of previous flip flop. The output of the first flip flop will change,
when the positive edge on clock signal occurs. The rising edge of the Q output of each flip flop
triggers the clock input of its next flip flop. It triggers the next clock frequency to half of its
applied input.

Asynchronous 3-bit down counter: The clock inputs of all flip flops are cascaded and the D
input (DATA input) of each flip flop is connected to logic 1. That means the flip flops will toggle
at each active edge (positive edge) of the clock signal. The clock input is connected to first flip
flop. The other flip flops in counter receive the clock signal input from Q output of previous
flip flop, rather than Q’ output. The output of the first flip flop will change, when the positive
edge of clock signal occurs. The input clock will cause the change in output (count) of the next
flip-flop.
Synchronous counter: The synchronous counter contains flip-flops which are all in sync with
each other i.e., their clock inputs are connected together and are triggered by the same
external clock signal. This implies that all the flip-flops update its value at the same time. The
result of this synchronization is that all the individual output bits changing state at exactly the
same time in response to the common clock signal with no ripple effect and therefore, no
propagation delay.

Synchronous 3-bit up counter: D-Flip flop updates its state according to the input applied to
it i.e., Q = D. Q0 is continuously changing so the input to FF0 will be D0 = Q̅ 0. Because it will
toggle the state whenever a clock pulse hits the FF0. Q1 = 1, when its previous state
Q1 &Q0 are not equal & Q1 = 0, when its previous state Q1 &Q0 are equal. That is the same
as XOR operation. So D1 = Q1 XOR Q0.
Q2 = 1, when in its previous state the AND of Q1 & Q0 is not equal to Q2. Q2 = 0, when in its
previous state the AND of Q1 & Q0 is equal to Q2.So D2 = Q2 XOR (Q1& Q0)
Transient analysis(Asynchronous 3-bit up counter):

Transient analysis(Asynchronous 3-bit down counter):

Transient analysis(Synchronous 3-bit up counter):

 Asynchronous 3-bit up Asynchronous 3-bit down Synchronous 3-bit up
counter counter counter

Power Results

Delay

Student Name:

Student SRN:

Faculty Signature with date: