PES University

(Established Under Karnataka Act 16 of 2013)

100-ft Ring Road, BSK 3rd Stage, Bangalore – 560085

Department of Electronics and Communication Engineering

Digital VLSI Design Lab

EXPERIMENT - 4
2 Input CMOS NAND and NOR gate
 EXPERIMENT-4
2 Input CMOS NAND and NOR gate

Design and determine:

Rise and Fall time,
Power results and
Frequency of CMOS NAND and NOR gates.
After analyzing and obtaining the results for the NAND and NOR schematics, draw the layout
for both NAND and NOR gates and perform the required checks.
In the end compare the simulation results for the schematics and layout designs for NAND
and NOR gates.

Theory:
NAND gate: The n-net consisting of two series-connected nMOS transistors creates a
conducting path between the output node and the ground only if both input voltages are
logic-high, i.e., are equal to VOH. In this case, both parallel-connected pMOS transistors in the
p-net will be off. For all other input combinations, either one or both of the pMOS transistors
will be turned on, while the n-net is cut-off, thus creating a current path between the output
node and the power supply voltage.
By De Morgan's theorem, AB=A+B, and thus a NAND gate is equivalent to inverters followed
by an OR gate. The NAND gate is significant because any Boolean function can be
implemented by using a combination of NAND gates. This property is called functional
completeness. It shares this property with the NOR gate.

X Y

Y
NOR gate: When either one or both inputs are high, i.e., when the n-net creates a conducting
path between the output node and the ground, the p-net is cut-off. On the other hand, if both
input voltages are low, i.e., the n-net is cut-off, then the p-net creates a conducting path
between the output node and the supply voltage VDD. Thus, the dual or complementary
circuit structure allows that, for any given input combination, the output is connected either
to VDD or to ground via a low-resistance path. A DC current path between the VDD and
ground is not established for any of the input combinations.
NOR can also be seen as an AND gate with all the inputs inverted. NOR is a functionally
complete operation. NOR gates can be combined to generate any other logical function. It
shares this property with the NAND gate. By contrast, the OR operator is monotonic as it can
only change LOW to HIGH but not vice versa.

X
Z
X Y

Schematic (NAND):
Testbench Schematic (NAND):

Schematic (NOR):
Testbench Schematic (NOR):

Transient analysis (NAND):

Transient analysis (NOR):

Layout (NAND):

Note: Use the above figure as reference for layout design.

Similarly, design the layout for CMOS NOR gate.
All 3 checks i.e., DRC, LVS and PEX MUST be conducted for BOTH the layouts.
All the simulation results for layout netlist as well must be noted.
 Note down the following Observations made:

Parameters Schematic Layout

Input Rise Time

Output Rise Time

Input Fall Time

Output Fall Time

Input Frequency

Output Frequency

Power results

Student Name:

Student SRN:
Faculty Signature with date: