Sahand University of Technology

The three major operations done on biological signals using Op-Amp:

1) Amplifications and Attenuations

2) DC offsetting: add or subtract a DC
3) Shape its frequency content: Filtering

2
 Ideal Op-Amp
Most bioelectric signals are small and require amplifications

Figure 3.1 Op-amp equivalent circuit.

The two inputs are 1 and  2. A differential voltage between them
causes current flow through the differential resistance Rd. The
differential voltage is multiplied by A, the gain of the op amp, to
generate the output-voltage source. Any current flowing to the output
terminal vo must pass through the output resistance Ro.
3
 Inside the Op-Amp (IC-chip)

20 transistors
11 resistors
1 capacitor

4
 Ideal Characteristics

1- A =  (gain is infinity)
2- Vo = 0, when v1 = v2 (no offset voltage)
3- Rd =  (input impedance is infinity)
4- R0 = 0 (output impedance is zero)
5- Bandwidth =  (no frequency response limitations) and no phase shift
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 Two Basic Rules

Rule 1
When the op-amp output is in its linear range, the two input terminals
are at the same voltage.

Rule 2
No current flows into or out of either input terminal of the op amp.
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 Inverting Amplifier
o
i
Rf 10 V

i
Ri -10 V 10 V
i 
o i
+
Slope = -Rf / Ri
(a)
-10 V

(b)
Rf vo Rf
vo   vi G 
Ri vi Ri

Figure 3.3 (a) An inverting amplified. Current flowing through the

input resistor Ri also flows through the feedback resistor Rf . (b) The
input-output plot shows a slope of -Rf / Ri in the central portion, but the
output saturates at about ±13 V.
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Summing Amplifier
R1
Rf
1
  v1 v2 
R2 o vo   R f   
2 +  R1 R2 

Example 3.1: The output of a +10

i
biopotential preamplifier that measures
the electro-oculogram is an undesired dc
voltage of ±5 V due to electrode half-cell i + b /2

Voltage, V
o 0
potentials, with a desired signal of ±5 V Time

superimposed. Design a circuit that will

balance the dc voltage to zero and
provide a gain of -10 for the desired -10 o
signal without saturating the op amp.
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The output of a biopotential preamplifier that measures the electro-
oculogram is an undesired dc voltage of ±5 V due to electrode half-
cell potentials, with a desired signal of ±5 V superimposed. Design a
circuit that will balance the dc voltage to zero and provide a gain of -
10 for the desired signal without saturating the op amp.

+10
i

Voltage, V i + b /2
o 0
Time

-10 o

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 Follower ( buffer)
Used as a buffer, to prevent a high source resistance from being
loaded down by a low-resistance load. An another word it prevent
drawing current from the source.

o
i +

vo  vi G 1

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Noninverting Amplifier

o
i i 10 V
Ri Rf Slope = (Rf + Ri )/ Ri

-10 V 10 V

i
-

o
i
-10 V
+
R f  Ri R f  Ri  Rf 
vo  vi G  1  
Ri Ri  Ri 

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 Differential Amplifiers
Differential Gain Gd
vo R4 R4 R3 R4
Gd   vo  (v4  v3 ) v3
v4  v3 R3 R3
R3
v4 vo

Common Mode Gain Gc R4

For ideal op amp if the inputs are equal then the
output = 0, and the Gc =0. No differential
amplifier perfectly rejects the common-mode
voltage.
Common-mode rejection ratio CMMR
Gd
CMRR  Typical values range from 100 to 10,000
Gc
Disadvantage of one-op-amp differential amplifier is its low input resistance
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Instrumentation Amplifiers

Differential Mode Gain

v3  v4  i ( R2  R1  R2 )
v1  v2  iR1
v3  v4 2 R2  R1
Gd  
v1  v2 R1

 2 R2  R1  R4
vo    v2  v1 
 R1  R3
Advantages: High input impedance, High CMRR, Variable gain
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Comparator – No Hysteresis
+15

v2
v1 > v2, vo = -13 V
v1 < v2, vo = +13 V
-15

o
R1
10 V
i


R1 o -10 V
ref + ref i
R2

-10 V

If (vi+vref) > 0 then vo = -13 V else vo = +13 V

R1 will prevent overdriving the op-amp 14
 Comparator – With Hysteresis
Reduces multiple transitions due to mV noise levels by moving the
threshold value after each transition.

o
R1
i 10 V With hysteresis


R1 o -10 V 10 V
ref + - ref
R2 i

R3
-10 V

Width of the Hysteresis = 4 x VR3

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 Rectifier R
D1 D2 o
xR (1-x)R 10 V


-10 V 10 V
i i Ri = 2 kW Rf = 1 kW
+ i vo
R
 D
D4 i -10 V RL = 3 kW
o=
D3 x +

(b) (c)
+
(a)

(a) Full-wave precision rectifier. For i > 0, the noninverting amplifier

at the top is active (D2 and D3 are on), making o > 0. For i < 0, the
inverting amplifier at the bottom is active, making o > 0. Circuit gain
may be adjusted with a single pot. (b) Input-output characteristics show
saturation when o > +13 V. (c) One-op-amp full-wave rectifier. For i
< 0, the circuit behaves like the inverting amplifier rectifier with a gain
of +0.5. For i > 0, the op amp disconnects and the passive resistor
chain yields a gain of +0.5. 16
 RectifierR
D1 D2
xR (1-x)R
R


i +
xRi (1-x)R
R vo
 D
D4 i
o=
D3 x i +

(a)
+

a) For i > 0, D2 and D3 conduct, whereas D1 and D4 are reverse-

biased.
b) For i < 0, D1 and D4 conduct, whereas D2 and D3 are reverse-
biased. 17
 Logarithmic Amplifiers
Rf /9 vo
Ic
10 V

Rf -10 V 10 V
Ri
i  1 i
o
+
-10 V 10
(b)
(a)

 IC   vi 
VBE  0.06 log  vo  0.06 log  at 27 oC
13 
 IS   i
R  10 
Figure 3.8 (a) A logarithmic amplifier makes use of the fact that a
transistor's VBE is related to the logarithm of its collector current. With
the switch thrown in the alternate position, the circuit gain is increased
by 10. (b) Input-output characteristics show that the logarithmic relation
is obtained for only one polarity; 1 and 10 gains are indicated. 18
 Logarithmic Amplifiers

Antilog (exponential) circuits are made by interchanging the resistor

and semiconductor.

Uses of Log Amplifier

1. Multiply variable
2. Divide variable
3. Raise variable to a power
4. Compress large dynamic range into small ones
5. Linearize the output of devices

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 Integrators

t1
1
vo  
Ri C f  v dt  v
0
i ic

Vo ( j ) Zf

Vi ( j ) Zi vo  R f
 for f < fc
Vo  j   R f
vi Ri
1

Vi  j  Ri 1  j fc 
1
2R f C f
A large resistor Rf is used to prevent saturation 20
 Integrators

Figure 3.9 A three-mode integrator With S1 open and S2 closed, the

dc circuit behaves as an inverting amplifier. Thus o = ic and o can
be set to any desired initial conduction. With S1 closed and S2 open,
the circuit integrates. With both switches open, the circuit holds o
constant, making possible a leisurely readout. 21
 Example 3.2
The output of the piezoelectric sensor may be fed directly into the
negative input of the integrator as shown below. Analyze the circuit
of this charge amplifier and discuss its advantages.
isC = isR = 0 R
i
vo = -vc s

C
dqs/ dt = is = K dx/dt 

o
isC isR
+ FET

Piezo-electric
sensor

1 t1 Kdx Kx
vo    dt  
C 0 dt C
Long cables may be used without changing sensor sensitivity or time
constant. 22
 Differentiators

dvi
vo   RC
dt
Vo ( j ) Zf
   jRC
Vi ( j ) Zi

Figure 3.11 A differentiator The dashed lines indicate that a small

capacitor must usually be added across the feedback resistor to
prevent oscillation. 23
 Active Filters- Low-Pass Filter Cf

Vo  j   R f 1 Rf

Ri
i 
Vi  j 
Gain = G =
Ri 1  jR f C f +
o

(a)
|G|

Rf/Ri
0.707 Rf/Ri

freq
fc = 1/2RiCf

Active filters
(a) A low-pass filter attenuates high frequencies
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 Active Filters (High-Pass Filter)
Rf

Vo  j   R f jRi Ci
Ci Ri
i 
o
Gain = G = 
Vi  j 
+
Ri 1  jRi Ci (b)
|G|

Rf/Ri
0.707 Rf/Ri

fc = 1/2RiCf freq
Active filters
(b) A high-pass filter attenuates low frequencies and blocks dc.
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 Active Filters (Band-Pass Filter)
Cf

Vo  j   j R f C i Ci R Rf

Vi  j  1  jR f C f 1  jRi Ci 
i

i
o
+

|G| (c)

Rf/Ri
0.707 Rf/Ri

fcL = 1/2RiCi fcH = 1/2RfCf freq

Active filters
(c) A bandpass filter attenuates both low and high frequencies. 26
Frequency Response of op-amp and Amplifier

Open-Loop Gain
Compensation
Closed-Loop Gain
Loop Gain
Gain Bandwidth Product
Slew Rate

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 Input and Output Resistance

Ro o
ii Rd d
+
Ad io
i 
+ RL CL

vi vo Ro
Rai   ( A  1) Rd Rao  
ii io A  1
Typical value of Rd = 2 to 20 MW Typical value of Ro = 40 W
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Phase-Sensitive Demodulator

Used in many medical

instruments for signal detection,
averaging, and Noise rejection

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 The Ring Demodulator
If vc is positive then D1 and D2 are forward-biased and vA = vB. So vo = vDB

If vc is negative then D3 and D4 are forward-biased and vA = vc. So vo = vDC

vc  2vi
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