Sequential Digital Systems: Memory Devices: Pinit Kumhom

Sequential Digital Systems: Memory Devices
Pinit Kumhom
vLSI Design for embedded Systems with intelligence (vDeSi) Lab

Department of Electronic and Telecommunication Engineering
Faculty of Engineering
King Mongkut’s University of Technology Thonburi
September 16, 2016
Pinit Kumhom (vDeSi Lab, KMUTT) Memory Devices September 16, 2016 1 / 26
Outline
1 What are expected to be learnt?
2 Bistable Element
3 SR Type Memory Devices
Basic SR Latch
SR Latches with Enable (Gated SR Latch)
Mater-Slave SR Flip-Flops
4 D Type Memory Devices
D Latches
D Flip-Flops
5 JK Type Memory Devices
Master-Slave JK Flip-Flops
Edge-Triggered JK Flip-Flops
6 Toggle (T) Flip-Flops
What are expected to be learnt after this learning session?
Be able to answer the following questions or describe the following terms from own
understanding.
What is the basic element for all memory devices? How to

implement it using logic gates?
What are the basic control functions of a memory devices?
Be able to catagorize memory devices based on excitations.
Be able to read a function table or symbol of a memory device.
Be able to generate a function table and/or symbol of a memory
device given its name.
Be able to recognize logic circuits of basic memory elements.
Be able to derive the characteristic equation and excitation table of
a given memory device.
To be able to remember a digital value (’0’ or ’1’), we need a bistable element.
In digital system, a bistable element can be achieved by the cross configuration of 2
inverters
Actually there are 3

stable states.
The metastable state
is the unwanted stable
state.
If the device stays
there, it then may
change to either 0 or 1,
unpredictably or
uncontrollably.
Outline
2 Bistable Element
Basic SR Latch
D Latches
D Flip-Flops
Want bistable element that can be set (S) or Reset (R), but the inverter cross
configuration is cannot do that.
Cross configuration of NORs or NANDs is such bistable element. It is called a SR Latch
Function Table
S R Q Qn Action
0 0 Qold Q̄old Rember
0 1 0 1 Reset
1 0 1 0 Set
1 1 0 0 Not allowed
Characteristic Equation: Q′ = S + R̄Q
Function Table
Sn Rn Q Qn Action
0 0 1 1 Not allowed
0 1 1 0 Set
1 0 0 1 Reset
1 1 Qold Q̄old Remember
The characteristic equation of a memory device decribes next output, Q′ , as a
logic function of its excitation inputs and current output,Q.
It can be derived from the truth table (the characteristic table) describing how it works
SR Latch Characteristic Table Q′ = S + R̄Q

S R Q Q′ Operation
0 0 0 0 Rember
• Q′ is the next output
0 0 1 1 Rember
• Q is the current output
0 1 0 0 Reset
0 1 1 0 Reset • S and R are the excitation
inputs
1 0 0 1 Set
1 0 1 1 Set
1 1 0 − Not allowed
1 1 1 − Not allowed
The term “−” is called “don’t care” term ⇒ its value can be either ’0’ or ’1’.
Don’t care terms at an output ⇒ it can be assigned as either ’0’ or ’1’
during the synthesis process (e.g. Kmap, QM) based on the design
constraints.
Cross configuration of NANDs gives the active-low SR latch
Function Table
Sn Rn Q Qn Action
0 0 1 1 Not allowed
0 1 1 0 Set
1 0 0 1 Reset
1 1 Qold Q̄old Remember
Characteristic Equation:
Q′ = S̄n + Rn Q
For both active-low and active high, we can say that “SR-latch Operation or
Characteristics” is as follows:
If S is active and R is not active, Q is Set to ’1’.
If S is not active and R is active, Q is Reset to ’0’.
If both S and R are not active, Q stays the same as the previous value.
If both S and R are active, Q and Qn are the same, which is conflicted.
Hence, it is NOT Allowed.
We control memory device output by controlling its excitation inputs.
SR Latch Excitation
For both active-low and active high, we state about “SR-latch excitation” as
follows:
To Set it to ’1’, activate S and deactivate R.

To Reset to ’0’, activate R and deactivate S.
To remember old value, deactivate both S and R.
Having both S and R active at the same time (conflicted order) is NOT
allowed.
Excitation Table for SR Latch Excitation Table for active-high SR Latch

Changes Excitation Action Changes Excitation Action
Q→Q′ S R Q→Q′ S R
0 →0 Not active Not active Remember ’0’ 0 →0 0 0 Remember ’0’
0 →1 Active Not active Set 0 →1 1 0 Set
1 →0 Not Active Active Reset 1 →0 0 1 Reset
1 →1 Not Acitve Not Active Remember ’1’ 1 →1 0 0 Remember ’1’
Outline
2 Bistable Element
Basic SR Latch
D Latches
D Flip-Flops
Problem with the basic SR Latches:
Sometimes, small gliches on S or R or both can lead to remembering (or
latching) a wrong data.
Solution: Adding a control input, denoted by C, to control the effect of S and R.
It is called Controlled SR Latch or Gated SR Latch or SR Latch with

enable
It operates as follows:
The excitation input S and R are allowed (gated) only when C is active
(’1’); otherwise S and R is forced to not active.
Outline
2 Bistable Element
Basic SR Latch
D Latches
D Flip-Flops
Master-Slave SR Flip-Flop is controlled by a pulse in place of level-controlled
method used in SR Latch.
Outline
2 Bistable Element
Basic SR Latch
D Latches
D Flip-Flops
Problem with the SR Latches with Enable:
The case of both S and R active simultaneously still is possible.
Solution: Forcing S and R to always be opposite (inverting).
The result is called D Latch or Transparency Latch

It operates as follows:
- The excitation input D are gated by the contorl signal C. As a result,
- If C is active (’1’), the output Q is the same as the input D;
(“The output Q is transparent to the input D”).
- otherwise (C is not active (’0’)), the output Q is no change.
Outline
2 Bistable Element
Basic SR Latch
D Latches
D Flip-Flops
Problem with the D Latches:
The glitches on D are also passed through the output Q during C =′ 1′ .
Solution: Applying the concept of master-slave doors to allow D to pass through only
during the small window.
The result is called D Flip-flop (D-FF)

The small window is during the edge of C, which will be referred to as the
“clock” signal, denoted by clk, instead.
We refer to this kind of control as edge-triggered control, which has two
kinds:
- Positive edge-triggered: the triggers occur during the changes of
clk from L to H (the clk’s positive edges)
- Negative edge-triggered: the triggers occur during the changes of
clk from H to L (the clk’s negative edges).
D Flip-Flops
Positive edge-triggered D-FF

Characteristic Equation: Q′ = D when triggered (the clk’s positive edges)
Negative edge-triggered D-FF

Characteristic Equation: Q′ = D when triggered (the clk’s negative edges)
D Flip-Flops with Asynchronous Controls
D-FF with active-low asynchronous reset (R) or clear (CLR) and
active-low asynchronous set (S) or preset (PR).
Function Table Characteristic Equation: Q′ = D

CLRn PRn clk D Q Qn Action
when all asynchronous controls
0 − − − 0 1 Asynchronous clear
1 0 − − 1 0 Asynchronous preset
are not acive, and triggered
1 1 0 − Qold Q̄old Remember (clk’s positve edges)
1 1 1 − Qold Q̄old Remember
1 1 ↓ − Qold Q̄old Remember
1 1 ↑ 0 0 1 Synchronous reset
1 1 ↑ 1 1 0 Synchronous set
D Type Memory Devices’ Characteristic Equation and Excitation Table
Characteristic Table Excitation Table

Inputs Outputs Action Changes Excitation Action
D Q Q′ Q→Q′ D
0 0 0 Reset 0→0 0 Reset
0 1 0 Reset 0→1 1 Set
1 0 1 Set 1→0 0 Reset
1 1 1 Set 1→1 1 Set
Characteristic Equation: Q′ = D
Outline
2 Bistable Element
Basic SR Latch
D Latches
D Flip-Flops
JK Type Memory Devices:
Two excitation inputs, denoted by J and K, that is similar to S and R,
respectively, but causing Q to toggle when J and K are active simultaneously.
Matster-Slave JK Flip-Flop
Outline
2 Bistable Element
Basic SR Latch
D Latches
D Flip-Flops
JK Type Memory Devices:
Two excitation inputs, denoted by J and K, that is similar to S and R,
respectively, but causing Q to toggle when J and K are active simultaneously.
Positive edge-triggered JK Flip-Flop
JK Type Memory Devices’ Characteristic Equation and Excitation Table
Characteristic Table Excitation Table for JK Type Memory Devices

Inputs Outputs Action Changes Excitation Action
J K Q Q′ Q→Q′ J K
0 0 0 0 Remember 0 →0 0 − Remember ’0’ or Reset
0 0 1 1 Remember 0 →1 1 − Set or Toggle
0 1 0 0 Reset 1 →0 − 1 Reset or Toggle
0 1 1 0 Reset 1 →1 − 0 Remember ’1’ or Set
1 0 0 1 Set
1 0 1 1 Set
1 1 0 1 Toggle
1 1 1 0 Toggle
Characteristic Equation: Q′ = JQ̄ + K̄Q
T Flip-Flop can be implemented by forcing a JK FF to be only in the Toggle
case, or by feeding back Qn of D-FF back to its input D.
T-FF with Enable

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Sequential Digital Systems: Memory Devices

vLSI Design for embedded Systems with intelligence (vDeSi) Lab

King Mongkut’s University of Technology Thonburi

September 16, 2016

What is the basic element for all memory devices? How to

Actually there are 3

SR Latch Characteristic Table Q′ = S + R̄Q

To Set it to ’1’, activate S and deactivate R.

Excitation Table for SR Latch Excitation Table for active-high SR Latch

It is called Controlled SR Latch or Gated SR Latch or SR Latch with

The result is called D Latch or Transparency Latch

The result is called D Flip-flop (D-FF)

Positive edge-triggered D-FF

Negative edge-triggered D-FF

Function Table Characteristic Equation: Q′ = D

Characteristic Table Excitation Table

Characteristic Table Excitation Table for JK Type Memory Devices

0 1 1 0 Reset 1 →1 − 0 Remember ’1’ or Set

Characteristic Equation: Q′ = JQ̄ + K̄Q

T-FF with Enable

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