Hardware Implementation of Real-Time Multiple
Frame Super-Resolution
Kerem Seyid, Sebastien Blanc, Yusuf Leblebici
Ecole Polytechnique Fédérale de Lausanne (EPFL) Lausanne, Switzerland
Email: {kerem.seyid, sebastien.blanc, yusuf.leblebici}@epfl.ch
Abstract—Super-resolution reconstruction is a method for
reconstructing higher resolution images from a set of low res-
olution observations. The sub-pixel differences among different
observations of the same scene allow to create higher resolution
images with better quality. In the last thirty years, many methods
for creating high resolution images have been proposed. However,
hardware implementations of such methods are limited. In this
work, highly parallel and pipelined implementation for iterative
back projection super-resolution algorithm is presented. The
proposed hardware implementation is capable of reconstructing
512x512 sized images from set of 20 lower resolution observations,
with real-time capabilities up to 25 frame per second (fps).
Explained system has been synthesized and verified via Xilinx
VC707 FPGAs. To the best of our knowledge, the system is
currently the fastest super-resolution implementation based on
FPGA.
I. I NTRODUCTION
From the early 70s on, usage of the charge-coupled devices
(CCD) and CMOS sensors are widely increased as opposed to
an exposure on photographic films. Back in 70s, these sensors
were sufficient for most of the applications. However, today
people want a digital handheld camera with high-resolution
(HR) and affordable prices. Furthermore scientists often need
a HR level close to an analog 35mm film that has no visible
artifacts when an image is magnified [1]. This creates a need
to find a way to increase the resolution level.
The most common method is to increase the pixel density,
or in other words, reducing the pixel size (spatial resolution)
by fabrication techniques. Spatial resolution refers to the pixel
density in an image and measures in pixels per unit area [2].
It is common knowledge that the scaling effects in CMOS
technology allow the semiconductor industry to make smaller
devices [3]. This rule holds for CMOS imaging applications as
well, in [3] it is indicated that CMOS image sensor technology
is lagging behind the technology nodes in ITRS roadmap.
The reason behind this lagging is very simple: current CMOS
process is not imaging friendly. Reducing the pixel sizes mean
less amount of light available per pixel. Furthermore, smaller
size generates shot noise that reduces the image quality. There
is a limit to reduce the pixel pitch without suffering the effects
of shot noise. For 35 µm CMOS process, estimated pixel area
is around 40 µm2 [1].
Another approach to enhance the resolution is to increase
the chip size. However, that leads to an increase in capacitance,
which makes it difficult to speed up a charge transfer rate
[4]. Furthermore, cost of high precision optics and image
978-1-4673-9140-5/15/$31.00 c 2015 IEEE
219
sensors are also playing an important role in commercial high
resolution imaging.
As explained, consumer applications are in need of high
resolution that can be obtained by smaller pixel sizes. Fur-
thermore current CMOS technology has the means to satisfy
the needs. However, smaller pixel size means degrading in the
performance. In order to compete with the current needs of
imaging technology, a new approach is required.
One approach is to use signal processing techniques to
obtain an HR image where multiple low-resolution images of
the same scene can be obtained. Recently, this approach has
been one of the most attractive research areas. It is called
Super-resolution (SR) image reconstruction or in another
terms, image resolution enhancement. The term SR image
reconstruction is referring to a signal processing approach that
aims to overcome the limitations imposed by obtained low
resolution images.
The major advantage of signal processing approach is that
it may cost less and the existing image systems can be utilized
[1]. After obtaining low resolution images with an inexpensive
video recorders or handheld cameras, a higher resolution
output image can be reconstructed in post processing.
Another approach related to resolution enhancement is the
single-image interpolation approach. However, since there is
no additional information and detail provided in this approach,
the quality of the single-image interpolation is very much
limited due to the ill-posed nature of the problem. The lost
frequency components cannot be recovered, therefore, image
interpolation methods are not considered as SR techniques.
In the example based SR methods, correspondences be-
tween low and high resolution image patches are learned
from a database of low and high resolution image pairs.
Corresponding patches are applied to a new low-resolution
image to recover its most likely high-resolution version [5].
Furthermore, Glasner et al. [6] proposed a patch based SR
resolution, which is database free single image super resolu-
tion. These methods are computationally expensive and real-
time implementations are not feasible.
In the SR setting, multiple low-resolution observations
are available for reconstruction, making the problem better
constrained. The nonredundant information contained in the
these LR images is typically introduced by sub-pixel shifts
between them. These subpixel shifts may occur due to un-
controlled motions between the imaging system and scene,
e.g., movements of objects, or due to controlled motions
 Desired HR Image X Kth Warped HR Image Xk
Warping
Continuous to
Continuous -Translation
Discreet Without
Scene -Rotation, Etc.
Aliasing
Figure 1. Observation model relating LR images to HR images
[2]. CCTV systems is now replacing DVRs and often they
need object magnifications, such as extracting the car plate
or focusing on the face of the suspect or region of interest
(ROI) [1]. Also, the techniques can be utilized in every aspect
of imaging technology where multiple images of same scene
can be obtained, such as Magnetic Resonance Imaging (MRI),
computed tomography (CT), satellite imaging, remote sensing
and video standard conversion.
Multiple scenes can be obtained either from one camera
with several captures that has relative motion in between
frames or from multiple cameras located in different positions
looking at same scene. After obtaining the motion estimation
with sub pixel accuracy, SR image can be reconstructed.
In this work, a real-time super-resolution algorithm capable
of creating 512 ⇥ 512 sized images from set of low resolu-
tion (LR) observations is presented. The paper is organized
as follows, theoretical background for imaging process and
previously implemented FPGA based super-resolution algo-
rithms are given in Section II. Super-resolution algorithm
implemented in this work is presented in Section III. Real-
time hardware implementation is presented in Section IV.
Implementation results is given in Section V and subsequently
discussion on real-time implementation and future work is
given in Section VI.
II. T HEORETICAL BACKGROUND
SR reconstruction has been one of the most active research
areas since its first mentioned by Tsai and Huang [7] in 1984.
In the past 30 years, numerous approaches and techniques
presented from frequency domain to spatial domain as well
as from signal processing approach to machine learning tech-
niques. In order to start talking about these techniques, one
needs to firstly understand the image observation model, which
represents the low resolution image capture process.
A. Observation Model
Image capturing process is not perfect due to the hardware
limitations. During the process, there is a natural loss of spatial
resolution caused by the optical distortions such as out of
focus, diffraction limit etc., optical blur which can be modelled
by Point Spread Function (PSF), motion blur due to limited
shutter speed, noise that occurs within the sensor or during
transmission [1]. Thus, recorded image usually suffers from
blur, noise and aliasing effects. These degradations modelled
Blur Downsampling
-Optical blur
Undersampling Kth Observed
-Motion blur
(L1 ,L2 ) LR Image yk
-Sensor PSF , Etc.
Noise
fully or partially in different SR techniques. The imaging
process is presented in Fig. 1.
Assuming X is the desired HR, sampled above the Nyquist
rate and band limited. yk is the kth subsampled, warped
and blurred LR observation of X. Furthermore, each image
is corrupted by noise, capturing process can be expressed as
yk = SbBk Wk X + nk (1)
where Wk is the warping matrix, Bk is the blur matrix and
Sb is the subsampling matrix, nk represents the noise vector.
A block diagram can be seen in Fig. 1.
The warp matrix, Wk , represents all the motion among the
captured images. It may contain global and local translation,
rotation and etc. It varies among each scene and needs to be
recalculated for each particular frame. Since the motion does
not occur in integer pixel shifts, sub-pixel calculations and
interpolations are necessary.
Bluring might be caused by the optical system, relative
motion between the imaging system and the original scene,
and Point Spread Function of the camera lens which is rep-
resented by the matrix Bk . It is assumed to be known during
the SR reconstruction, however, it is not easy to obtain this
information. The subsampling matrix SB generates aliased
images from warped and blurred HR image.
B. Related Work
Although the super-resolution reconstruction is an attrac-
tive field for over thirty years, there are not many research
conducted for hardware implementation. Bowen and Bouganis
[8] proposed a hardware architecture for FPGA implemen-
tation, however implementation needs 20 iteration stages for
satisfactory results and device capabilities were not sufficient.
Moreover, it was limited to the on-chip memory. Another
implementation for iterative back projection algorithm was
introduced in [9], which was designed for adaptive sensor and
capable of outputting 25 frame per second (fps) in VGA reso-
lution. The bottleneck of the system was explained as the triple
buffering memory access scheme. One other implementation
was presented by Szydik et al. [10]. The proposed algorithm
was a non iterative approach. However, results was limited to
QCIF to CIF super-resolution for 25 fps. Furthermore, authors
220

Figure 2. Sub-pixel shifts among the low resolution observations
stated that their implementation is not scalable and limited to
work with only two reference frames.
III. S UPER -R ESOLUTION
Super-resolution is computationally complex and ill-posed
problem. The motion between the frames, the blur kernel(s),
and the high-resolution image of interest are three interwoven
unknowns that should ideally be estimated together rather
than sequentially [11]. There are many methods proposed in
literature to solve the ill-posed SR problem where multiple
low resolution observations can be obtained. These methods
are mainly divided into two domains, either in spatial domain
or in frequency domain [1], [12], [13]. In this work, spatial
domain approaches are investigated since they are more suit-
able for hardware implementation and can be easily parallized.
Additionally, it will avoid the computational complexity of the
frequency domain approaches.
Several algorithms have been investigated for real-time
implementation. Farsiu et al. [14] proposed a fast and robust
implementation where the aim is to reduce the modelling
errors. Zomet et al. [15] proposed another method, utilizing
pixel wise median. The iterative back-projection algorithm
(IBP) proposed by Irani and Peleg [16] which aims to back
project the error between observed and simulated images.
Among these methods, IBP is suitable for hardware imple-
mentation, since it can be highly parallized and computational
complexity is suitable for real-time implementation. In the
iterative back projection algorithm, firstly an initial guess is
created by using interpolation from one of the observed low
resolution images. Afterwards the algorithm aims to find the
high resolution image X by simulating the image capture
process and creating the low resolution observations yk . The
difference between low resolution observations yk and created
low resolution observations y0 k are iteratively back projected
to the initial guess. The algorithm iteratively converges to an
HR estimate until the error between simulated LR observations
and obtained LR observations is negligable. A high quality
221
image registration is needed in order to start the super-
resolution process.
A. Image Registration
Image registration is the first and the crucial part of any
super-resolution algorithm. The registration is transforming
different sets of images to a single coordinate system. An
example of three images registered to a single coordinate
system can be seen in Fig. 2. Sub-pixel level registration
allows super-resolution algorithms to create the HR image
content. The registration methods can be divided into two,
namely intensity based and feature based methods. Among the
intensity based methods, majority of the algorithms use either
block matching based methods or optical flow to calculate
motion vectors in order to determine motion field. Optical flow
based algorithms [17] provide superior motion vector quality
over block matching based algorithms [18]. There are many
well known works focusing on sub pixel image registration
[19], [20]. Furthermore, there are works specifically focus-
ing on motion estimation and image registration for super-
resolution [21], [22].
In this work, images are assumed to be registered with
respect to reference frame using the method explained in [20].
Horizontal shifts a, vertical shifts b and rotation angle ✓ are
assumed to be known prior to starting the iterative image
super-resolution process.
B. Iterative Reconstruction
Iterative algorithms start with initial high resolution ap-
proximation such as linear interpolation of the reference low
resolution frame. For each iteration, the observation model is
explained in Fig. 1 is applied to simulate the low resolution
observation results y0 k .
The aim of the IBP is to minimize the error e in every step
(n) between simulated results y0 k and observed images set yk .
If Xn is the correct high resolution image, then the simulated
images y0 k and observed images yk should be identical to one
another.
sX X
e(n) = (yk (x, y) y0 0k (x, y))2 (2)
k x,y
In each iteration, every pixel in high resolution image X is
updated according to error of all low resolution pixels y0 k that
it affects. The difference error (yk y0 k ) is multiplied by a
factor and added to the initial high resolution estimate.
It is important to know that original high resolution fre-
quencies may not be fully restored. For example, the blurring
operation may filter out the high frequency components and
make them impossible to restore. In such cases, there are more
than one single high resolution images which result in same
low resolution images after the imaging process. It has been
stated in [16] initial guess does not influence the performance
of the algorithm, but it will influence the HR estimate that the
algorithm converges.

(a) Original Image (b) First Shearing in the x axis
(c) Shearing in the y axis (d) Second shearing in the x axis
Figure 3. Shearing based image rotation
For color images, the super-resolution algorithm is applied
in Y CbCr domain. All the images in the RGB domain
are initially converted to Y CbCr domain and the proposed
iterative back projection algorithm is applied in Y domain, and
Cb and Cr components are interpolated for HR image. Finally,
the Y CbCr components are converted to RGB domain.
IV. P ROPOSED H ARDWARE I MPLEMENTATION
As stated previously, iterative back projection algorithm is
suitable for hardware implementation. The iterative scheme
suitable for pipelining and pipelined architectures can be
implemented in parallel for each set of observed images. In
this work, a pipelined hardware is designed in order to mimic
the camera image acquisition process. The observation of low
resolution images from high resolution estimate is designed in
block based operations. Each block mimics the operation of
capture process for 2 ⇥ 2 pixels. During the simulations, it has
been realized that using block size bigger than 2 ⇥ 2 causes
significant degradation in the output image quality.
Another important aspect is to choose which portion of
estimated high resolution image should be applied to the
imaging process. The best option is to choose the whole image
and to create low resolution observation simulations. However,
this method will drastically increase the memory bandwidth of
the system. For every iteration, a new LR observation should
be created and saved in the external memory and read back
for the error calculations. Therefore, instead of saving the
simulated results in the external memory, the calculation of
the LR observations are created block by block in a pipelined
architecture, and final results obtained for HR sequence is
saved in external memory.
For calculating each yk in pipelined stage, simulations have
been conducted to find N⇥N block size such that it minimizes
222
the differences between operating in the whole image and the
2 ⇥ 2 sized pixel block. Throughout the simulations, the block
size N = 9 gives the best results in the trade-off between block
size and output image quality. For each 2 ⇥ 2 block, using a
block size 9 ⇥ 9 for image acquisition process is sufficient for
small horizontal shifts a, vertical shifts b and rotation angles
✓.
The block diagram of imaging process designed for hard-
ware implementation can be seen in Fig. 4. It can be seen
in the first part of the diagram that the capture process is
being mimicked. First of all, the warping operation between
the HR image and the LR image is being conducted. After the
HR image being shifted and rotated, it is blurred according
to the model of the camera PSF. Once the blur operation
is conducted, the final HR image is decimated by 2 in both
directions to obtain the LR image. Once the process is finished,
the warped and decimated image forms the y0 k . Once the
difference between the y0 k and yk is calculated, the back
projection of the error operation starts. The back projection is
the inverse operation of the imaging process. The error block
is back projected to HR image with inverse functions. Final
result is saved to the external memory after adding the error
to the current HR estimate of X(n).
A. Image Warping
In the image warping process, shifting and rotating oper-
ations are being conducted. Firstly, the sub-pixel shifts, that
corresponds to integer pixel shifts in HR image, is applied.
Sub-pixel shifts are calculated with half pixel precision, which
are then applied to the HR image in integer pixel level.
After the images are shifted, the rotation operation with
the angle ✓ is conducted. There are many methods proposed
for image rotation operation among which Unser et al. [23]
proposed a convolution based image rotation algorithm. The
algorithm can be applied to operating blocks with angular
motion. In [23] it has been stated that rotation can be defined
as rotation matrix

cos(✓) sin(✓)
R(✓) = (3)
sin(✓ cos(✓)
Which is also equivalent to
" # " # " #
1 tan(✓/2) 1 0 1 tan(✓/2)
⇥ ⇥ (4)
0 1 sin(✓) 1 0 1
The whole rotational translation can be decomposed to
appropriate sequence of 1-D signal translations that can all
be implemented via simple convolutions. It is a three pass
implementation of rotation that can be seen in Fig. 3. The
original image Fig. 3(a) is first sheared in x dimension Fig.
3(b) then in y dimension Fig. 3(c) and finally again in x
dimension Fig. 3(d).
The algorithm can be implemented as first shearing among
the x axis, using tan(✓/2) and current macro block position.
 HR(n) Line 1
Warp Blur Dec
HR(n) Line 9
LR Line 1
⊖
LR Line 5
Figure 4. System Architecture Block Diagram of IBP Super-Resolution
The shearing values on the edges and the corners will not be
equal to the shearing values in the center of the image. In order
to solve this problem, appropriate values for tan(✓/2) are
stored in block rams. Depending on the values of tan(✓/2)
and current position of the macro block (X, Y ), shearing oper-
ation can be calculated. Line values are delayed or forwarded
depending on the calculated shearing operation.
Afterwards, the output image can be sheared in y axis using
sin(✓). Similarly, sin(✓) values are stored in the block rams.
Utilizing (X, Y ) positions and sin(✓) values, the block is
sheared among the Y axis. Output of the y axis shearing is
extended in order for the image to be properly sheared. Finally
the macro block sheared among the x axis with tan(✓/2).
Image dimensions are carefully calculated and increased with
respect to shearing operations in the y dimensional shearing
and second x dimensional shearing. Thanks to global motion,
blocks do not coincide with each other. Final image is cropped
to fit 9 ⇥ 9 macro block. The obtained macro block is the
shifted and rotated version of the original HR macro block.
B. Blur and Decimate
After the image warping, the 9 line values coming from the
image warping block are synchronized for the image blurring
operation. The blur operation is applied to create the camera
Point Spread Function. Camera PSF function is estimated as
3 ⇥ 3 matrix and blurring operation is applied accordingly to
mimic both atmospheric and lens blur.
The output of the image filter block is subsampled in
order to create the simulated observation of y0 k . After the
subsampling process, size of the macro block is reduced to
5 ⇥ 5. The obtained block Mobt (x, y), corresponding to a
portion of the simulated observation yk , is subtracted from
the block of the observed LR Mobs (x, y) of y0 k . Results of
the subtraction Mdif f (x, y) corresponds to error function that
needs to be back projected into the initial HR image X(n).
C. Back projection
Back projection is the inverse operation of the image obser-
vation process. The imaging process applied until subtraction
block is now applied in reverse order. Firstly, Mdif f (x, y)
block is interpolated in order to obtain Mdif 0
f (x, y), the 9 ⇥ 9
block. Simulations of the SR process showed that there were
no significant difference between tested interpolation methods.
Therefore, the averaging filter is applied to Mdif f (x, y) to
obtain Mdif
f (x, y) block.
0
The upsampled block Mdif 0
f (x, y) is fed into the deblurring
filter. The deblurring filter is different than the PSF function.
223
UpSample Sharpen Warp HR(n+1)
It can be chosen arbitrarily, where the camera PSF represents
the camera blur parameters. 9 lines coming from the image
interpolation blocks are filtered in parallel in order to reduce
the noise to obtain Mdeblur
0
(x, y).
In the final stage of the pipeline, Mdeblur
0
(x, y) rotation with
angle R = ✓ is conducted. The backwards warping block
0
is the same as forward warping block, except the ✓ value
which is the negative angle of the forward warping block.
Same shearing process is applied on the deblurred block to
obtain Mwarped
0
(x, y). From Mwarped
0
(x, y) block, the middle
subset of 2 ⇥ 2 block is taken for the back projected error.
D. Parallelization
The system overview of the iterative back projection algo-
rithm is shown in Fig. 4. The process can parallel for each
image i and the same HR macro block can be used for each
operation. Finally, the calculated errors are summed with an
adder tree depending on the number of the LR observations as
seen in Fig. 5. The final added error E(n)(X,Y ) is multiplied
with a constant . The observed error is added to the current
HR estimate X(n).
E. Simulation Results
The fixed point version of the proposed algorithm is im-
plemented via MATLAB with different input image sets.
Several shifted, rotated, blurred and subsampled sets of LR
observations are created from a HR image and the HR image
taken as ground truth. With different data sets, the output of
the algorithm had an average PSNR value of 30.34 dB.
V. I MPLEMENTATION R ESULTS
The proposed iterative back projection hardware is imple-
mented using VHDL. The models are mapped to a Virtex-
IBP
IBP
E(n)(X,Y)
IBP
IBP
Figure 5. Parallelisation of iterative back projection blocks
 Table I
N UMBER OF ITERATIONS FOR DIFFERENT HR IMAGE RESOLUTIONS
HR 256 ⇥ 256 512 ⇥ 512 720 ⇥ 1280 1024 ⇥ 1024
Iterations 71 17 5 4
7 XC7VX485T FPGA. Single super-resolution module con-
sumes %0.96 of LUT and %0.98 of DFF. The FPGA utilization
scales proportionally depending on the number LR observa-
tions need to work in parallel. The proposed hardware operates
at 265 MHz after place & route. The pipelined process flow
can process 2 ⇥ 2 blocks in every Ncyc = 9 cycles. With
the operating frequency, the system can construct 512 ⇥ 512
HR resolution image with 25fps, using up to Nit = 17
iterations and does not depend on the number of images,
except the adder tree. The required number of cycles for SR
implementation can be calculated as
M N
⇥ ⇥ Nit ⇥ f ps ⇥ Ncyc + Lattree (5)
2 2
Where Lattree is corresponding to adder tree delay in the
final stage.
Number of iterations that can be conducted for different HR
image sizes can be seen in Table I. During the simulations,
most of the LR sets are converged over the minimum error
barrier in less than 10 iterations. The number of iterations as
low as 5 can produce good results with sufficient number of
LR observations.
VI. D ISCUSSION AND F UTURE W ORK
In this work, a novel hardware implementation for multiple
frame super-resolution is presented. The presented hardware is
easily scalable in terms of number of low resolution observa-
tions and final high resolution output size. The presented sys-
tem is implemented in hardware description language VHDL;
synthesized, placed and routed for Xilinx Virtex-7 FPGAs
using Vivado Synthesis Tool. The implemented hardware
operating real-time with 25 fps, and reconstructs a 512 ⇥ 512
sized HR image from 256 ⇥ 256 LR observations with 20
iterations. To the best of our knowledge, this is currently the
fastest FPGA implementation for a real-time super resolution
algorithm. Currently, an optical flow based real-time image
registration algorithm is under development in order to create
a real-time multiple image SR system.
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