G-TUO t2> INC O2 Def) 3777475 onDOLY 5 GUL : vy 21 T aS : 12/16MHz PC/AT Compatible Chip Features Description « Highly Integrated PC/AT Com- The GC101/GC102 is a fully IBM The GC101 performs CPU and patible Three Chip Set. PC/AT compatible chip set support- Peripheral support functions includ- ing the 80286 CPU at clock speeds up ing that of DMA Controllers, @ © Supports up to4MegDRAM using to 16MHz._ This highly integrated | Memory Mapper, Timers, Counters, AMBit or 256k devices. three chip solution features high per- Interrupt Controllers, Bus Con- formance, low power consumption, troller, and their supporting circuitry. Available in 16MHz and 12MHz low board space requirements, high This device is packaged in a 160 pin versions, reliability, and low cost. A fully flat pack. PCIAT compatible system may be im- « Designed in HCMOS for high plementedwiththischipset,the CPU, The GC102 may be configured as speed and ow power consumption. Keyboard Controller, RTC and 7 either an Address Buffer or Data Buf- ‘other devices plus memory, This chip fer by strapping one pin high or low. : ‘ All‘Megacells’ are full implemens _setsupports256K and1Mbit RAMs This chip replaces address buffers, tations of standard devices. in configurations up to4 megabytes at data transceivers, memory drivers, zero or one wait state, Zero wait state parity generators and supporting cir- ‘¢ Available as cores for customiza- operations is supported up to 12MHz —_cuitry. ‘This device is packaged in an tion in high volume applications. ‘4 pin PLCC, System Board Block Diagram cro2 DATA BUFFER oPu February 1988 G-2 Incorporated © 1655 McCarthy Blvd. Preliminary Milpitas, CA 95035 @ 408-943-0224wh e a 3077475 G-TWO (2) G2 INC ~ INC O2 DEB Di 3772475 oooooLs 7? Wf O2E 00065 OD =T-4q-17-01 GC101/GC102 GC101 Peripheral Controller Functional Description ‘Tet GC101 Peripheral Controlsr chip isthe bear: ofthe three chip system and forms most of th con- trol eixcuits and “glue” logic of the AT architect ip » single CMOS VLSI chip. Ir this device. at 82284 megafunction (MF) geotrates PROCCLK. IREADY and RESET signals for use by the sys- tem. MFB225§ provides all sigzals for memon. p: boards, A 9-bi refrest coun cuit to provide the row address of the memory during refrest, 2 ouiputs memory map- ping addresses. MPS284 uses 2 14.318 MHz input is used in the cir- SNe el G.2 Incorporated « 1685 MeCartby Blvd. @ Milpitas. CA 95035 @ 408.94: lock to generate an OSC video signal and bast ‘lock for the MFE2S4 timer/eounter, The timer is programmed by the CPU and provides signals for system timing, refresh, and speaker tone genera- tio. ‘Two MF8237s support Direct Memory Access. ‘transferring 8-bit and 16-bit data between memory and VO devices. Two MF8259s are configured at master/slave and receive interrupt requests from Timer, Keyboard Controller, Real Time Clock, ‘Numeric Processor and upto11 other sources. The ‘MP8259s issue a signal tothe CPU toinitiate anin- terrupt routine. For all peripherals of &-bit dats ‘width, the GC102 provides conversion circuitry from a 16-bit bus to an 8-bit bus, thus maintaining compatibility with an 8088 PC. ‘The GC101 desigo encompasses one wait state for memory operation and four wait states for 1/0 operation. The design includes the option of im- proving performance by using faster RAM. faster CPU, or by reducing the memory wait state 102210 ‘with the addition of external synchronization logic. Designers can configure memory from 256K to 4 Mostes (or more) by using RSELO, SEL and RSEL2 (see pin listing). There are also select sig- tals to establish chip and system speed. The chip cap operate at upto 12/6 MHzin the full eommer- cial temperature range.G-TW0 {2} INC O@ deff 3777475 oooooe 4 | ——— 3777475 G-TWO (2) INC O2E 00066 +F-Yq-\7-0) G 2 GC101/GC102 GC101 PIN ASSIGNMENT RA thee Sts 3s, HF see SELSESSSSSERREBBRESSSRSBRS SE EUSE EER Ea2 SS RRP ORERDRE EER SR RRESoroNsegesesessssssnskzassRs 80 vo prmon 322 89 v2 (aor las Bx fasrez> 23 BR Towuree iz : 3e mstte orrsuren 135 HEE, er a ‘74 RSELC Cronng 339 ee fy ise BEE ire 3 ‘72 XAL4 Tan 130 HE 32 69 XA12 3 68 XAll Prostate 133 SRE jaan 34 ‘ ou ({RICWR 135 $6 ms frear 36 se foaties ee feos i om 55 2 61 XAG % G2 sci ge veld oi ye ia {DACKO 143 23 jones se 3 goaces es 3 i jeacrs 186 a jase B fprexe hee 2 qace? 83 By i oreo” 80 aH Brest ie ; prez 2 brs. 183 3 presse 2 bree les 2 prey ise Et ime is BS ine ise Ea ins ibs es “ 7 Menenonanynerens i g. gece i EE gb Sikes weees ! SBoegeSeseeseeSSSesigaue SEERRESEC GREER ECE BEEREE November 1967 G-2 Incorporated # 1655 McCarthy Bivd. « Milpitas, CA 95035 « 408-963-022G-Two t2 INC Oe DE a777475 GooooK7 o Due scor G2 GC101/GC102 GC101 Peripheral Controller Chip Block Diagram Con re Ls anas Lane November 1987 G-2 Incorporated « 1655 McCarthy Blvd. # Milpitas, CA 95035 » 408-943-022G2 G-TUO 2} INC D2 DEM} az77475 cooooLs 2 & TH4q4-(1-01) GC101/GC102 GC101 Peripheral Controller - Pin Description Pin Pio Mio Pull Symbol ‘Type = Numbers UpDn Description Ana (TTL) —_78,7978890 PU 0,1 are the address inputs from the CPU. AO generates SAO, ‘Aland M/1O, $0, and $1 generate the CPU shutdown operation. AlT23 ICTTL) 104-110/116-122 PU 17-23 are the input address lines from the CPU. These signals are OB) tuted to decode the memory selection logic and can be output address Hines of the memory mapper 7ALS612. AEN om) = ens7 DMA address eoable signal. Whea High, AEN indicates that the DMA. controller has control of the address, data, and read/write coatrol buses. BALE ows) 8597 Buffered Address Latch Enable signals the 1/0 slots that the preset address is valid. SAO-19 is latched with the falling edge of BALE. BALE is forced High during DMA cycles. BHE IqrTL) 8698 PU__Bus High Enable signal. BHE is active Low and is used to enable the. High Byte of the data bus. pBUsY ICTTL) 122/138 PU_This input (active Low) should be connected to the BUSY output of. the 80287, rusyes 082), 13851 ‘Thisis an active Low output that indicates the numeric processor 80287 is in operation mode. This pin is tied to busy input of the CPU. cLK2 1am.) 8294 PU Thisis the clock input and must be twice the desired processor clock frequency. CNTLOFF = 0(B2)_— 4/106, Control Off signal. When High, CNTLOFF enables the low byte data latch during &-bit data trans CPUHLDA I(TTL) —119132,_— PU_CPUHold Acknowledge is the granting signal from the CPU to relin~. . ‘quish control ofthe system. CPUHRO = 082) 2745 CPU Hold Request to the CPU for DMA and Refresh operation, ac- tive High. ress042 02) 138/156 (Chip Select 8042 signal. When Low, /CS8042 selects the keyboard con- twoller. MDACKO3 (82) 143-46/161-64 DMA Acknowledge signals. These signals are active Low and are used IDACKS-7 147-49 7165-67 to acknowledge DMA requests (DROO-7) Pin Symbol preceded by are active low Pin Type I= pet = Ourpu; (TTL) = TTL level buffer, (CMOS) = CMOS level buffer. Pin Numbers 10, the lel of are fr 160 pin at pick Number tothe right ar forthe 190 pin PGA. PU Pull Up: PD = Pull Down. November 1987 G-2 Incorporated @ 1655 McCarthy Blvd. ¢ Milpitas, CA. 95035 « 408-943-022.G2 G-Tuo te} INC U2 DEM} a7z7475 oooOLT 4 BF yg 17-0, GC101/GC102 GC101 Peripheral Controller - Pin Description Pin Pio Min Pal Symbol ‘Type = Nambers UpDo Description [MAAEN 082) STS ‘DMA Adéreas Enable signal, /DMAAEN is active Low when sD MA. ‘access is in operation. DROS ICTTL) 150537168-71 PD DMA Requests signals These sctive High signals are wsod to reques! DROS? 154561724 DMA services or cootrol of the system. Each signal should be beld ‘High until the corresponding DACK signal goes Active. DROO-3 will perform 8-bit DMA transfer. DRO4-7 will performl6-bit DMA trans. fer. DIR o(e2)sn27 Data Transmit/Receive signal. When High, DT/R indicetes dats flow from CPU to SDO-15 bus; when Low, DT/R indicates data flow in the (ERROR ——«CTTL).-~—=«21/136.-—-PU_Thissignalis active Lowwhen 80287 bas an unmasked error condition: HISPEED —-ICTTL)-—=«129/140.—= PU. When HISPEED is active (high), the processor clock will run at half the CLK*2 clock. Otherwise the processor clock will ran at one fourth CLK*2, Bus VO speed is handled separately. INTR oe2) ones INTerrupt Request from the master Interrupt Coatroller INT output, is active High. AOCHCK TTL) 1194 PU. CHannel Check. This signal is active low and indicates an error ‘condition from an I/O device. The error coodition will interrupt the CPU when enabled throug NMI (Noo-Maskable Interrupt) output, JOCRDY =—-ITTL) 10713 —-PD_‘O Channel Ready signal, JOCHRDY is held Low by the VO or ‘memory devices o lengthen the cycles by an integral number of elock cycles. This sigoal should not be held Low for more than 2.5 ‘microseconds or memory data can be lost due to inadequate refresh, nocsi6 = ACTTL) 136 PU_‘ U0 Chip Select 16 signals the CPU that the data transfer is a 16-bit, ‘one-wait state VO cycle. This signal should be driven by open collec: tor or Sate driver. AOR ICTTL) —«3185_—~PU_/0 Read signal from 82288 to read from peripheral devices, active O(B4) Low. now ICTTL) —«32_—PU__1/0 Write signal from 82288 to write to peripheral devices, active Low. oes) ‘TTL input Butter, Pi Symbol preceded by are acts low. Pin Type I= Input: O= Output (TTL) TTL keve! buer, (CMOS) = CMOS lw! buffer. Pin Number ie the eftof November 1987 for M6 pin ha pack Numbers 10 ghtare G-2 Incorporated « 1655 MeCartby Biv 180 pin PGA. PUs Pull Up: PD Pull Down 4 Milpitas, CA 95085 « 408-943-022¢G2 ~6-TH0 {2} INC O2 DEB 3777475 ooooo70 o r4aciq-ol MAT GC101/GC102 GC101 Peripheral Controller - Pin Description Description Pin Pin Pin Pull Symbol Type = Numbers Up/Do IOHALFSP (TTL) = ana2_ PU. IRQ35 ACTTL) 157-159176-178 PD TRO? QTL) 1-224 TRQS-12 IQTL) = 477-10 TRQI415 (TTL) 8-9/11-12 ARQS 1qTTL) 36 PU ALSBEN 2) 1224 (LCSROM —O(BA). 2n7 MASTER (TTL) ms PU MAO ATL) 8199 PU MEDIR 2) nas MMDPCKN (TTL) 1830S PU MDPCKE = 0(B2)_—17/129 IMEMCS16—I(TTL) unt PU IMEMR ICTTL) 2882 PU O(Bs) ‘This signal cootrols the frequency of SYSCLK. Whea this signal is high and HISPEED is high, VO will run at half the epu dock. When HISPEED is low, U/O runs atthe opu clock speed. When IOHALFSP {is low,U/O will run at the same speed as the cpu clock regardless of the ute of HISPEED. ‘These are active High signals that interrupt the CPU. This signal is connected to the realtime clock interrupt output. ‘Least Significant Byte Enable signal, When Low, /LSBEN enables low- byte data Latch Chip Select ROM signal, which selects the ROM address space (00000-OFFFFF and FEQ00-FFFFFF. IMASTER is an active Low signal and is used with the DRQ and DACK lines to gain control of the system. Upon receiving DACK, an VO processor can pull /MASTER Low to gain control of the sysiem address, data, and control buses. Memory VO signal. When High, M/1O indicates a memory cycle; when Low, MII indicates an LO cycle. Memory Buffer Direction Signal. Whea MBDIR is High, data flows from MDO-15 to SD0-15; when MBDIR is Low, the data flows in the ‘opposite direction. Memory Data Parity Check signal. When Low, /MDPCKN indicates ‘memory failure on parity test. Memory Data Parity Check Enable Signal. Whea High, MDPCKE selects parity checking logic. ‘Memory Chip Select 16 signals the CPU that the data transfer is a 16- Dit, one-wait state UO cycle. This signal should be driven by open col- lector or trisate driver. ‘Memory Read signal. /MEMR is active Low during memory read and is 3-stated when CPUHLDA is High. Pim Symbols preceded by ae active low Pia Type I= Input; O= Out (TTL) = TTL teve! butler: (CMOS) = CMOS tev! butter. Pin Numbers 0 ‘he lef of are fr 160 pin a pack, Numbers tothe righ are forthe 180 pin PGA. PU Pull Up; PD = Pll Dows. eee November 1987 G-2 Incorporated # 1655 McCarthy Blvd. @ Milpitas, CA 95035 « 408-943-0224G-Tu0 {2} INC B2 DEB az7747s Oooog7L 2 ie 4a-t ~Ya-ti-o1 GC101/GC102 GC101 Peripheral Controller - Pin Description Pin Pio Pio Pull Symbol Type Nombers Up/Da Description TMEMWACTTL) 2933. PU Memory Write signal. MEMW is active Low during memory write an ons) is tristated whea CPUHLDA is High. IMSBEN —O(B2),— 138705 Most Significant Byte Enable signal When Low, (MSBEN enables bigh-byte data. NMI 0@2 ne Non-Maskable laterrupt signal. NMI is an active High signal that for- ces the CPU to execute the interrupt routine under any eneditions. INPCS om = Bins ‘Numeric Processor Chip Select signal. NPCS is an active Low signa! that tes tothe NPS1 pin of 80287. osc ors) ans ‘Oscillator isthe 14.3818 MHZ color burs signal and is pot synchronous with the SYSCLOCK. OPTBUFUL ICTTL) 135/43 PD. Output Buffer Full signal from keyboard controller P24. This gna s connected to IRQ1, which interrupts the CPU when the keyboard bufl- ris full [POWERGOOD (CMOS) 25729 -—=«-PD__Thissignal, when Low, resets the controler. Schmitt Trigger Input. PROCCLK (BS) s708 Processor Clock isthe output signal that ties to the clock input of the CPU and the sumerie processor. RAMORAS —_0(B2) 3387 ‘This signal selects RAM bank 0 RAS control, RAMIRAS —O(B2) 3438 “This signal selects RAM bank 1 RAS control. RAMOCAS (62) 3539 ‘This signal isthe same as RAMORAS except during refresb. RAMICAS (82) 36140 ‘This signal isthe same as RAMIRAS except during refresh. RC HCTTL) 1267144 PU_Reset CPU signal This isan active Low signal from keyboard control- ler P21 and causes CPU shutdown. READY —O(B2)—— 128/146 IREADY isan active Low signal that indicates to the CPU that the cur- rent bus eycle is near completion. [REFRESH (TTL) 3720 __NO__Refresh indicates the current cycle is for memory refresh and can be (Bs) deiven Low by devices on the VO channel. Open Drain Outputs. Pin Symbols preceded by el of 7 are for 60 pin are acne iow: Pin Type l= InputO = Output: (TTL) =‘TTL bevel butler, (CMOS)= CMOS lve! beer Pin Numbers 1¢ jpck Numbers tothe right are forthe 180 pin PGA. PUs Pull Up: PD = Pull Down November 1967 G-2 Incorporated « 1655 MeCarthy Blvd. # Milpitas, CA 95035 ¢ 408-943-022«G-Tuo {2} INC G2 GC101/GC102 GC101 Peripheral Controller - Pin Description ‘ Pia Pio Pio Pull ‘ Symbol ‘Type Numbers Up/Da Description re : PRESET ows) 72N5 —-—-NO_ This signal is active Low and is weed to reset systom logic at power-up + low-line voltage ootage. Open Drala Outputs, RESETCPU 0(B2) 116/128 ‘This isan active High signal that resets 80286 CPU daring powerup, Ieyboard reset, and during a hak suas. RESET27 «© O(B2), 13280 ‘Reset 80257 is an active High signa that resets 80287 eo-procestor. RSEL2 OCTTL) «76/84. PU_-RAM Select 2 signal. When High, RSEL2 selects 1MBIT DRAM; ‘when Low, RSEL2 selects 256K -bit RAM. RSELLO = CTTL)—_75,74/83,82 RSEL21,0 as follows: 000 selects 0-256K 00 selects 0-522K 010 selects 0-640K (0123 selects 0-640K, 1M-1.304M 10 Oseleets 0-512 - 101 selects 0-640K 110 selects O-640K, 1M-2.384M 111 selects 0-640K, IM-4384M RTCAS 02) 6s Real Time Clock Address Strobe signal. When Low, RTCAS latches the RAM address for Read/Write operations. MRTCRD = O(B2). HISD. Real Time Clock Read signal. Whea Low, /RTCRD data is read from the RTC MICWR = O(B2) SASS Real Time Clock WRite signal. Wheo Low/RTCWR datas written to the RTC. Ao I(TTLYO(BS) 3054 PU.‘ VOSlot Address bus 0. This signal enables the low byte SDO-7, sDo1s ICTTL) _37-54/41-62-PU_V/O Slot Data bus bits 0-15. These support 8/16 bit data transfer from O06) WO slots to CPU. BMEMR = O(B4) 260 ‘System MEMory Read, which is the buffered version of /MEMR, ac- tive Low. 3-State Output Buffer SMEMW ——O(B4) 27A1 System MEMory Write, which isthe buffered version of (MMW, ac- tive Low. State Output Buffer 150/81 ICTTL) 3.849596 Status 0,1 signals are used to convey the current CPU status 10 the 80288 bus controller ‘Pin Symbols preceded by ‘Fare active low. Pn Type I= Input: O = Output: (TTL) = TTL lee! buffer (CMOS) = CMOS love! buffer. Pia Numbers to ‘the fel fF are for 16 pin fat pack, Number othe righ ar forthe 180 pn PGA. PU» Pull Up: PD = Pull Dow. TS November 1967 G-2 Incorporated « 1655 McCarthy Blvd. © Milpitas, CA. 95035 # 408-943-022¢GTO fe INC D2 DEB] 3777475 coono73 y | —— 3777475 G-TWO (2) INC O8E 00073 “=P. 4-\7 0) G2 GC101/GC102 Seen GC101 Peripheral Controller - Pin Description Pin Pin Pin Pull Symbol Type Numbers. Up/Du_Descrtption SPKR ‘OfB4) m8 ‘Output of the Timer 8254 Channel 2. SYSCLK OBA) 172 ‘System Clock is synchronous with the CPU clock. See Table 1. Te oe) azo ‘Terminal Coust signal. T/C will pule whea the DMA channel terminal count is reached. xA0 ICTTL) —$8/63.-— PU External Address Ois the signa! that enables the Low byte of the data os) bis. XAL9 ——I(TTL)/O(B4) 56-66/64.74 PU Emernal Address 1-16 are the external address lines that tic to XAI016 —I(TTL)/O(B4) 67-73/75-81 EPROM, keyboard, the sumerie processor, ete. XA10-16 are 3-State Buffers. XBHE ICTTL) —«-7/86.-—=—SPU_ External Bus High Enable signal activates the High byte of the data ‘O(B4) bus. xD07 ICTTL) _ 89.96/101-108 PU External data bus bits 0-7. These support only 8-bit data transfers from ‘O(B4) external devices such as clock chip, serial port etc, to CPU. (XDEVEN (TTL) = 8193. PU_ External Device Enable signal. ‘MDEVEN is an active Low signal that gates external devices to the SD bus. IXMEMW =—-/O(B4)_—99/111. PU When /DMAAEN is not active, external memory and external /O PAMEMR = /O(B4).——(98/110 ‘commands follow M/IO commands. When DMAAEN is active, exter- row vores) — 103115 tal M/IO commands have control ofthe operations. PXIOR vows) — 924 ‘TTL Input Buffers xt (CMOS) . 1629 NO_Xland X2are inputs tied to a 14.31818 MHz crystal to create OSC out- x 1(B64) 3518 ut. ows ICTL) —asit00 ‘Zero Wait State isan active Low signa] that cues the CPU to complete the preseat memory or VO data tansfer without inserting additional ‘wail states, This signal should be driven by open collector or 3-state driver. Pin Symbols preceded by are active low. Pin Type I= Input: O= Output; (TTL) = TTL tev! buffer, (CMOS) = CMOS level buller. Pia Numbers to ‘the left of are for 160 pin at pack, Numbers 10 the sight ae forthe 180 pin PGA. PU Pll Up: PD = Pull Down. November 1987 G-2 Incorporated « 1685 McCarthy Blvd. @ Milpitas, CA. 95035 « 408-943-0224G-Tuo {2} INC G2 def) 3777475 oonon7y 6 A 4a: 7-01 2 GC101/GC102 GC102 Data Buffer Chip fare connected to pias MDPOUTD and MDPOUT! ‘The GC102 Data Buffer chip buffers dats for the as the aintb input o the -bit parity erro detect CPL, the Expansion bus and the Memory data ‘ircults, The other eight puts come from the ‘bus. Two sigoals control data flow direction. The Memory data bus. DTMR signal controls data flow between the CPU the Expansion data bus. The ‘When the output sigal MDPCKN s enabled an: al controls data flow berween the an error is detected oe either byte O or byte Lof Expansion bus and the Memory data bus, the Memory data bus, MDPCKN will be active ee a el wpe 10a § ony 6am 4 pu 2 ou M bn 2 oF 80 over v4 you ccm eT BM bmn cme mn so 72 aoe 71 70 ao ne mer es GC102 Data Buffer Chip Pin Assignment as we sams @ sence 61 wore 0 worse $9 me 51 mo wwe s sou $5 sas $4 sve 32 vis 360 3H ap: a0 400 42 gos 8 amy 46 vas Ab 404 $0 202 rites st at ieee eo ert) Clocked by the CNTLOFF signal. latching is ow), During memory write eyeles, parity bits for provided for data between the E byte O and byte 1 are generated through on- the CPU bus board parity generator circuitry and then eutput through the MDPINO and MDPINI pins and ‘written to RAM, (Pin 73 = VSS) logic cir During memory read cycles, the fur byte 0 and byte I from the RAMS G-2 Incorporated # 1655 MeCarthy Blvd. © Milpitas, CA 95035 » 408-943-0224 ¢G-Tuo {2} INC U2 de} 3777475 oooDO7S o Feg--01 G2 Gc101/ci02 LN GC102 Data Buffer Chip Block Diagram i prow: | | | i i \ | ; | \ : I te i | Ua 1 | Lem i el : | 4 seas asst) ——t se NDPEKEN Des ss November 1987 G-2 Incorporated « 1655 MeCarthy Blvd. « Milpitas, CA 95035 408-943-0224 Ja‘13. -Two {2} INC 02 DEB} az7747s5 coooo% 2 fF T=W9-17-01 GC101/GC102 GC102 Data Buffer - Pin Description Pin Pio Pin Poll ‘Symbol ‘Type ‘Numbers Up/Dn Description OfB12) 9 ‘Address bit 20 of the CPU conditioned by AZ0GATE signal. 3-State ‘Output Buffer. (A20G ACTTL) 6 ‘With a High 00 A20Gate and Low oo CPUHLDA, A20 is the same sate as that geoerated from the CPU. A Low on A20GATE and Low 00 CPUHLDA results in A20 being Low. (CNTLOFF ATTL) 7 An active High input to enable the low-byte data bus latch. (CPUA2 A(TTL) nn Address bit 20 from CPU. ‘This signal is conditioned by the A20GATE ‘signal. CPUHLDA = I(TTL) “ (CPU Hold Acknowledge signal. When High, the address bit 20 (A20GATE) is stated. When CPUHLDA is Low, A20 is the same ‘as the CPUA20 conditioned by A20GATE. ‘DO-DS VO(B6) 65-70 PU Bidrectional Data Bus signals to and from the CPU. Dée-Di2 8-84 DiI-DS 13, DTR \(TTL) % ‘Date TransmivReceive signal. Indicates the direction of data flow be- ‘tween the D and SD buses, Whes DT/R is HIGH, data flows from D toSD. When DTM is LOW data flows from SD to D. ALSBEN (TTL) R “Active Low to enable low-byte data transfer between D and SD buscs. MBDIR A(TTL) n MD/SD bus directional contro! signal. When MBDIR is High, datz flows from MD bus to SD bus; When MBDIR is Low, flows from SD bus to MD bus : MDO-MD3 VO(B6) 32-29 PU On board memory data bus. MD&MDS —/O(B6) 26-25 MD6-MD14 —‘1/0(B6) 23 MDIS UVO(BS) 8 MDPCKE A(TTL) 15 ‘Memory Data Parity ChecK Enable signal. ‘Wheo High, MDPCKE enables the parity checking during memory read. TTL Input Buffer IMDPCKX O86) a PU Memory Data Parity Check signal. Active Low to indicate « parity error during memory read. MDPINO O(B6) 59,60 PU Memory data low and bigh parity bits. As generated, these signals arc MDPIN1 ‘written into the RAMs during RAM write cycles. Pan Symbol preceded "Fare asine low. Pin Type I Input: O= Output: (TTL)=*TTL evel butler, (CMOS)= CMOS ove butler, PUs Pull Ur PD Pull Dow. November 1987 G-2 Incorporated # 1655 MeCatthy Blvd. @ Milpitas, CA 95035 » 408-943-022¢G-Two {2} INC G2 de) 3777475 oOOD077 3 T4419-0 G2 GC101/GC102 GC102 Data Buffer - Pin Description Pin Fin Pio Pull Symbol Type Numbers UpDn Description MDPOUTO (TTL) 45 ‘Memory Data Low and High parity bit signals. These signals read data MDPOUTL from the RAMS to generate parity check during read cycles. MMSBEX = KCTTL) a PU Active High to enable High-byte data transfer between D and SD ‘buses. TTL Input Buffer. vss 102335,473,73 GROUND vop 11,22,37,64 POWER: +5 Volt Supply 12,24, 27-28 NOT CONNECTED . 33-34, 36,48 NOT CONNECTED VO(BS) 35-46 © PU Expansion data bus, which makes possible data transfer betwees the 4955 Dand MD buses. xA0 1qTL) 2 Local 1/0 bus address bit . This input enables the date transfer be- tween the low byte of the SD and MD buses. XBHE ATL) 58 Local 1/O Bus High Enable signal. This signal enables the data trans- fer berween the high byte of the SD and MD buses. IXMEMR (TTL) 56 Memory Read signal. Thisinput enables the parity circuit duringRAM read operations. Fin Symbols preceded by‘ ae ace low. Pun Type I= Input. O= Output: (TTL) = TTL lel buller (CMOS) = CMOS level bulls. PU= Pull Up PDe Pull Down A November 1f G.2 Incorporated # 1655 McCarthy Blvd. Milpitas, CA 95035 408-543-0224 aeG2 G-Tuo {2} INC D2 DEB}a777475 oooo07 s FP yq-1y-0) GC101/GC102 GC102 Address Buffer Chip ‘The GC102 Address Buffer chip provides address ‘buffers for the Expansion bus, the Local VO bus ‘and the system board DRAMS. Early ALE is included to atch the address from the CPU. The IDMAAEN sigea! controls the adéress flow direction between the Expansion bus and Local VO bus. The CPUHLDA signal controls the direction of address flow from the CPU to the Expansion bus. By multiplexing the address bits of the Expansion bus (via ADRSEL and /RE- FRESH), the Memory address bes (MARS), ‘which drives the system board DRAMS, is geaer- ‘ted. Tes bits of address allow for elther 256K or Mbit DRAMs. (Pia 73 = VDD) ie ees Bee ka as ata Baus Vea tsa Next 1x: thee wx pew new row sows Sie see HEE ELL noe 9 8 1 8 November 1967 15 . pus 1Onu9 8 ae 6 ait 4 ase 2 ae Mast 2D ase Oa ame 76 aoe, “6 GC102 Address Buffer Chip Pin Assignment as 30 vas 36 vOD3b 44s 40 ne <2 aas Od nad 46 vs A a en) “a Be mem won omen 2 pane 71 “7 ue we ao a as wou wo wa @ sas 61 sae @ sat 8 sarasn St 00 57 oo 6 ta 85 as $e mop tah aad $0 sans? wane os 9 o Got Incorporated 0 1655 McCarthy Blvd, # Milpitas, CA. 95035 « 408-943-072G-TWo f2} INC G2 DE}3777475 oooo7s 7 T-49-17-01 G 2 GC101/GC102 GC102 Address Buffer Chip Block Diagram sx 4 asd Lae ate November 198 G-2 Incorporated e 1655 McCarty Blvd. « Milpitas, CA 95035 © 408.943-022¢G-Tuo {2} INC D2 Def) 3777475 qoooosa a 3777475 6 G-TWO (2) INC 02E 00080 = O-T-4q-(7-0} G 2 GC101/GC102 GC102 Address Buffer - Pin Description Pio Pin Ps Pull ‘Symbol ‘Type Nombers Up/Do Description (AL-AG (TTL) 6-70 PU Address inpat signals from CPU. These are latched whan both /S0 and ATAR 1m) Be Bi are High. AIGAIS ATTL) 13, (AIT-A20 A(TTL) 47 ADRSEL (TTL) 5 Address Select signal. ADRSEL costrols the geacration of the RAS and CAS addrresses 0c the MA bus for addressing the system RAMs. AEN 1(86) 6 PU Address Enable signal This pio conveys the A17-A19 signals directly into SA17-SA19, respectively. BHE ACTTL) 4 ‘Bus High Enable signal. Transmitted from the CPU, BHE indicates data transfer oa the most significant byte of the bus. CPUHLDA = (TTL) Rn CPU Hold Acknowledge signal. When CPUHLDA is Low, the ad- dress latches drive the SA bus. DMAAEN (TTL) n DMA Address ENable signal. DMAAEN controls the direction of data wransfer berween SA and XA buses. When DMAAEN is High, data flows from SA to XA. MAO O(B12) Address signals for addressing system RAMs; MAL (B12) MAS is for IMB DRAMS. MA3-MA2 O(B12) ‘3-State Output Buffers MAS-MAS O(B12) MAG O(Bi2) mu MA8-MA7 O(B12) 1132 MAS O(B12) 9 PREFRESH = (TTL) $8 Refresh active LOW signal. This signal selects SAO as MA6 during refresh. SAO \(TTL) 7 Address bit 0 signal. SAO is used during refresh. Bidirectional signals SA1-SA9 VO(Bs) B46 for the expansion bus. SAI0-SA16 — VO(B6) 49-55 SAIT-SAI9 —-UO(B6) ‘$9.61 SBHE (Bs) a PU Bus High Enable signal for the expansion bus. This signal is the outpu of the BHE latch. Bs) ir.) % CPU Status output signals. ‘61 and /S0 generate the clock signals for 80 (TTL) nn the address latches in this chip. VSS 10, 23, 35, 47, 63 GROUND in Symbols pressed by PD= Pull Devs. are acive low. Pin Type I= Input; O= Output; (TTL) TTL teva buffer, (CMOS)= CMOS level buffer, PUs Pull Up TS November 1987 72 G-2 Incorporated « 1655 McCarthy Blvd. # Milpitas, CA 95035 » 406-943-022G-TwO {2} INC O2 De 2277075 coon, 5 aT AA -l7o1 G2 GC101/GC102 GC102 Address Buffer - Pin Description Pip rio Pin Pall Symbol ‘Type Numbers. Up/Dn Description op 22,37,64,73 POWER: +5 Volt Supply XALXAG — VOLES) 32-29 PU_ Peripheral address signals for the local bus XASXAS —-UOKBE) 26-25 XATXAIS — VO(B6) 213 XAI6 vO(B6) 8 Fa trmbou presen 7 ae a lo: Pn Type T= Inu: O» Oupt (TTL) TT tev butler (CMOS) = CMOS ra bates, PU Pal Up rosrabos November 1987 G-2 Incorporated © 1655 MeCarthy Blvd. # Milpitas, CA 95035 0 408-943-022: Le6-Two {2} INC D2 DE) 3777475 oooNBe 7 i= ya-it-0y : G2 GC101/GC102 GC102 Address Buffer Chip -- AC Characteristics Tyeica, WCCOM Tyne. WCCOM Inver Ovurect = (ns) (ns) Ir Ourevr (ns) (as) anya any SA 995 186 any XA anyMA oo 2 BHE SBHE 8.76 16.4 DMAAEN = any XA 1192, 2m S0or SI any SA M77 22.0 DMAAEN = any SA 10.49 a CPUHLDA “any SA 10.58 212 REFRESH = MA ‘$05 iT CPUHLDA SBHE 8.46 138 ADRSEL MA 629 Ss MAS 90 16 xEN Sait, 10.78 — — a anya MA 10.22 wa any SA any XA M9 MAS 11.50 21s any xa wy SA ED any SA (SAO) FopNA PSASAD) Sh El November 1987 G-2 Incorporated # 1655 McCarthy Blvd. # Milpitas, CA 95035 0 406-943-0224 17Tuo {2} INC O2 “DEW azz 7475 oooo08a § fF 40-40) G2 GC101/GC102 GC 101 / GC102 Chip Set - DC Characteristics Specified at VDD = SV +/-5% over the commercial temperarure range (0-70C). Sombo) = Barameter ‘Condition Min Max nits vo ‘Voltage Input LOW - TTL Inputs 03 v vin ‘Voltage Input HIGH -TTL Inputs 20 v TN Input Currest, TTL, CMOS Inputs Vad or Vis 10 » uA Inputs with Pull Down Resistors = Vin= Vdd 10 | A Inputs with Pull Up Resistors Vine Vis 100 8 3A 1D ‘Quiescent Supply Current Vin = Ve or Vis 4 ma LY November 1987 G-2 Incorporated » 1655 McCarthy’ Blvd, @ Milpitas, CA 95035 « 408-943-022 ao2/ G2 G-Tuo {2} INC O2 def) 3777475 ooooa4 o Mf +.4q-17-0) Application Note GC101/102 Configuration Options [AT compatible systems implemented using the G2 AT chipset (Models GC101 and GC102) offer several different con- figuration options. Those options involve the processor clock speed, options to slow down the ex pansion board compatibility, and options for suppor of 286k or IMbit DRAMS. This paper ela insion bus to insure ex rates on those options HISPEED ‘This option allows the user to change the CPU speed dynamically either from a switch mounted on the front panel orif supported by the keyboard controller firmware, through the system keyboard. In a 16 MHz system, the os- «illator for the CPU wall normally be 32 MHz. The output ‘of the oscillator is buffered by the peripheral controller and then feed to the CLK input of the 80286 CPU, When the HISPEED input of the controller chip is low, the 32 MHz clock is divided by two before feeding to the CLK input of the CPU, Internal circuitry will ensure the synchronization ofthe change-over of frequency to the CPU and will not af- fectthe operation of the software that is running on the sys- tem. IOHALFSP This signal allows the use of lower speed peripheral cards tobe used in the higher speed G2 system. When this option is selected (IOHALHSP =1 and HISPEED = 1), The sig- nal SYSCLK at the expansion bus will change frequency depending on the instruction being executed by the CPU. Ina 16 MHz system, the SYSCLK signal will normally run at 16 MHz, when the controller detects that an 1/ instruc- tion is being executed, the SYSCLK frequency will be divided by two. The peripheral card will operate asif the system is running at half the CPU speed or 8 MHz. Note that the slow down of the SYSCLK only occurs at 1/0 in- s. SYSCLK will continue to run at full speed instruction fetch, memory read write and CPU in- ternal operation aslong asit is accessing the on board RAM as set by DIP switches SELO.SEL1 and SEL2, For 2 12 MHzsystem, the /O hall speed option willforce 1/0 opera- tion to the expansion slots to an equavalent speed of 6 MHz. during the reading or writing to 1O ports on these expan- sionboards. The video memory or system memory on the: boards can operate at one wait state if the MEMCS16 si nal at the expansion i slot is pulled low. Or, if the OWS si nal is pulled low, expansion memory can operate at zero wait states. In the case of a line printer operating at 200 CPS with a parallel interface, five milli seconds are available for the system to test if the printer is ready for another character and to send the character, This is suiciet time forthe sys- temo respond, In bh case of ouer peripherals he ae usually ony a few registers that are accessed wsing structions and they usually written to ‘one time. The lowering of the SYSCLK to balf of the ‘speed will al- lows slower devices to be used on the system and have only ‘avery minor impact on system throughput, Also note that JOHALFSP input is only valid when HISPEED is at a 1. ‘When HISPEED is at logic 0, the system is running at half speed and IOHALHSP input will have no effect on the sys- tem. RSEL2 This input selects the type of DRAM to be used in the sys- tem, When RSEL2is high, 1M-bit DRAMs can be used on the system, When RSEL2 is low, 256K-bit DRAM must be used. RSEL1,0 ‘These two signals control the address mappi tem board. For systems using 256K DRAM, is.as follows: RSEL 1 0 0 osm 0 1 O512K ne 0 oom 1 1 O-640K, 1M-1.384M For system with 1M-byte of memory, connecting RSEL 0 and 1 to logic high will map the first 640K of memory to ad- dress 0 10 640K of the system. The remaining 384K will be ‘mapped to the memory space 1M to 1.384M. This frees up the memory location from 640K to 1M for system use. For system using 1 M-bit DRAM: RSEL 10 o 0 0-512K o 4 0-640K 1 0 (0-640K, 1M -2.384M 1 1 (0-640K, 1M - 4:384M February 1988 G-2 Incorporated © 1655 McCarthy Blvd. © Milpitas, CA 95035 @ 408-943-0224a2 6-TW0 {2} INC 02° deff a777475 ooouss 2 I 4 o-(4-0) Application Note 4 Memory Expansion / IRQ Lines / Delay Line —_—— SS AT compatible system boards designed with the GC101/102 according to schematics Published: prior to M: rch 16, 1988 will require require several modifications to ensure the highest degree of com- lity with OS/2, common exp: sion boards, and delay lines used in manufacturing. Running OS/2 on the G2 System Board In order to guarantee compatibility with IBM OS/2 on boards designed or to mid March 1968, it will be necessary to make a minor change to one ofthe PAL equations (US1) and add swo jumpers: US1 pin 17 to JC pin 1 (SBHE), and US1 pin 16 to U49 11 (XBHE). The diagram below shows these modifications to sheet 9 of the 286 motherboard schematic dated before March 16 1988. . Modification to Delay Line Circuit In order to render superior tolerance to the wide range of delay line specifications available from leading suppliers, it is necessary to add a single gate to the circuit between the delay line (U48) and JP6. This change is also reflected in the diagram below. To XBHE IRQ Pullup Resistors. Allevaluation board implementations of G2's GC101/102 designed by G2 prior to March 1988 lack- ed pullup resistors on all /O channel IRQ lines (specifically IRQ3,4,5,6,7,9,10,11,12,14 and 15). A pullup resistor to +SV with a value of 10k ohms should be added to each of these lines. This was the cause of several minor incompatibility problems with some expansion boards. es March 16, 1988, G-2 Incorporated @ 1655 McCarthy Bivd. @ Milpitas, CA 95035 © 408-943-0224G-Two <2} INC D2 DEP arz7475 cooooaL 4» FP = 4qQ-i1-9) : GC101/GC102 % Timing Diagrams ——— Key to Timing D GC101 TIMING TEST MIN MAX COND 1_PROCCLK DELAY 2ins 85pf 2_PROCCLK PERIOD Sins 85ph 3_SYSCLK Ons 85pf 4 $0,$1 SETUP TIME Ins 85ph ‘5_$0,$1 HOLD TIME Ons 85pf 6 BALE DELAY Ons S0pf 7_[MEMR DELAY Ons 85pf 8 _/MEMW DELAY 10ns 85pf 9 _DT/R DELAY ‘ns 25pf 10 [OR DELAY T7ns 85ph 11_AOW DELAY Tas 85ph 12_/MEMCS16 SETUP TIME ns Spf 13_/MEMCS16 HOLD TIME Ons 85ph 14_ (MAO SETUP TIME 16ns 85ph 15_/MAO HOLD TIME Ons 85ph 16 BHE SETUP TIME 2ns 85pf 17_[OCS16 SETUP TIME 9ns 85ph 18 MOCS16 HOLD TIME. Ons 85pf 19_RAMORAS, RAMIRAS DELAY Tans 25pf 20_RAMOCAS, RAMICAS DELAY 14ns 25ph 21_OWS SETUP TIME T2ns 85ph 22_OWS HOLD TIME Ons 85pf GC102 TIMING T6MHaiws __12MHz 12MHzOws lws 23_MA BUS TO ALE DELAY 32ns 24ns 85pf 24 MD TO D BUS DELAY T2ns____16.5ns 85pf February 1988 G-2 Incorporated # 1688 McCarthy Blvd. @ Milpitas, CA 95035 Preliminary | QRG-Two fay INC O2 deBarr77s oooona7 bP Royo) GC101/GC102 % Timing Diagrams GC101 Clock Timing CLK*2 | | | i I i E F 2 PROCCLK HISPEE! i So PROCCLK HISPEED =O February 1988 G-2 Incorporated © 1688 McCarthy Bivd. © Milpit 943-0224 AYG-Tuo {2 INC O2 DEB}3777475 oooo0ss 6 | —y-4yq-17-0} GC101/GC102 4 Timing Diagrams GC101 Input Signal Timing /MEMCS16 LS February 1988 G-2 Incorporated © 1688 McCarthy Blvd. @ Milpitas, CA 95035 © 408-943.9224 Preliminary !~~ g-Two fey INC o2 DEB) ar7747s oooonss o ff —r-4a-\1-0) : GC101/GC102 ° 4 Timing Diagrams ET t t GC101 Control Signal Timing proc \ of \ ff \_s \ ra i SYSCLK i \ mh $0,S1 ————_ $$$ February 1988 G-2 Incorporated © 168§ McCarthy Blvd. @ Milpitas, CA 95035 @ 408-943-0224 Preliminary“G-TwO fe} INC D2 DE—ar7747s ooooosa & ff 49-11-01 GC101/GC102 4 Timing Diagrams GC101 Output Signals PROCCLK \ / \ / \ | \ je RAMORAS } RAMIRAS RAMOCAS, RAMICAS~~ @-Tu0 {2} INC O2@ Def) 3777475 oooooq 6 WP -49-14-01 : GC101/GC102 y Timing Diagrams GC102 Address Buffer 0-20 X ALE (S0,S1 pin) \ GC102 Data Buffer MBDIR | MDO -15, J February 1988 Preliminary G-2 Incorporated © 1688 McCarthy Blvd. @ Milpitus, CA 95035 @ 408-943-0224 QFG-Tuo te} INC O2 eB) 3777475 oooooI2 o If +-49-17-01 GC101/GC102 4 Timing Diagrams GC101 12MHz Zero Wait State Timing /EMEMR JRASO j i \ : oa 08 NS February 1988 G-2 Incorporated @ 1655 McCarthy Blvd, @ Milpitas, CA 95035 © 408.943.0224 Preli aq3777475 G-TWO (2) ITEM QTY PART~! 10 12 12 3 14 1s 16 17 19 22 23 25 27 29 31 33 1 GC102DAT He39 R40 R40 R40 R40 R40 R40 R40 R40 R40 R40 R40 R40 R40 RSIPLOBA DIPSW4 Gc102ADD 80287 BATTH2 1N60 27256 74F08 G-Two {2} INC o2 Def) 3777475 oooo0a3 a Jf -———— GC101/GC102 TNC ozE o00es NAME REFERENCE-DESIGNATOR DESCRIPTION Device List for Production Board DHA Hoy U33 ¥3 VAL=32.768KHZ R18 R30 R28 R22 VAL#1K R24 R20 R21 R19 RS RE VAL=10K R26 R32 R23 R2 R33 Ril R16 VAL=30 R27 R15 R14 R29 R13 VAL=300 RO VALE2M R8 VAL=100 R10 R7 VAL=15 R12 R17 VAL=2.0M R3 R4 VAL=150 RL VAL=330 R25 VAL#=51K R31 VAL=470 za VAL#=30 si u46 . us1 BL CRI CRS u44 45 u32 Leanne ee eee een ee aE pUnEappeemere? May 20 1988 G-2 Incorporated © 1685 McCarthy Blvd, © Milpitas, CA 95035 © 408-943-02246-Tuo {2} INC 2 DEB} 3777475 cooooy a PS GC101/GC102 . % Device List for Production Board 3777475 G-TWO(2) INC eae Ob094 = 44-17 01 ITEM QTY PART-NAME REFERENCE-DESIGNATOR DESCRIPTION 35. 12 CORO20 can VAL#100pF 36) 1 congzo c42 VAL=50pF = 37 2 CoRO20 94 VAL=27pF t 38 2 ~— CoRo20 59 c60 VAL#15pF = 39 1 coRO20 C77 VAL=4.7nF oat 1 uci) Y2 VAL#14,318MHz 422 Hels y2 VAL=8 . O0OMH2 445 1X3PIN We Wi W3 W2 Wa . 46 2 Gerori60U47 “48 6 ~~ CONS6EMB -g2¢D g3CD JecD yeep 37¢D 31cD 50 8 CON62EMB J3AB J4AB JSAB J6AB J7AB J8AB J2AB J1AB 52 1 74ALS245 U5 54-2 2N3904 Q1 93 56 23 CERO10 96 C100 97 ¢3 VAL#=10uF 99 C98 C61 C72 92 cB6 ced C66 82 C80 C1 C15 C38 : 70 c90 ces ces C64 C134 58 1 8 Mcasssi8 «= Us2 60 1 Mc14069 = -US3 62 i RSIPBAA 25 VAL=10k 64 1 2N3906 Q2 66 2 RSIPBBA 22 71 67 1 RSIPSBA 23 VAL=30 4 : 69 MOLEX6 PS PE May 20 1988 G-2 Incorporated @ 1655 McCarthy Blvd, ¢ Milpitas, CA 95035 ¢ 40G-Tuo <2} INC O2 EM 3777475 ooONDaS 5 Tr 02E 00095 Ob +-4Q-(1-0J GC101/GC102 % Device List for Production Board ITEM QTY PART-NAME “REFERENCE-DESIGNATOR DESCRIPTION 3777475 G-TWO (2) INC Oi) J anata RS 73002 ~~ «AN914 CR3 CR2 759 1 DELAY4 u20 G7) ie = cozee uss 79 «36 4125610. 014 10 US U1 UI5 U11 U6 U2 U16 U12 U7 U3 U17 013 UB % U4 U9 U18 U38 U34 25 U21 U39 U35 U26 U22 U40 U36 U27 U23 041 U37 28 U24 U29 U42 1 18742 use 83 17406 uUs4 85 2 «1X4PIN P7 PL ge 2) D0d0) Li L2 VAL=2.2uH Oy 4 bee) UA3 VAL=25. 0OOOMHZ Sle 4 ixcerh) W7 P4 WS P2 93 2 16L8 U31 U30 95 1 74F112 vis ; S72 1XSPrth) P3 99 2 RSIP6AA 26 27 VAL=10K 101 1 — COAo30 c2 VAL=.01uF 102 98 COA030 78 C17 cB C4 C22 VAL=. 1uF 18 ¢c9 cS C23 C19 C10 C6 C24 C20 C11 C12 ¢25 c21 C44 33 ¢29 C49 C45 34 ¢30 C50 C46 €35 ¢31 51 C47 636 C32 37 C52 c48 C28 C62 C63 26 C27 C13 C14 May 20 1988 G-2 Incorporated 1655 McCarthy Blvd. ¢ Milpitas, CA 95035G2 1032 lode 105: 1) 1072 G-Tuo {2} INC 02 def) 3777475 oooo% 7 D sega OV ITEM QTY PART-NAME COA030 COA030 COA030 SPDINF GC101/GC102 Device List for Production Board REFERENCE-DESIGNATOR DESCRIPTION 39 C53 C16 C40 €130 C126 C122 118 C114 cil0 €106 C103 C129 €125 C121 C113 109 C105 C102 €131 C128 C127 124 120 C112 108 C104 C101 €123 ¢119 C115 ©111 C107 C87 C72 89 C73 C91 C93 65 C81 C67 CB3 69 C85 C79 C7 C54 €56 C74 C55 C75 ¢58 C43 C57 132 c133 VAL=47pF ¢95 c117 c116 c76 VAL=.047UF 39 Neen nN ETE NEEP yyy TerEEpTSPSsprret May 20 1988 : BR 2 Incorporated © 1655 McCarthy Blvd. @ Milpitas, CA 98035a GC101/GC102 4 Jumper Settings for Production Board 27128 EPROM DRAM ORAM Socket EPROM Socket EPROM Socket Socket DRAM DRAM Socket wre Socket Pe 12MHz 16MHz Zero Walt State One Wait State | oer oP6 oP5 uP4 Board Board Edge Mounting Edge Mounting Hole Co @) @) NY February 1988 G2 Incorporated @ 1655 McCarthy Blvd. @ Milpitas, CA 95035 © 408.943.0224G-Tuo {2} INC 02 DEB} ar77u7s oooooss o fF Huq} GC101/GC102 4 Switch Settings for Production Board ee Swi 1-HISPEED 2-1/0 HALF SPEED 3-RSELO 4-RSEL1 5 - RSEL2 NN EDU Sse February 1988 G-2 Incorporated © 1655 McCarthy Blvd. @ Milpitas, CA 95035 © 408-943-0224 3S—— 90088 NA ipay G-Two {2} INC 02 aggoone 3777475 o0000%9 rT 3777475 G-TWO (2) INC Jumper functions and setting for 286 system board j a EXTERNAL BATTERY CONNECTOR i 1 = POSITIVE 2 = Nc OR KEY 3 = GROUND 4 = GROUND 32 LOUD SPEAKER CONNECTION 2 = OUTPUT 2 = Ne OR KEY 3 = GROUND aot sv : 33 KEYBOARD . a4 mzsc 1 = LED POWER 2 = NC OR KEY 3 = GROUND 4 = KEYBOARD INHIBIT 5 = GROUND JP1 RESET JP2 -HI-SPEED OR TURBO LED JP3. MONOCHROME / COLOR JP{ -EMEMW SELECT - SELECT 2 AND 3 ALWAYS JP5 CLOCK _DELAY SELECTION 1-2 FOR 16 MHZ 2-3 FOR 12 MHZ oP6 DELAY LINE JUMPER - SELECT 1 AND 2 ALWAYS oP7 ZERO WAIT STATE SELECTION 1-2 FOR ows 2-3 FOR 1Ws ly ~G-TW0 {2} INC 02 Dep) 3777475 coooLoo s 2 ithe Plat Pack ve 030 Rg EEE WU SOOT we February 1988 G-2 Incorporated @ 1685 McCarthy Bivd. @ Milpitas, CA 95035 @ 408-943-0224 Preliminary Raoveci2a Package Outlines “777475 G-TWO (2) INC ~ 02— 00100 0 T-HG-(“-01 a ONLG-TuO {2} INC O2 dEPpar77475 coooIon 7 Peano GC101/GC102 Package Outlines bal more aaa BeoesuaE a February 1988 G-2 Incorporated @ 1685 McCarthy Blvd. Milpitas, CA 98035 @ 408-943-0224 Preliminary OeG-Tu0 {2} INC O2 def) 2777475 coon 9 F———— GC101/GC102 = Package Outlines "9777475 G-TWO (2) INC D2E DOI DEAT -OF }—_—- rasez - 91082 ————} miso 2eo16 - 28524 a | x |}____—— 1ee2 - 8262 ————— toz0e - 66006 February 1988 G2 Incorporated © 1655 McCarthy Blvd. @ Milpitas, CA 95035 « 408.943.0224 Preliminary 39G-Tu0 {2} INC 02 Def) az77475 oooo13 of tea Geddiecu02 G2 Package Outlines ET i ge at February 1988, G-2 Incorporated @ 1655 McCarthy Bly Preliminary Milpitas, CA 95035 © 408-943-0224 _ fovon 2 seep at ——~Gatuo 23 INC D2 vel 3777475 ooo0204 2 | t-49-1 GC101/GC102 Manufacturing Drawings Qi i Es Te cB Fy FeAl == ta (ical Lo Cs 4 leah LI HK bp Kesh i oa i 0. imal | folffcxiliCl eet FHI) ‘O ik | WH Ell YW spitte| EAI ES He Act IF 4 ES G-2 Incorporated 1685 McCarthy Blvd. © Milpitas, CA 95035 @ 408-943-0224G-Tuo {2} INC 02 DEB}a777475 ooooLns 4 Vocioyecio G 2 Manufacturing Drawings S7TTa7S Two 2) INC O28 00105 0 T=44-171-01 y q Ee £3 g5 2 $A A + z 8s 7 Qe i IL i | 5. lu ! = i 1. ni & | | tT 1 l l 1 — Fooraory 1588 Ga incorpornd'o 16HFNeCariy Birds © Miping CA 9505 « AON SSDOIDE Yu