A B C D E

ZZZ

LA-6321P
PCB@
DAZ0DJ00100
1 1

NCL60/61
2 2

LA-6321P REV 1.0 Schematic

3
Intel Processor ARD/ PCH HM55/NV N11M GE2, N11P-LP, 3

N11P-LP1(optimus)
2010-04-19 Rev 1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Monday, April 19, 2010 Sheet 1 of 59
A B C D E
 A B C D E

Fan Control VGA Thermal Sensor Clock Generator

APL5607 ADM1032ARMZ-2 RTM890N
Intel Arrandale page 6 page 14 page 23
PCIE-Express 16X 2.5GHz

rPGA-989 Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2 1

Dual Channel BANK 0, 1, 2, 3 page 11,12

page 5~10 1.5V DDRIII 800/1066/1333 MT/s

N11M-GE2 /N11P LP
N11M GE2, 64*16 512MB,128*16 1GB CRT USB/B Right Left USB Int. Camera
N11P-LP1/N11P-LP 64*16*8 1GB FDI X8 DMI X4 USB port 0,1 USB port 2 USB port 11
page 26 page 37 page 37 page 25
2.7GHz 2.5GHz
Optimus
BT conn
page 13~24
USB port 5
USB page 38
5V 480MHz
LVDS Conn.
page 25

2 2
USB
5V 480MHz PCIeMini Card
HDMI Conn. Level Shifter PCIe 1x
page 25 1.5V 2.5GHz(250MB/s) PCIe port 2 USB port 13

page 27
LPC BUS page 39
Intel Ibex Peak 3.3V 33 MHz

RTL8111E-GR SATA port 1 SATA HDD

RJ45 PCIe 1x 5V 3GHz(300MB/s) SATA port 1
w/o LED
page 38
QFN48_6X6 PCIe port 1 1.5V 2.5GHz(250MB/s) page 37
page 38
BGA-1071
SATA port 4 SATA ODD
5V 3GHz(300MB/s) SATA port 4
USB page 37
RTS5160-GR
5V 480MHz
LQFP 48P USB port12
page 41
3 3
page 28~36

HD Audio 3.3V/1.5V 24MHz

HDA Codec
ALC272
SPI ROM ENE KB926 D3/E0 page 42
page 43
(4MB)
page 28
RTC CKT.
page 45
Touch Pad Int.KBD EC ROM Int. SPK Conn JPIO
page 42
page 45 page 44 MIC Conn (HP &page
MIC)
DC/DC Interface CKT. (256KB)
page 44
page 23 42

page 44

4 4

Power Circuit DC/DC

page 47,48,49,50,51,52
53,54,55,56
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 200910/9 Deciphered Date 2010/01/23 Title

Power On/Off CKT. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
page 43 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
NCL60/61 LA-6321P M/B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 24, 2010 Sheet 2 of 59
A B C D E
 5 4 3 2 1

B+
Ipeak=5A, Imax=3.5A, Iocp min=7.9 DESIGN CURRENT 5A +5VALW

SUSP
D N-CHANNEL DESIGN CURRENT 4A +5VS D

SI4800

TPS51125RGER
Ipeak=5A, Imax=3.5A, Iocp min=7.7 DESIGN CURRENT 5A +3VALW
WOL_EN#
P-CHANNEL DESIGN CURRENT 330mA +3V_LAN
AO-3413

SUSP
N-CHANNEL DESIGN CURRENT 4A +3VS
SI4800
VGA_ENVDD
P-CHANNEL DESIGN CURRENT 1.5A +LCD_VDD
AO-3413
C C

BT_PWR#
DESIGN CURRENT 180mA +BT_VCC
P-CHANNEL
AO-3413
PCIE_OK
DESIGN CURRENT 100mA +3VS_DELAY
P-CHANNEL
AO-3413
VR_ON
DESIGN CURRENT 52A +CPU_CORE
ISL62883

SUSP#
DESIGN CURRENT 26A +VGA_CORE
ISL6268

VTTP_EN#
Ipeak=18A, Imax=12.6A, Iocp min=19.8 DESIGN CURRENT 18A +VTT
B B
ISL6268

SYSON
Ipeak=15A, Imax=10.5A, Iocp min=16.5 DESIGN CURRENT 15A +1.5V +1.5V_CPU
ISL6268 SUSP
DESIGN CURRENT 12A +1.5VS
N-CHANNEL
SI4856 SUSP
DESIGN CURRENT 1.5A +0.75VS
PCIE_OK
G2992F1U
DESIGN CURRENT 2A +1.1VS
SUSP# APL5913
DESIGN CURRENT 8A +1.8VS
TPS51117RGYR

SUSP#
A A

Ipeak=7A, Imax=4.9A, Iocp min=7.7 DESIGN CURRENT 7A +1.05VS

TPS51117RGYR
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Tree
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Wednesday, March 24, 2010 Sheet 3 of 59
5 4 3 2 1
 A B C D E

( O MEANS ON X MEANS OFF )

Voltage Rails
Platform SKU CPU PCH VGA
+RTCVCC +B +5VL +5VALW +1.5V +5VS UMA Arrandale HM55 N/A
+3VL +3VALW +3VS
+VSB +1.5VS
DIS Arrandale HM55 N11M-GE2
power
Calpella (OPT@)
1 plane +VGA_CORE 1

+CPU_CORE
+VTT
+1.05VS BOM configu table
+1.8VS
+1.1VS SKU Description Bom configu
State +0.75VS
1 UMA W/O TPM W/HDMI UMA@/PCB@/HDMI@/NTPM@ 45188030L01

2 UMA W/O TPM W/O HDMI UMA@/PCB@/NHDMI@/NTPM@ 45188030L02

3 DIS(N11M) W/HDMI W/TPM 1G VRAM TPM@/PCB@/OPT@/N11M@/SAM1G@/HDMI@ 45188030L14

4 DIS(N11M) W/HDMI W/OTPM 1G VRAM NTPM@/PCB@/OPT@/N11M@/HY1G@/HDMI@ 45188030L12

S0
O O O O O O 5 DIS(N11M) W/HDMI W/TPM 512MB VRAM TPM@/PCB@/OPT@/N11M@/HY512@/HDMI@/512@/8PCS@ 45188030L11

S1 6 DIS(N11M) W/HDMI W/O TPM 512M VRAM NTPM@/PCB@/OPT@/N11M@/SM512@/HDMI@ 45188030L13

O O O O O O
2
S3
7 DIS(N11P) W/HDMI WTPM 1GB VRAM 2
O O O O O X
8 DIS(N11P) W/HDMI W/O TPM 1GB VRAM NTPM@/PCB@/OPT@/N11P@/HDMI@/8PCS@/LP@ 45188030L15
S5 S4/AC
O O O O X X
S5 S4/ Battery only
O O O X X X
S5 S4/AC & Battery
don't exist
O X X X X X
N11M Hynix 512 X7623130L01
N11M SAM 512 X7623130L02
N11M Hynix 1G X7623130L03
N11M SAM 1G X7623130L04
EC SM Bus1 address EC SM Bus2 address
N11P Hynix 1G X7623130L05
Power Device Address Power Device Address
3 +3VL EC KB926 D3 +3VS EC KB926 D3 N11P SAM 1G X7623130L06 3

+3VL Smart Battery 0001 011x b +3VS AMD GPU Thermal Sensor 1001 101x b
+3VALW PCH 1001 011x b

ZZZ HY512@ ZZZ SM512@ ZZZ HY1G@

N11M Hynix 512 N11M SAM 512 N11M Hynix 1G

SIGNAL
PCH SM Bus address STATE SLP_S3# SLP_S4# SLP_S5# ZZZ SAM1G@
N11M SAM 1G
ZZZ N11P@
N11P Hynix
SAM1G
N11P SAM @

Power Device Address Full ON HIGH HIGH HIGH

+3VALW PCH
S1(Power On Suspend) HIGH HIGH HIGH
+3VS Clock Generator 1101 001x b
+3VS DDR DIMMA 1001 000x b S3 (Suspend to RAM) LOW HIGH HIGH
+3VS DDR DIMMB 1001 010x b
S4 (Suspend to Disk) LOW LOW HIGH UV1 UV1 UV1
+3VS WLAN Reserved for N11M-GE2 N11P-LP N11P-LP
common design.
S5 (Soft OFF) LOW LOW LOW N11M@ LP@ LP1@

4 G3 LOW LOW LOW 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Wednesday, March 31, 2010 Sheet 4 of 59
A B C D E
 5 4 3 2 1

JCPUB
1 2 H_COMP3 AT23
R1 20_0402_1% COMP3 CLK_CPU_BCLK
BCLK A16 CLK_CPU_BCLK 33

MISC
1 2 H_COMP2 AT24 B16 CLK_CPU_BCLK#
COMP2 BCLK# CLK_CPU_BCLK# 33
R2 20_0402_1%
H_COMP1 G16

CLOCKS
1 2 COMP1 BCLK_ITP AR30
@ R4 49.9_0402_1% AT30
1000P_0402_50V7K DRAMPWROK H_COMP0 AT26 BCLK_ITP#
2 1 C487 1 2 COMP0
R3 49.9_0402_1% E16 CLK_PEG CLK_PEG 29
@ PEG_CLK CLK_PEG#
PEG_CLK# D16 CLK_PEG# 29
1000P_0402_50V7K 2 1 C488 VTTPWROK_CPU PAD T41
TP_SKTOCC# AH24 SKTOCC#
+VTT A18
DPLL_REF_SSCLK
DPLL_REF_SSCLK# A17 Unused by Clarksfield rPGA989 +VTT
D 1 2 CATERR# AK14 D
CATERR#

THERMAL
R18 49.9_0402_1%

F6 SM_DRAMRST#_CPU PM_EXTTS#0 R15 2 1 10K_0402_5%

PECI SM_DRAMRST#
33 PECI AT15 PECI
SM_RCOMP[0] AL1 SM_RCOMP_0 R6 1 2 100_0402_1% DDR3 Compensation Signals PM_EXTTS#_R R13 2 1 10K_0402_5%
Power has removed VR_TT# SM_RCOMP[1] AM1 SM_RCOMP_1 R7 1 2 24.9_0402_1% Layout Note:Please these
SM_RCOMP[2] AN1 SM_RCOMP_2 R8 1 2 130_0402_1% resistors near Processor XDP_TDO R162 1 2 51_0402_5%
1 2 H_PROCHOT# AN26
+VTT +VTT PROCHOT#
R9 68_0402_5% AN15 PM_EXTTS#0

DDR3
MISC
PM_EXT_TS#[0]
PM_EXT_TS#[1] AP15 PM_EXTTS#_R 2 1 PM_EXTTS# 11,12
R12 0_0402_5%
H_THERMTRIP# AK15
33 H_THERMTRIP# THERMTRIP#
2

R10
68_0402_5% PRDY# AT28
@ AP27 XDP_TDI_R 1 2 XDP_TDI
PREQ# R20 0_0402_5%
1

TCK AN28
H_CPURST# H_CPURST# AP26 AP28 Routed as a single daisy chain XDP_TDO_M 1 @ 2 XDP_TDO
RESET_OBS# TMS

PWR MANAGEMENT
AT27 R21 0_0402_5%
TRST#

1
JTAG & BPM
PMSYNCH AL15 AT29 XDP_TDI_R R23
30 PMSYNCH PM_SYNC TDI
AR27 XDP_TDO_R 0_0402_5%
TDO XDP_TDI_M
TDI_M AR29 2 1 +3VS
2 1 H_PWRGOOD1_R AN14 AP29 XDP_TDO_M R312 1K_0402_5%

2
+1.5V_CPU +1.5V 0_0402_5% R25 VCCPWRGOOD_1 TDO_M XDP_TDI_M 1 @ 2
AN25 XDP_DBRESET# R26 0_0402_5%
DBR# XDP_DBRESET# 30
H_PWRGOOD AN27 Close to CPU for EMI
33 H_PWRGOOD VCCPWRGOOD_0
C XDP_TDO_R 1 2 C
2

AJ22 R27 0_0402_5%

BPM#[0]
1.1K_0402_1%

R36 R28 DRAMPWROK AK13 AK22

30 DRAMPWROK SM_DRAMPWROK BPM#[1]
1.1K_0402_1% AK24
@ @ BPM#[2]
BPM#[3] AJ24
51 VTTPWROK_CPU VTTPWROK_CPU AM15 AJ25
1

VTTPWRGOOD BPM#[4]
BPM#[5] AH22
DRAMPWROK AK23
BPM#[6]
AM26 TAPPWRGOOD BPM#[7] AH23
JTAG MAPPING
2

R29 R29
32,38 BUF_PLT_RST# 1 2 BUF_PLT_RST#_R AL14 RSTIN#
750_0402_1% 3K_0402_1% 1.5K_0402_1% R30 1 Scan Chain STUFF -> R20, R23, R27
@ (Default) NO STUFF -> R21, R26
R31
1

750_0402_1% IC,AUB_CFD_rPGA,R0P9 CONN@

CPU Only STUFF -> R20, R21
NO STUFF -> R23, R26, R27
2

GMCH Only STUFF -> R26, R27

NO STUFF -> R20, R21, R23

B
For S3 CPU Power Saving B

@
2 1
R19 0_0402_5%

+3VALW
S

SM_DRAMRST#_CPU 3 1 SM_DRAMRST# 11,12

1

Q41
G

1 2
2

C163 0.1U_0402_16V4Z R123 2N7002_SOT23-3

100K_0402_5%
5

U10 RST_GATE 33
2

46,51 VTTPWROK VTTPWROK 1

P

IN1 DRAMPWROK
O 4 2 1
2 R33 1.5K_0402_1% 1
IN2
G

C140
SN74AHC1G08DCKR_SC70-5 0.047U_0402_25V6K
3

2
Add C140 for RST_GATE Glitch issue
2 @ 1
R52 0_0402_5%
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CLK/MISC/JTAG/XDP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Thursday, April 15, 2010 Sheet 5 of 57
5 4 3 2 1
 5 4 3 2 1

+5VS
FAN Control Circuit

1A

JFAN
2
+FAN1 1
C3 1
2 2
10U_0805_10V4Z 3
1 3
D 2 D
C4 4
U1 1000P_0402_25V8J GND
5
@ GND
1 8
EN GND 1 ACES_85205-03001
2 VIN GND 7
+FAN1 3 6 CONN@
VOUT GND
43 EN_DFAN1 4 VSET GND 5
1 R34 10K_0402_5%
10mil APL5607KI-TRG_SO8 2 1 +3VS
C5
10U_0805_10V4Z FAN_SPEED1 43
2
2
C6
0.01U_0402_16V7K
JCPUA @
PEG_COMP 1 1
B26 2
PEG_ICOMPI R38 49.9_0402_1%
A26
DMI_PTX_CRX_N0 PEG_ICOMPO
30 DMI_PTX_CRX_N0 A24 B27
DMI_PTX_CRX_N1 DMI_RX#[0] PEG_RCOMPO PEG_RBIAS 1
30 DMI_PTX_CRX_N1 C23 A25 2
DMI_PTX_CRX_N2 DMI_RX#[1] PEG_RBIAS R39 750_0402_1%
30 DMI_PTX_CRX_N2 B22 DMI_RX#[2] PCIE_GTX_C_CRX_N[0..15] 13
DMI_PTX_CRX_N3 A21 K35 PCIE_GTX_C_CRX_N15
30 DMI_PTX_CRX_N3 DMI_RX#[3] PEG_RX#[0]
J34 PCIE_GTX_C_CRX_N14
DMI_PTX_CRX_P0 PEG_RX#[1] PCIE_GTX_C_CRX_N13
30 DMI_PTX_CRX_P0 B24 J33
DMI_PTX_CRX_P1 DMI_RX[0] PEG_RX#[2] PCIE_GTX_C_CRX_N12
30 DMI_PTX_CRX_P1 D23 G35
DMI_RX[1] PEG_RX#[3]

DMI
DMI_PTX_CRX_P2 B23 G32 PCIE_GTX_C_CRX_N11
30 DMI_PTX_CRX_P2 DMI_RX[2] PEG_RX#[4]
DMI_PTX_CRX_P3 A22 F34 PCIE_GTX_C_CRX_N10
30 DMI_PTX_CRX_P3 DMI_RX[3] PEG_RX#[5]
F31 PCIE_GTX_C_CRX_N9
DMI_CTX_PRX_N0 PEG_RX#[6] PCIE_GTX_C_CRX_N8
30 DMI_CTX_PRX_N0 D24 D35
DMI_CTX_PRX_N1 DMI_TX#[0] PEG_RX#[7] PCIE_GTX_C_CRX_N7
30 DMI_CTX_PRX_N1 G24 E33
C DMI_CTX_PRX_N2 DMI_TX#[1] PEG_RX#[8] PCIE_GTX_C_CRX_N6 C
30 DMI_CTX_PRX_N2 F23 DMI_TX#[2] PEG_RX#[9] C33
DMI_CTX_PRX_N3 H23 D32 PCIE_GTX_C_CRX_N5
30 DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10]
B32 PCIE_GTX_C_CRX_N4
DMI_CTX_PRX_P0 PEG_RX#[11] PCIE_GTX_C_CRX_N3
30 DMI_CTX_PRX_P0 D25 C31
DMI_CTX_PRX_P1 DMI_TX[0] PEG_RX#[12] PCIE_GTX_C_CRX_N2
30 DMI_CTX_PRX_P1 F24 B28
DMI_CTX_PRX_P2 DMI_TX[1] PEG_RX#[13] PCIE_GTX_C_CRX_N1
30 DMI_CTX_PRX_P2 E23 DMI_TX[2] PEG_RX#[14] B30
DMI_CTX_PRX_P3 G23 A31 PCIE_GTX_C_CRX_N0
30 DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15]
PCIE_GTX_C_CRX_P[0..15] 13
J35 PCIE_GTX_C_CRX_P15
PEG_RX[0] PCIE_GTX_C_CRX_P14
H34
PEG_RX[1] PCIE_GTX_C_CRX_P13
H33
FDI_CTX_PRX_N0 PEG_RX[2] PCIE_GTX_C_CRX_P12
30 FDI_CTX_PRX_N0 E22 F35
FDI_CTX_PRX_N1 FDI_TX#[0] PEG_RX[3] PCIE_GTX_C_CRX_P11
30 FDI_CTX_PRX_N1 D21 FDI_TX#[1] PEG_RX[4] G33
FDI_CTX_PRX_N2 D19 E34 PCIE_GTX_C_CRX_P10
30 FDI_CTX_PRX_N2 FDI_TX#[2] PEG_RX[5]
FDI_CTX_PRX_N3 D18 F32 PCIE_GTX_C_CRX_P9
30 FDI_CTX_PRX_N3 FDI_TX#[3] PEG_RX[6]
FDI_CTX_PRX_N4 G21 D34 PCIE_GTX_C_CRX_P8
30 FDI_CTX_PRX_N4 FDI_TX#[4] PEG_RX[7]
PCI EXPRESS -- GRAPHICS

FDI_CTX_PRX_N5 E19 F33 PCIE_GTX_C_CRX_P7

30 FDI_CTX_PRX_N5 FDI_TX#[5] PEG_RX[8]
FDI_CTX_PRX_N6 F21 B33 PCIE_GTX_C_CRX_P6
30 FDI_CTX_PRX_N6 FDI_TX#[6] PEG_RX[9]
Intel(R) FDI

FDI_CTX_PRX_N7 G18 D31 PCIE_GTX_C_CRX_P5

30 FDI_CTX_PRX_N7 FDI_TX#[7] PEG_RX[10]
A32 PCIE_GTX_C_CRX_P4
PEG_RX[11] PCIE_GTX_C_CRX_P3
C30
FDI_CTX_PRX_P0 PEG_RX[12] PCIE_GTX_C_CRX_P2
30 FDI_CTX_PRX_P0 D22 A28
FDI_CTX_PRX_P1 FDI_TX[0] PEG_RX[13] PCIE_GTX_C_CRX_P1
30 FDI_CTX_PRX_P1 C21 B29
FDI_CTX_PRX_P2 FDI_TX[1] PEG_RX[14] PCIE_GTX_C_CRX_P0
30 FDI_CTX_PRX_P2 D20 A30
FDI_CTX_PRX_P3 FDI_TX[2] PEG_RX[15]
30 FDI_CTX_PRX_P3 C18 PCIE_CTX_C_GRX_N[0..15] 13
FDI_CTX_PRX_P4 FDI_TX[3] PCIE_CTX_GRX_N15 C39 OPT@1 0.1U_0402_16V7K PCIE_CTX_C_GRX_N15
30 FDI_CTX_PRX_P4 G22 FDI_TX[4] PEG_TX#[0] L33 2
FDI_CTX_PRX_P5 E20 M35 PCIE_CTX_GRX_N14 C40 OPT@1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N14
30 FDI_CTX_PRX_P5 FDI_TX[5] PEG_TX#[1]
FDI_CTX_PRX_P6 F20 M33 PCIE_CTX_GRX_N13 C41 OPT@1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N13
30 FDI_CTX_PRX_P6 FDI_TX[6] PEG_TX#[2]
FDI_CTX_PRX_P7 G19 M30 PCIE_CTX_GRX_N12 C42 OPT@1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N12
B 30 FDI_CTX_PRX_P7 FDI_TX[7] PEG_TX#[3] B
L31 PCIE_CTX_GRX_N11 C43 OPT@1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N11
FDI_FSYNC0 PEG_TX#[4] PCIE_CTX_GRX_N10 C44 OPT@1 0.1U_0402_16V7K PCIE_CTX_C_GRX_N10
30 FDI_FSYNC0 F17 K32 2
FDI_FSYNC1 FDI_FSYNC[0] PEG_TX#[5] PCIE_CTX_GRX_N9 C45 OPT@1 0.1U_0402_16V7K PCIE_CTX_C_GRX_N9
30 FDI_FSYNC1 E17 M29 2
FDI_FSYNC[1] PEG_TX#[6] PCIE_CTX_GRX_N8 C46 OPT@1 0.1U_0402_16V7K PCIE_CTX_C_GRX_N8
PEG_TX#[7] J31 2
30 FDI_INT FDI_INT C17 K29 PCIE_CTX_GRX_N7 C47 OPT@1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N7
FDI_INT PEG_TX#[8] PCIE_CTX_GRX_N6 C48 OPT@1 0.1U_0402_16V7K PCIE_CTX_C_GRX_N6
PEG_TX#[9] H30 2
30 FDI_LSYNC0 FDI_LSYNC0 F18 H29 PCIE_CTX_GRX_N5 C49 OPT@1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N5
FDI_LSYNC1 FDI_LSYNC[0] PEG_TX#[10] PCIE_CTX_GRX_N4 C50 OPT@1 0.1U_0402_16V7K PCIE_CTX_C_GRX_N4
30 FDI_LSYNC1 D17 F29 2
FDI_LSYNC[1] PEG_TX#[11] PCIE_CTX_GRX_N3 C51 OPT@1 0.1U_0402_16V7K PCIE_CTX_C_GRX_N3
PEG_TX#[12] E28 2
D29 PCIE_CTX_GRX_N2 C52 OPT@1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N2
PEG_TX#[13] PCIE_CTX_GRX_N1 C53 OPT@1 0.1U_0402_16V7K PCIE_CTX_C_GRX_N1
D27 2
PEG_TX#[14] PCIE_CTX_GRX_N0 C54 OPT@1 0.1U_0402_16V7K PCIE_CTX_C_GRX_N0
PEG_TX#[15] C26 2
PCIE_CTX_C_GRX_P[0..15] 13
L34 PCIE_CTX_GRX_P15 C55 OPT@1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P15
PEG_TX[0] PCIE_CTX_GRX_P14 C56 OPT@1 0.1U_0402_16V7K PCIE_CTX_C_GRX_P14
M34 2
PEG_TX[1] PCIE_CTX_GRX_P13 C57 OPT@1 0.1U_0402_16V7K PCIE_CTX_C_GRX_P13
M32 2
PEG_TX[2] PCIE_CTX_GRX_P12 C58 OPT@1 0.1U_0402_16V7K PCIE_CTX_C_GRX_P12
L30 2
PEG_TX[3] PCIE_CTX_GRX_P11 C59 OPT@1 0.1U_0402_16V7K PCIE_CTX_C_GRX_P11
M31 2
PEG_TX[4] PCIE_CTX_GRX_P10 C60 OPT@1 0.1U_0402_16V7K PCIE_CTX_C_GRX_P10
PEG_TX[5] K31 2
M28 PCIE_CTX_GRX_P9 C61 OPT@1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P9
PEG_TX[6] PCIE_CTX_GRX_P8 C62 OPT@1 0.1U_0402_16V7K PCIE_CTX_C_GRX_P8
H31 2
PEG_TX[7] PCIE_CTX_GRX_P7 C63 OPT@1 0.1U_0402_16V7K PCIE_CTX_C_GRX_P7
K28 2
PEG_TX[8] PCIE_CTX_GRX_P6 C64 OPT@1 0.1U_0402_16V7K PCIE_CTX_C_GRX_P6
G30 2
PEG_TX[9] PCIE_CTX_GRX_P5 C65 OPT@1 0.1U_0402_16V7K PCIE_CTX_C_GRX_P5
G29 2
PEG_TX[10] PCIE_CTX_GRX_P4 C66 OPT@1 0.1U_0402_16V7K PCIE_CTX_C_GRX_P4
F28 2
PEG_TX[11] PCIE_CTX_GRX_P3 C67 OPT@1 0.1U_0402_16V7K PCIE_CTX_C_GRX_P3
PEG_TX[12] E27 2
D28 PCIE_CTX_GRX_P2 C68 OPT@1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P2
PEG_TX[13] PCIE_CTX_GRX_P1 C69 OPT@1 0.1U_0402_16V7K PCIE_CTX_C_GRX_P1
C27 2
PEG_TX[14] PCIE_CTX_GRX_P0 C70 OPT@1 0.1U_0402_16V7K PCIE_CTX_C_GRX_P0
A C25 2 A
PEG_TX[15]

IC,AUB_CFD_rPGA,R0P9 CONN@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_DMI/FDI/PEG/FAN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Wednesday, April 14, 2010 Sheet 6 of 57
5 4 3 2 1
 5 4 3 2 1

JCPUC JCPUD

11 DDR_A_D[0..63] 12 DDR_B_D[0..63]

AA6 DDRA_CLK0 W8 DDRB_CLK0

SA_CK[0] DDRA_CLK0 11 SB_CK[0] DDRB_CLK0 12
AA7 DDRA_CLK0# W9 DDRB_CLK0#
SA_CK#[0] DDRA_CLK0# 11 SB_CK#[0] DDRB_CLK0# 12
P7 DDRA_CKE0 DDR_B_D0 B5 M3 DDRB_CKE0
SA_CKE[0] DDRA_CKE0 11 SB_DQ[0] SB_CKE[0] DDRB_CKE0 12
DDR_A_D0 A10 DDR_B_D1 A5
DDR_A_D1 SA_DQ[0] DDR_B_D2 SB_DQ[1]
C10 SA_DQ[1] C3 SB_DQ[2]
D DDR_A_D2 C7 DDR_B_D3 B3 V7 DDRB_CLK1 D
SA_DQ[2] SB_DQ[3] SB_CK[1] DDRB_CLK1 12
DDR_A_D3 A7 Y6 DDRA_CLK1 DDR_B_D4 E4 V6 DDRB_CLK1#
SA_DQ[3] SA_CK[1] DDRA_CLK1 11 SB_DQ[4] SB_CK#[1] DDRB_CLK1# 12
DDR_A_D4 B10 Y5 DDRA_CLK1# DDR_B_D5 A6 M2 DDRB_CKE1
SA_DQ[4] SA_CK#[1] DDRA_CLK1# 11 SB_DQ[5] SB_CKE[1] DDRB_CKE1 12
DDR_A_D5 D10 P6 DDRA_CKE1 DDR_B_D6 A4
SA_DQ[5] SA_CKE[1] DDRA_CKE1 11 SB_DQ[6]
DDR_A_D6 E10 DDR_B_D7 C4
DDR_A_D7 SA_DQ[6] DDR_B_D8 SB_DQ[7]
A8 SA_DQ[7] D1 SB_DQ[8]
DDR_A_D8 D8 DDR_B_D9 D2
DDR_A_D9 SA_DQ[8] DDRA_SCS0# DDR_B_D10 SB_DQ[9] DDRB_SCS0#
F10 SA_DQ[9] SA_CS#[0] AE2 DDRA_SCS0# 11 F2 SB_DQ[10] SB_CS#[0] AB8 DDRB_SCS0# 12
DDR_A_D10 E6 AE8 DDRA_SCS1# DDR_B_D11 F1 AD6 DDRB_SCS1#
SA_DQ[10] SA_CS#[1] DDRA_SCS1# 11 SB_DQ[11] SB_CS#[1] DDRB_SCS1# 12
DDR_A_D11 F7 DDR_B_D12 C2
DDR_A_D12 SA_DQ[11] DDR_B_D13 SB_DQ[12]
E9 SA_DQ[12] F5 SB_DQ[13]
DDR_A_D13 B7 DDR_B_D14 F3
DDR_A_D14 SA_DQ[13] DDRA_ODT0 DDR_B_D15 SB_DQ[14] DDRB_ODT0
E7 SA_DQ[14] SA_ODT[0] AD8 DDRA_ODT0 11 G4 SB_DQ[15] SB_ODT[0] AC7 DDRB_ODT0 12
DDR_A_D15 C6 AF9 DDRA_ODT1 DDR_B_D16 H6 AD1 DDRB_ODT1
SA_DQ[15] SA_ODT[1] DDRA_ODT1 11 SB_DQ[16] SB_ODT[1] DDRB_ODT1 12
DDR_A_D16 H10 DDR_B_D17 G2
SA_DQ[16] SB_DQ[17]
DDR_A_D17 G8 SA_DQ[17]
DDR_B_D18 J6 SB_DQ[18] Unused by Clarksfield rPGA989
DDR_A_D18 K7 SA_DQ[18] Unused by Clarksfield rPGA989 DDR_B_D19 J3 SB_DQ[19]
DDR_A_D19 J8 DDR_B_D20 G1
SA_DQ[19] SB_DQ[20] DDR_B_DM[0..7] 12
DDR_A_D20 G7 DDR_B_D21 G5 D4 DDR_B_DM0
SA_DQ[20] DDR_A_DM[0..7] 11 SB_DQ[21] SB_DM[0]
DDR_A_D21 G10 DDR_B_D22 J2 E1 DDR_B_DM1
DDR_A_D22 SA_DQ[21] DDR_A_DM0 DDR_B_D23 SB_DQ[22] SB_DM[1] DDR_B_DM2
J7 SA_DQ[22] SA_DM[0] B9 J1 SB_DQ[23] SB_DM[2] H3
DDR_A_D23 J10 D7 DDR_A_DM1 DDR_B_D24 J5 K1 DDR_B_DM3
DDR_A_D24 SA_DQ[23] SA_DM[1] DDR_A_DM2 DDR_B_D25 SB_DQ[24] SB_DM[3] DDR_B_DM4
L7 SA_DQ[24] SA_DM[2] H7 K2 SB_DQ[25] SB_DM[4] AH1
DDR_A_D25 M6 M7 DDR_A_DM3 DDR_B_D26 L3 AL2 DDR_B_DM5
DDR_A_D26 SA_DQ[25] SA_DM[3] DDR_A_DM4 DDR_B_D27 SB_DQ[26] SB_DM[5] DDR_B_DM6
M8 SA_DQ[26] SA_DM[4] AG6 M1 SB_DQ[27] SB_DM[6] AR4
DDR_A_D27 L9 AM7 DDR_A_DM5 DDR_B_D28 K5 AT8 DDR_B_DM7
DDR_A_D28 SA_DQ[27] SA_DM[5] DDR_A_DM6 DDR_B_D29 SB_DQ[28] SB_DM[7]
L6 SA_DQ[28] SA_DM[6] AN10 K4 SB_DQ[29]
DDR_A_D29 K8 AN13 DDR_A_DM7 DDR_B_D30 M4
DDR_A_D30 SA_DQ[29] SA_DM[7] DDR_B_D31 SB_DQ[30]
N8 SA_DQ[30] N5 SB_DQ[31]
C DDR_A_D31 P9 DDR_B_D32 AF3 C
DDR_A_D32 SA_DQ[31] DDR_B_D33 SB_DQ[32]
AH5 SA_DQ[32] AG1 SB_DQ[33] DDR_B_DQS#[0..7] 12
DDR_A_D33 AF5 DDR_B_D34 AJ3 D5 DDR_B_DQS#0
SA_DQ[33] DDR_A_DQS#[0..7] 11 SB_DQ[34] SB_DQS#[0]
DDR_A_D34 AK6 C9 DDR_A_DQS#0 DDR_B_D35 AK1 F4 DDR_B_DQS#1
DDR SYSTEM MEMORY A

DDR_A_D35 SA_DQ[34] SA_DQS#[0] DDR_A_DQS#1 DDR_B_D36 SB_DQ[35] SB_DQS#[1] DDR_B_DQS#2

AK7 SA_DQ[35] SA_DQS#[1] F8 AG4 SB_DQ[36] SB_DQS#[2] J4
DDR_A_D36 AF6 J9 DDR_A_DQS#2 DDR_B_D37 AG3 L4 DDR_B_DQS#3
DDR_A_D37 SA_DQ[36] SA_DQS#[2] SB_DQ[37] SB_DQS#[3]
AG5 N9 DDR_A_DQS#3 DDR_B_D38 AJ4 AH2 DDR_B_DQS#4

DDR SYSTEM MEMORY - B

DDR_A_D38 SA_DQ[37] SA_DQS#[3] SB_DQ[38] SB_DQS#[4]
AJ7 SA_DQ[38] SA_DQS#[4] AH7 DDR_A_DQS#4 DDR_B_D39 AH4 SB_DQ[39] SB_DQS#[5] AL4 DDR_B_DQS#5
DDR_A_D39 AJ6 AK9 DDR_A_DQS#5 DDR_B_D40 AK3 AR5 DDR_B_DQS#6
DDR_A_D40 SA_DQ[39] SA_DQS#[5] SB_DQ[40] SB_DQS#[6]
AJ10 SA_DQ[40] SA_DQS#[6] AP11 DDR_A_DQS#6 DDR_B_D41 AK4 SB_DQ[41] SB_DQS#[7] AR8 DDR_B_DQS#7
DDR_A_D41 AJ9 AT13 DDR_A_DQS#7 DDR_B_D42 AM6
DDR_A_D42 SA_DQ[41] SA_DQS#[7] DDR_B_D43 SB_DQ[42]
AL10 SA_DQ[42] AN2 SB_DQ[43]
DDR_A_D43 AK12 DDR_B_D44 AK5
DDR_A_D44 SA_DQ[43] DDR_B_D45 SB_DQ[44]
AK8 SA_DQ[44] AK2 SB_DQ[45]
DDR_A_D45 AL7 DDR_B_D46 AM4
SA_DQ[45] DDR_A_DQS[0..7] 11 SB_DQ[46]
DDR_A_D46 AK11 C8 DDR_A_DQS0 DDR_B_D47 AM3
SA_DQ[46] SA_DQS[0] SB_DQ[47] DDR_B_DQS[0..7] 12
DDR_A_D47 AL8 F9 DDR_A_DQS1 DDR_B_D48 AP3 C5 DDR_B_DQS0
DDR_A_D48 SA_DQ[47] SA_DQS[1] DDR_A_DQS2 DDR_B_D49 SB_DQ[48] SB_DQS[0] DDR_B_DQS1
AN8 SA_DQ[48] SA_DQS[2] H9 AN5 SB_DQ[49] SB_DQS[1] E3
DDR_A_D49 AM10 M9 DDR_A_DQS3 DDR_B_D50 AT4 H4 DDR_B_DQS2
DDR_A_D50 SA_DQ[49] SA_DQS[3] DDR_A_DQS4 DDR_B_D51 SB_DQ[50] SB_DQS[2] DDR_B_DQS3
AR11 SA_DQ[50] SA_DQS[4] AH8 AN6 SB_DQ[51] SB_DQS[3] M5
DDR_A_D51 AL11 AK10 DDR_A_DQS5 DDR_B_D52 AN4 AG2 DDR_B_DQS4
DDR_A_D52 SA_DQ[51] SA_DQS[5] DDR_A_DQS6 DDR_B_D53 SB_DQ[52] SB_DQS[4] DDR_B_DQS5
AM9 SA_DQ[52] SA_DQS[6] AN11 AN3 SB_DQ[53] SB_DQS[5] AL5
DDR_A_D53 AN9 AR13 DDR_A_DQS7 DDR_B_D54 AT5 AP5 DDR_B_DQS6
DDR_A_D54 SA_DQ[53] SA_DQS[7] DDR_B_D55 SB_DQ[54] SB_DQS[6] DDR_B_DQS7
AT11 SA_DQ[54] AT6 SB_DQ[55] SB_DQS[7] AR7
DDR_A_D55 AP12 DDR_B_D56 AN7
DDR_A_D56 SA_DQ[55] DDR_B_D57 SB_DQ[56]
AM12 SA_DQ[56] DDR_A_MA[0..15] 11 AP6 SB_DQ[57]
DDR_A_D57 AN12 DDR_B_D58 AP8
DDR_A_D58 SA_DQ[57] DDR_A_MA0 DDR_B_D59 SB_DQ[58]
AM13 SA_DQ[58] SA_MA[0] Y3 AT9 SB_DQ[59]
DDR_A_D59 AT14 W1 DDR_A_MA1 DDR_B_D60 AT7
B DDR_A_D60 SA_DQ[59] SA_MA[1] DDR_A_MA2 DDR_B_D61 SB_DQ[60] B
AT12 SA_DQ[60] SA_MA[2] AA8 AP9 SB_DQ[61]
DDR_A_D61 AL13 AA3 DDR_A_MA3 DDR_B_D62 AR10
SA_DQ[61] SA_MA[3] SB_DQ[62] DDR_B_MA[0..15] 12
DDR_A_D62 AR14 V1 DDR_A_MA4 DDR_B_D63 AT10 U5 DDR_B_MA0
DDR_A_D63 SA_DQ[62] SA_MA[4] DDR_A_MA5 SB_DQ[63] SB_MA[0] DDR_B_MA1
AP14 SA_DQ[63] SA_MA[5] AA9 SB_MA[1] V2
V8 DDR_A_MA6 T5 DDR_B_MA2
SA_MA[6] DDR_A_MA7 SB_MA[2] DDR_B_MA3
SA_MA[7] T1 SB_MA[3] V3
Y9 DDR_A_MA8 R1 DDR_B_MA4
DDR_A_BS0 SA_MA[8] DDR_A_MA9 DDR_B_BS0 SB_MA[4] DDR_B_MA5
11 DDR_A_BS0 AC3 SA_BS[0] SA_MA[9] U6 12 DDR_B_BS0 AB1 SB_BS[0] SB_MA[5] T8
DDR_A_BS1 AB2 AD4 DDR_A_MA10 DDR_B_BS1 W5 R2 DDR_B_MA6
11 DDR_A_BS1 SA_BS[1] SA_MA[10] 12 DDR_B_BS1 SB_BS[1] SB_MA[6]
DDR_A_BS2 U7 T2 DDR_A_MA11 DDR_B_BS2 R7 R6 DDR_B_MA7
11 DDR_A_BS2 SA_BS[2] SA_MA[11] 12 DDR_B_BS2 SB_BS[2] SB_MA[7]
U3 DDR_A_MA12 R4 DDR_B_MA8
SA_MA[12] DDR_A_MA13 SB_MA[8] DDR_B_MA9
SA_MA[13] AG8 SB_MA[9] R5
T3 DDR_A_MA14 DDR_B_CAS# AC5 AB5 DDR_B_MA10
SA_MA[14] 12 DDR_B_CAS# SB_CAS# SB_MA[10]
DDR_A_CAS# AE1 V9 DDR_A_MA15 DDR_B_RAS# Y7 P3 DDR_B_MA11
11 DDR_A_CAS# SA_CAS# SA_MA[15] 12 DDR_B_RAS# SB_RAS# SB_MA[11]
DDR_A_RAS# AB3 DDR_B_WE# AC6 R3 DDR_B_MA12
11 DDR_A_RAS# SA_RAS# 12 DDR_B_WE# SB_WE# SB_MA[12]
DDR_A_WE# AE9 AF7 DDR_B_MA13
11 DDR_A_WE# SA_WE# SB_MA[13]
P5 DDR_B_MA14
SB_MA[14] DDR_B_MA15
SB_MA[15] N1

IC,AUB_CFD_rPGA,R0P9
CONN@

A A
IC,AUB_CFD_rPGA,R0P9
CONN@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_DDR3
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Wednesday, April 14, 2010 Sheet 7 of 57
5 4 3 2 1
 5 4 3 2 1

Material Note (+VTT):

JCPUF
390uF/ 10mohm, number are 3,
power x1, HW x2

+CPU_CORE Clarksfield: 65A Clarksfield: 21A (Place these capacitors under CPU socket Edge, top layer) (Place these capacitors between inductor and socket on Bottom)
+VTT
Auburndale:48A Auburndale:18A +CPU_CORE
AG35 VCC1 VTT0_1 AH14
AG34 AH12 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K
D VCC2 VTT0_2 D
AG33 AH11
VCC3 VTT0_3
AG32 AH10 1 1 1 1 1 1 1 1 1
VCC4 VTT0_4 C144 1
AG31 VCC5 VTT0_5 J14 2 330U_D2_2V_Y C81 1 2 10U_0805_10V4K
AG30 J13

+
VCC6 VTT0_6 C267 1
AG29 H14 2 330U_D2_2V_Y C83 1 2 10U_0805_10V4K C71 C72 C73 C74 C75 C76 C77 C78 C79
VCC7 VTT0_7 2 2 2 2 2 2 2 2 2
AG28 H12

+
VCC8 VTT0_8 C85 1
AG27 G14 2 10U_0805_10V4K
VCC9 VTT0_9 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K
AG26 G13
VCC10 VTT0_10 C89 1
AF35 VCC11 VTT0_11 G12 2 10U_0805_10V4K
AF34 G11 C87 1 2 22U_0805_6.3V6M
VCC12 VTT0_12 C88 1
AF33 F14 2 10U_0805_10V4K
VCC13 VTT0_13 C91 1
AF32 F13 2 22U_0805_6.3V6M
VCC14 VTT0_14 C90 1
AF31 F12 2 10U_0805_10V4K
VCC15 VTT0_15
AF30
VCC16 VTT0_16
F11 (Place these capacitors under CPU socket, top layer)
AF29 E14 C92 1 2 10U_0805_10V4K
VCC17 VTT0_17
AF28 E12
VCC18 VTT0_18 C94 1 +CPU_CORE
AF27 D14 2 10U_0805_10V4K
VCC19 VTT0_19 @
AF26 D13
VCC20 VTT0_20
1.1V RAIL POWER
AD35 D12 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K
VCC21 VTT0_21
AD34 VCC22 VTT0_22 D11
AD33 C14 1 1 1 1 1 1 1
VCC23 VTT0_23
AD32 C13
VCC24 VTT0_24
AD31 C12
VCC25 VTT0_25 C98 C99 C100 C101 C102 C103 C104
AD30 C11
VCC26 VTT0_26 2 2 2 2 2 2 2
AD29 VCC27 VTT0_27 B14
AD28 B12
VCC28 VTT0_28 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K
AD27 A14
VCC29 VTT0_29
AD26 A13
VCC30 VTT0_30
AC35 A12
VCC31 VTT0_31
AC34 VCC32 VTT0_32 A11
AC33
VCC33
C
AC32
VCC34 (Place these capacitors on CPU cavity, Bottom Layer) C
AC31
VCC35
AC30 VCC36 VTT0_33 AF10
AC29 AE10 +CPU_CORE
VCC37 VTT0_34
AC28 AC10
VCC38 VTT0_35
CPU CORE SUPPLY

AC27 AB10 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M

VCC39 VTT0_36
AC26 Y10
VCC40 VTT0_37
AA35 W10 1 1 1 1 1 1
VCC41 VTT0_38 C105 C106 C107 C108 C109 C110
AA34 U10
VCC42 VTT0_39
AA33 T10
VCC43 VTT0_40
AA32 J12
VCC44 VTT0_41 2 2 2 2 2 2
AA31 J11
VCC45 VTT0_42
AA30 J16
VCC46 VTT0_43 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
AA29 J15
VCC47 VTT0_44
AA28 VCC48
AA27
VCC49
AA26
VCC50 +CPU_CORE
Y35
VCC51
Y34
VCC52 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
Y33
VCC53
Y32
VCC54
Y31 1 1 1 1 1 1
VCC55 C111 C112 C113 C114 C115 C116
Y30
VCC56
Y29 VCC57
Y28
VCC58 2 2 2 2 2 2
Y27
VCC59
Y26
V35
VCC60
AN33 H_PSI# CRB default setting: 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
VCC61 PSI# H_PSI# 54
V34 VID[6:0]=[0100111]
POWER

VCC62
V33
VCC63
V32 AK35 CPU_VID0 CPU_VID0 54
VCC64 VID[0]
V31 AK33 CPU_VID1 CPU_VID1 54
VCC65 VID[1]
V30 AK34 CPU_VID2 CPU_VID2 54
B VCC66 VID[2] CPU_VID3 B
V29 VCC67 VID[3] AL35 CPU_VID3 54 VTT Rail
CPU VIDS

V28 AL33 CPU_VID4 TOP side (under inductor)

VCC68 VID[4] CPU_VID4 54
V27 AM33 CPU_VID5 CPU_VID5 54
VCC69 VID[5]
V26 AM35 CPU_VID6 CPU_VID6 54 Auburndale +1.1VS_VTT=1.05V
VCC70 VID[6] +CPU_CORE
U35 AM34 H_DPRSLPVR_R 1 2
U34
VCC71 PROC_DPRSLPVR R62 0_0402_5%
H_DPRSLPVR 54 Clarksfield +1.1VS_VTT=1.1V
VCC72 330U_D2_2V_Y 330U_D2_2V_Y
U33
VCC73
U32 1 1 1 1
VCC74 H_VTTSELECT
U31 G15 T64 PAD
VCC75 VTT_SELECT + + + +
U30
VCC76 H_VTTSELECT = low, 1.1V C121 C122 C123 C124
U29
VCC77
U28 VCC78 H_VTTSELECT = high, 1.05V 2 2 2 2
U27
VCC79 330U_D2_2V_Y 330U_D2_2V_Y
U26
VCC80
R35
VCC81
R34
VCC82
R33 VCC83
R32 AN35 IMVP_IMON
VCC84 ISENSE IMVP_IMON 54
R31
VCC85
R30 1 2 +CPU_CORE
VCC86 R64 100_0402_1%
R29
VCC87 VCCSENSE_R R65 VCCSENSE
2 0_0402_5%
SENSE LINES

R28 VCC88 VCC_SENSE AJ34 1 VCCSENSE 54

VSSSENSE_R R66 2 0_0402_5% VSSSENSE
R27
R26
VCC89 VSS_SENSE
AJ35 1 VSSSENSE 54 Check list:
VCC90
P35 1 2
VCC91 VTT_SENSE R67 100_0402_1%
P34
P33
VCC92 VTT_SENSE
B15
A15 VSS_SENSE_VTT
VTT_SENSE 51 +CPU_CORE: 6x 470uF, 12x 22uF, 17x 10uF
VCC93 VSS_SENSE_VTT
P32 VCC94 Close to CPU
P31
P30
VCC95 +VTT: 4x 330uF, 7x 22uF, 8x 10uF
VCC96
P29
VCC97
P28
A VCC98 A
P27 VCC99
P26
VCC100

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 200910/9 Deciphered Date 2010/01/23 Title
IC,AUB_CFD_rPGA,R0P9
CONN@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_POWER-1
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Wednesday, April 14, 2010 Sheet 8 of 57
5 4 3 2 1
 5 4 3 2 1

For EMI
PJ30 @
+GFX_CORE 2 1
2 1
JUMP_43X79
47P_0402_50V8J 47P_0402_50V8J PJ31 @
2 1
2 1

1
C279 C280 C281 C272
@ @ @ @ JUMP_43X79

2
D
+1.5V_CPU +1.5V D
47P_0402_50V8J 47P_0402_50V8J Q33
1 8
S D
2 7
S D

2
3 6
R424 S D
1 4 G D 5
Close to CPU 470_0603_5% C179
10U_0805_10V4K FDS6676AS_SO8 R419
+GFX_CORE JCPUG 1 2 +VSB

3 1
2 220K_0402_5%
1 2 +GFX_CORE

6
22U_0805_6.3V6M 1U_0402_6.3V4Z 10U_0805_6.3V6M AT21 R509 100_0402_1%
VAXG1

1
AT19 AR22 VCC_AXG_SENSE_R R117 1 2 0_0402_5% Q46B 1 Q46A
VAXG2 VAXG_SENSE VCC_AXG_SENSE 55
VSS_AXG_SENSE_R R142 1 2 0_0402_5% C476 R418

SENSE
LINES
1 AT18 AT22 VSS_AXG_SENSE 55
VAXG3 VSSAXG_SENSE SUSP 0.1U_0402_25V6 820K_0402_5% SUSP
1 1 1 1 1 1 AT16 5 2 SUSP 46,53
C271 + C249 C266 C247 C286 C250 C248 VAXG4
AR21 1 2
330U_D2_2VM_R6M VAXG5 R510 100_0402_1% 2N7002DW-T/R7_SOT363-6 2 2N7002DW-T/R7_SOT363-6
AR19

1
VAXG6
AR18
2 2 2 2 2 2 2 VAXG7 GFXVR_VID_0
AR16 AM22 GFXVR_VID_0 55
VAXG8 GFX_VID[0] GFXVR_VID_1
22U_0805_6.3V6M 1U_0402_6.3V4Z 10U_0805_6.3V6M
AP21 VAXG9 GFX_VID[1] AP22
GFXVR_VID_2
GFXVR_VID_1 55 For S3 CPU Power Saving

GRAPHICS VIDs
AP19 AN22 GFXVR_VID_2 55
VAXG10 GFX_VID[2]
AP18
VAXG11 GFX_VID[3]
AP23 GFXVR_VID_3
GFXVR_VID_3 55 Change R136 to 330 ohm
AP16 22A AM23 GFXVR_VID_4
AN21
VAXG12 GFX_VID[4]
AP24 GFXVR_VID_5
GFXVR_VID_4 55 for GFX issue
VAXG13 GFX_VID[5] GFXVR_VID_5 55

GRAPHICS
AN19 AN24 GFXVR_VID_6
VAXG14 GFX_VID[6] GFXVR_VID_6 55
AN18
VAXG15 GFXVR_EN
AN16 1 2
VAXG16 R136 330_0402_5%
AM21 AR25 GFXVR_EN 55
VAXG17 GFX_VR_EN GFXVR_DPRSLPVR
AM19 AT25 T54 PAD
VAXG18 GFX_DPRSLPVR GFXVR_IMON
AM18 AM24 GFXVR_IMON 55
C VAXG19 GFX_IMON C
AM16
VAXG20
AL21
VAXG21
AL19 VAXG22
AL18
VAXG23
AL16
VAXG24 1U_0402_6.3V4Z 1U_0402_6.3V4Z 22U_0805_6.3V6M
AK21 AJ1 +1.5V_CPU
VAXG25 VDDQ1
AK19 AF1 1
VAXG26 VDDQ2
AK18 AE7 1 1 1 1 1 1 1

- 1.5V RAILS
VAXG27 VDDQ3 + C216
AK16
VAXG28 Clarksfield: 5A VDDQ4
AE4
C133 C134 C135 C136 C137 C138 C139
AJ21 AC1
VAXG29 VDDQ5
AJ19
VAXG30 Auburndale:3A VDDQ6
AB7
2 2 2 2 2 2 2 2
330U_D2_2V_Y +1.5V
AJ18 VAXG31 VDDQ7 AB4
AJ16 Y1
VAXG32 VDDQ8
AH21 W7
VAXG33 VDDQ9

POWER
AH19 W4 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 22U_0805_6.3V6M
VAXG34 VDDQ10
AH18 U1
VAXG35 VDDQ11

0.1U_0402_16V4Z
AH16 VAXG36 VDDQ12 T7
T4 @ 1
VDDQ13
P1
+VTT VDDQ14

C257
N7
VDDQ15
N4
VDDQ16 2

DDR3
L1
VDDQ17
J24 H1
VTT1_45 VDDQ18
FDI

J23
VTT1_46 +VTT
1 1 H25 VTT1_47
C141 C142
(Place these capacitors under CPU socket Edge, top layer)
22U_0805_6.3V6M 22U_0805_6.3V6M P10 1
2 2 VTT0_59 C143
VTT0_60 N10
B B
L10
VTT0_61 10U_0805_10V4K
K10
VTT0_62 2
Clarksfield: 21A
+VTT
+VTT Auburndale:18A
1.1V

J22
VTT1_63
K26 J20
VTT1_48 VTT1_64
J27 J18 1
VTT1_49 VTT1_65
PEG & DMI

1 1 J26 H21 C145

C146 C147 VTT1_50 VTT1_66
J25 H20
VTT1_51 VTT1_67 22U_0805_6.3V6M
H27 H19
22U_0805_6.3V6M 22U_0805_6.3V6M VTT1_52 VTT1_68 2
G28 VTT1_53
2 2
G27
VTT1_54 (Place these capacitors under CPU socket, top layer)
G26
VTT1_55 +1.8VS
F26
VTT1_56
E26 L26
VTT1_57 VCCPLL1
1.8V

E25 VTT1_58 VCCPLL2 L27

M26 +1.8VS_H_PLL 1U_0402_6.3V4Z 4.7U_0603_6.3V6K 2 1
VCCPLL3 R71 0_0805_5%
1 1 1 1
(Place these capacitors under CPU socket, top layer) Clarksfield: 1.35A C151 C152 C153 C154 C155
Auburndale:1.35A 1U_0402_6.3V4Z
2 2 2 2 22U_0805_6.3V6M

IC,AUB_CFD_rPGA,R0P9 CONN@ 2.2U_0603_6.3V4Z

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_POWER-2
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Wednesday, April 14, 2010 Sheet 9 of 57
5 4 3 2 1
 5 4 3 2 1

JCPUI JCPUH JCPUE

AT20 VSS1 VSS81 AE34 RSVD32 AJ13

AT17 VSS2 VSS82 AE33 RSVD33 AJ12
K27 VSS161 AR31 VSS3 VSS83 AE32
K9 VSS162 AR28 VSS4 VSS84 AE31 AP25 RSVD1
K6 VSS163 AR26 VSS5 VSS85 AE30 AL25 RSVD2 RSVD34 AH25
D K3 VSS164 AR24 VSS6 VSS86 AE29 AL24 RSVD3 RSVD35 AK26 D
J32 VSS165 AR23 VSS7 VSS87 AE28 AL22 RSVD4
J30 VSS166 AR20 VSS8 VSS88 AE27 AJ33 RSVD5 RSVD36 AL26
J21 VSS167 AR17 VSS9 VSS89 AE26 AG9 RSVD6 RSVD_NCTF_37 AR2
J19 VSS168 AR15 VSS10 VSS90 AE6 M27 RSVD7
H35 VSS169 AR12 VSS11 VSS91 AD10 L28 RSVD8 RSVD38 AJ26
H32 VSS170 AR9 VSS12 VSS92 AC8 T9 PAD J17 RSVD9 (SA_DIMM_VREF) RSVD39 AJ27
H28 VSS171 AR6 VSS13 VSS93 AC4 T8 PAD H17 RSVD10(SB_DIMM_VREF)
H26 VSS172 AR3 VSS14 VSS94 AC2 G25 RSVD11
H24 VSS173 AP20 VSS15 VSS95 AB35 G17 RSVD12
H22 VSS174 AP17 VSS16 VSS96 AB34 E31 RSVD13 RSVD_NCTF_40 AP1
H18 VSS175 AP13 VSS17 VSS97 AB33 E30 RSVD14 RSVD_NCTF_41 AT2
H15 VSS176 AP10 VSS18 VSS98 AB32
H13 VSS177 AP7 VSS19 VSS99 AB31 RSVD_NCTF_42 AT3
H11 VSS178 AP4 VSS20 VSS100 AB30 RSVD_NCTF_43 AR1
H8 VSS179 AP2 VSS21 VSS101 AB29 WW41 Recommend not pull down
H5 VSS180 AN34 VSS22 VSS102 AB28 PCIE2.0 Jitter is over on ES1
H2 VSS181 AN31 VSS23 VSS103 AB27
G34 VSS182 AN23 VSS24 VSS104 AB26 RSVD45 AL28
G31 AN20 AB6 3.01K_0402_1% 1 @ R74 2 CFG0 AM30 AL29
VSS183 VSS25 VSS105 CFG1 CFG[0] RSVD46
G20 VSS184 AN17 VSS26 VSS106 AA10 AM28 CFG[1] RSVD47 AP30
G9 AM29 Y8 CFG2 AP31 AP32
VSS185 VSS27 VSS107 3.01K_0402_1% 1 R75 CFG3 CFG[2] RSVD48
G6 VSS186 AM27 VSS28 VSS108 Y4 2 AL32 CFG[3] RSVD49 AL27
G3 AM25 Y2 3.01K_0402_1% 1 @ R76 2 CFG4 AL30 AT31
VSS187 VSS29 VSS109 CFG5 CFG[4] RSVD50
F30 VSS188 AM20 VSS30 VSS110 W35 AM31 CFG[5] RSVD51 AT32
F27 AM17 W34 CFG6 AN29 AP33
VSS189 VSS31 VSS111 CFG7 CFG[6] RSVD52
F25 VSS190 AM14 VSS32 VSS112 W33 AM32 CFG[7] RSVD53 AR33
F22 AM11 W32 CFG8 AK32 AT33
VSS191 VSS33 VSS113 CFG9 CFG[8] RSVD_NCTF_54
F19 AM8 W31 AK31 AT34

RESERVED
C VSS192 VSS34 VSS114 CFG10 CFG[9] RSVD_NCTF_55 C
F16 VSS193 AM5 VSS35 VSS115 W30 AK28 CFG[10] RSVD_NCTF_56 AP35
E35 AM2 W29 CFG11 AJ28 AR35
VSS194 VSS36 VSS116 CFG[11] RSVD_NCTF_57
E32 AL34 W28 AN30 AR32
E29
E24
VSS195
VSS196
VSS197
VSS AL31
AL23
VSS37
VSS38
VSS39
VSS VSS117
VSS118
VSS119
W27
W26
CFG13
CFG14
AN32
AJ32
CFG[12]
CFG[13]
CFG[14]
RSVD58

E21 AL20 W6 CFG15 AJ29 E15

VSS198 VSS40 VSS120 CFG16 CFG[15] RSVD_TP_59
E18 VSS199 AL17 VSS41 VSS121 V10 AJ30 CFG[16] RSVD_TP_60 F15
E13 AL12 U8 CFG17 AK30 A2
VSS200 VSS42 VSS122 CFG18 CFG[17] KEY
E11 VSS201 AL9 VSS43 VSS123 U4 H16 RSVD_TP_86 RSVD62 D15
E8 VSS202 AL6 VSS44 VSS124 U2 RSVD63 C15
E5
E2
VSS203
AT35 H_NCTF1 PAD T4
AL3
AK29
VSS45 VSS125 T35
T34
Reserve via for test RSVD64 AJ15
AH15
VSS204 VSS_NCTF1 H_NCTF2 VSS46 VSS126 RSVD65
D33 VSS205 VSS_NCTF2 AT1 PAD T5 AK27 VSS47 VSS127 T33
D30 VSS206 VSS_NCTF3 AR34 AK25 VSS48 VSS128 T32 B19 RSVD15
D26 VSS207 VSS_NCTF4 B34 AK20 VSS49 VSS129 T31 A19 RSVD16
D9 B2 AK17 T30
NCTF

VSS208 VSS_NCTF5 H_NCTF6 VSS50 VSS130

D6 VSS209 VSS_NCTF6 B1 PAD T6 AJ31 VSS51 VSS131 T29 A20 RSVD17
D3 A35 H_NCTF7 PAD T7 AJ23 T28 B20
VSS210 VSS_NCTF7 VSS52 VSS132 RSVD18
C34 VSS211 AJ20 VSS53 VSS133 T27 RSVD_TP_66 AA5
C32 VSS212 AJ17 VSS54 VSS134 T26 U9 RSVD19 RSVD_TP_67 AA4
C29 VSS213 AJ14 VSS55 VSS135 T6 T9 RSVD20 RSVD_TP_68 R8
C28 VSS214 AJ11 VSS56 VSS136 R10 RSVD_TP_69 AD3
C24 VSS215 AJ8 VSS57 VSS137 P8 AC9 RSVD21 RSVD_TP_70 AD2
C22 VSS216 AJ5 VSS58 VSS138 P4 AB9 RSVD22 RSVD_TP_71 AA2
C20 VSS217 AJ2 VSS59 VSS139 P2 CFG0 - PCI-Express Configuration Select RSVD_TP_72 AA1
C19 VSS218 AH35 VSS60 VSS140 N35 RSVD_TP_73 R9
C16 VSS219 AH34 VSS61 VSS141 N34 RSVD_TP_74 AG7
B31 VSS220 AH33 VSS62 VSS142 N33 *1:Single PEG C1 RSVD_NCTF_23 RSVD_TP_75 AE3
B
B25 VSS221 AH32 VSS63 VSS143 N32 0:Bifurcation enabled A3 RSVD_NCTF_24 B
B21 VSS222 AH31 VSS64 VSS144 N31
B18 VSS223 AH30 VSS65 VSS145 N30 RSVD_TP_76 V4
B17 VSS224 AH29 VSS66 VSS146 N29 RSVD_TP_77 V5
B13 VSS225 AH28 VSS67 VSS147 N28 RSVD_TP_78 N2
B11 VSS226 AH27 VSS68 VSS148 N27 CFG3 - PCI-Express Static Lane Reversal J29 RSVD26 RSVD_TP_79 AD5
B8 VSS227 AH26 VSS69 VSS149 N26 J28 RSVD27 RSVD_TP_80 AD7
B6 VSS228 AH20 VSS70 VSS150 N6 RSVD_TP_81 W3
B4 AH17 M10 *1 :Normal Operation A34 W2
VSS229 VSS71 VSS151 RSVD_NCTF_28 RSVD_TP_82
A29 VSS230 AH13 VSS72 VSS152 L35 0 :Lane Numbers Reversed A33 RSVD_NCTF_29 RSVD_TP_83 N3
A27 VSS231 AH9 VSS73 VSS153 L32 15 -> 0, 14 -> 1, ... RSVD_TP_84 AE5
A23 VSS232 AH6 VSS74 VSS154 L29 C35 RSVD_NCTF_30 RSVD_TP_85 AD9
A9 VSS233 AH3 VSS75 VSS155 L8 B35 RSVD_NCTF_31
AG10 VSS76 VSS156 L5
AF8 VSS77 VSS157 L2 VSS AP34
AF4 VSS78 VSS158 K34 CFG4 - Display Port Presence
AF2 VSS79 VSS159 K33
AE35 VSS80 VSS160 K30
*1:Disabled; No Physical Display Port
attached to Embedded Display Port IC,AUB_CFD_rPGA,R0P9
0:Enabled; An external Display Port CONN@

IC,AUB_CFD_rPGA,R0P9 CONN@ IC,AUB_CFD_rPGA,R0P9 CONN@

device is connected to the Embedded
Display Port

*:Default

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_GND/RESERVED
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Wednesday, March 24, 2010 Sheet 10 of 57
5 4 3 2 1
 5 4 3 2 1

+1.5V +1.5V
JDIMM1
+VREF_DQA 1
3
VREF_DQ
VSS2
VSS1
DQ4
2
4 DDR_A_D4
DDR_A_DQS[0..7] 7 M1@: Arrandale
DDR_A_D0 DDR_A_D5 +1.5V
5 6

0.1U_0402_16V4Z

2.2U_0603_6.3V4Z
DQ0 DQ5 DDR_A_DQS#[0..7] 7
1 1 DDR_A_D1 7 8
DQ1 VSS3 DDR_A_DQS#0
9 VSS4 DQS#0 10 DDR_A_D[0..63] 7

1
+1.5V
C156

C157
DDR_A_DM0 11 12 DDR_A_DQS0 +VREF_DQA 2 1
DM0 DQS0 0_0402_5% R92 +V_DDR3_DIMM_REF R79
13 VSS5 VSS6 14 DDR_A_DM[0..7] 7
2 2 DDR_A_D2 DDR_A_D6 1K_0402_1%
15 DQ2 DQ6 16

1
DDR_A_D3 17 18 DDR_A_D7 DDR_A_MA[0..15] 7
DQ3 DQ7 R80
19 20

2
DDR_A_D8 VSS7 VSS8 DDR_A_D12 1K_0402_1%
21 DQ8 DQ12 22
D DDR_A_D9 23 24 DDR_A_D13 D
DQ9 DQ13

1
Close to JDDRL.1 25 26

2
DDR_A_DQS#1 VSS9 VSS10 DDR_A_DM1 R81
DDR_A_DQS1
27
29
DQS#1 DM1 28
30 SM_DRAMRST#
For S3 CPU Power Saving 2 1 1K_0402_1%
DQS1 RESET# SM_DRAMRST# 5,12 +VREF_DQB
31 32 0_0402_5% R93
DDR_A_D10 VSS11 VSS12 DDR_A_D14
33 34

2
DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 DQ11 DQ15 36
37 VSS13 VSS14 38
DDR_A_D16 39 40 DDR_A_D20
DDR_A_D17 DQ16 DQ20 DDR_A_D21
41 DQ17 DQ21 42
43 VSS15 VSS16 44
DDR_A_DQS#2 45 46 DDR_A_DM2
DDR_A_DQS2 DQS#2 DM2
47 DQS2 VSS17 48
49 50 DDR_A_D22
DDR_A_D18 VSS18 DQ22 DDR_A_D23
51 DQ18 DQ23 52
DDR_A_D19 53 54
DQ19 VSS19 DDR_A_D28
55 VSS20 DQ28 56
DDR_A_D24 57 58 DDR_A_D29
DDR_A_D25 DQ24 DQ29
59 DQ25 VSS21 60
61 62 DDR_A_DQS#3
DDR_A_DM3 VSS22 DQS#3 DDR_A_DQS3
63 DM3 DQS3 64
65 VSS23 VSS24 66
DDR_A_D26 67 68 DDR_A_D30
DDR_A_D27 DQ26 DQ30 DDR_A_D31
69 DQ27 DQ31 70
71 VSS25 VSS26 72

DDRA_CKE0 73 74 DDRA_CKE1
C
7 DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 7 C
75 VDD1 VDD2 76
77 78 DDR_A_MA15
DDR_A_BS2 NC1 A15 DDR_A_MA14
7 DDR_A_BS2 79 BA2 A14 80
81 VDD3 VDD4 82
DDR_A_MA12 83 84 DDR_A_MA11
DDR_A_MA9 A12/BC# A11 DDR_A_MA7
85 A9 A7 86
87 VDD5 VDD6 88
DDR_A_MA8 89 90 DDR_A_MA6
DDR_A_MA5 A8 A6 DDR_A_MA4
91 A5 A4 92
93 VDD7 VDD8 94
DDR_A_MA3 95 96 DDR_A_MA2
DDR_A_MA1 A3 A2 DDR_A_MA0
97 A1 A0 98
99 VDD9 VDD10 100
DDRA_CLK0 101 102 DDRA_CLK1
7 DDRA_CLK0 CK0 CK1 DDRA_CLK1 7
DDRA_CLK0# 103 104 DDRA_CLK1#
7 DDRA_CLK0# CK0# CK1# DDRA_CLK1# 7
105 VDD11 VDD12 106
DDR_A_MA10 107 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 7
DDR_A_BS0 109 110 DDR_A_RAS#
7 DDR_A_BS0 BA0 RAS# DDR_A_RAS# 7
111 VDD13 VDD14 112
DDR_A_WE# 113 114 DDRA_SCS0#
7 DDR_A_WE# WE# S0# DDRA_SCS0# 7
DDR_A_CAS# 115 116 DDRA_ODT0
7 DDR_A_CAS# CAS# ODT0 DDRA_ODT0 7 +V_DDR3_DIMM_REF
117 VDD15 VDD16 118
DDR_A_MA13 119 120 DDRA_ODT1
A13 ODT1 DDRA_ODT1 7
DDRA_SCS1# 121 122
7 DDRA_SCS1# S1# NC2 R89
123 VDD17 VDD18 124
125 126 +DDR_VREF_CA_DIMMA 1 2
NCTEST VREF_CA 0_0402_5%
127 VSS27 VSS28 128
DDR_A_D32 129 130 DDR_A_D36
DDR_A_D33 DQ32 DQ36 DDR_A_D37
131 132
0.1U_0402_16V4Z
2.2U_0603_6.3V4Z

B DQ33 DQ37 B
133 VSS29 VSS30 134
DDR_A_DQS#4 135 136 DDR_A_DM4 Layout Note: Layout Note: Place these 4 Caps near Layout Note:
DDR_A_DQS4 DQS#4 DM4
137 DQS4 VSS31 138 1 1
139 140 DDR_A_D38 Place near JDDRL Command and Control signals of DIMMA Place near JDDRL1.203 and 204
VSS32 DQ38
C161

C162

DDR_A_D34 141 142 DDR_A_D39

DDR_A_D35 DQ34 DQ39
143 DQ35 VSS33 144
DDR_A_D44 2 2 +1.5V
145 VSS34 DQ44 146 C218
DDR_A_D40 147 148 DDR_A_D45 +1.5V +0.75VS
DDR_A_D41 DQ40 DQ45
149 DQ41 VSS35 150 1 2
151 152 DDR_A_DQS#5

+
DDR_A_DM5 VSS36 DQS#5 DDR_A_DQS5 C164 1
153 DM5 DQS5 154 close to JDDRL.126 2 0.1U_0402_16V4Z C165 1 2 10U_0805_6.3V6M
155 156 C166 1330U_D2_2V_Y
2 10U_0805_6.3V6M
DDR_A_D42 VSS37 VSS38 DDR_A_D46 C167 1
157 DQ42 DQ46 158 2 0.1U_0402_16V4Z
DDR_A_D43 159 160 DDR_A_D47 C168 1 2 10U_0805_6.3V6M C169 2 1 1U_0402_6.3V4Z
DQ43 DQ47 C170 1
161 VSS39 VSS40 162 2 0.1U_0402_16V4Z
DDR_A_D48 163 164 DDR_A_D52 C171 1 2 10U_0805_6.3V6M C172 2 1 1U_0402_6.3V4Z
DDR_A_D49 DQ48 DQ52 DDR_A_D53 C173 1
165 DQ49 DQ53 166 2 0.1U_0402_16V4Z
167 168 C174 1 2 10U_0805_6.3V6M C175 2 1 1U_0402_6.3V4Z
DDR_A_DQS#6 VSS41 VSS42 DDR_A_DM6
169 DQS#6 DM6 170
DDR_A_DQS6 171 172 C176 1 2 10U_0805_6.3V6M C177 2 1 1U_0402_6.3V4Z
DQS6 VSS43 DDR_A_D54
173 VSS44 DQ54 174
DDR_A_D50 175 176 DDR_A_D55 C178 1 2 10U_0805_6.3V6M
DDR_A_D51 DQ50 DQ55
177 DQ51 VSS45 178
179 180 DDR_A_D60
DDR_A_D56 VSS46 DQ60 DDR_A_D61
181 DQ56 DQ61 182
DDR_A_D57 183 184
DQ57 VSS47 DDR_A_DQS#7
185 VSS48 DQS#7 186
DDR_A_DM7 187 188 DDR_A_DQS7
DM7 DQS7
A 189 VSS49 VSS50 190 A
DDR_A_D58 191 192 DDR_A_D62 PM_EXTTS#
DQ58 DQ62 PM_EXTTS# 5,12
DDR_A_D59 193 194 DDR_A_D63 PM_SMBDATA
DQ59 DQ63 PM_SMBDATA 12,25,29,39
R90 1 2 195 196 PM_SMBCLK
VSS51 VSS52 PM_SMBCLK 12,25,29,39
10K_0402_5% 197 198 PM_EXTTS#
SA0 EVENT# PM_SMBDATA
+3VS 199 VDDSPD SDA 200
201 202 PM_SMBCLK
Compal Electronics, Inc.
0.1U_0402_16V4Z

Compal Secret Data

2.2U_0603_6.3V4Z

SA1 SCL Security Classification

10K_0402_5%

1 1 +0.75VS 203 VTT1 VTT2 204 +0.75VS

1

C182 200910/9 2010/01/23 Title

Issued Date Deciphered Date
C181 205 206
G1 G2 DDRIII-SODIMM0
R91

2 2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TYCO_2-2013289-1 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
CONN@ DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NCL60/61 LA-6321P M/B
2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 14, 2010 Sheet 11 of 57
5 4 3 2 1
 A B C D E

+1.5V +1.5V
JDIMM2
+VREF_DQB 1 VREF_DQ VSS1 2
3 4 DDR_B_D4
DDR_B_D0 VSS2 DQ4 DDR_B_D5
5 DQ0 DQ5 6
DDR_B_D1 7 8
DQ1 VSS3 DDR_B_DQS#0
9 10

0.1U_0402_16V4Z
2.2U_0603_6.3V4Z
DDR_B_DM0 VSS4 DQS#0 DDR_B_DQS0
11 DM0 DQS0 12
1 1 13 VSS5 VSS6 14
DDR_B_D2 15 16 DDR_B_D6
DDR_B_D3 DQ2 DQ6 DDR_B_D7
17 DQ3 DQ7 18
C183

C184
19 VSS7 VSS8 20
2 2 DDR_B_D8 DDR_B_D12
21 DQ8 DQ12 22
1 DDR_B_D9 23 24 DDR_B_D13 1
DQ9 DQ13
25 VSS9 VSS10 26
DDR_B_DQS#1 27 28 DDR_B_DM1
DDR_B_DQS1 DQS#1 DM1 SM_DRAMRST#
29 DQS1 RESET# 30 SM_DRAMRST# 5,11
31 VSS11 VSS12 32 DDR_B_DQS#[0..7] 7
DDR_B_D10 33 34 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
close to JDDRH.1 35 DQ11 DQ15 36 DDR_B_DQS[0..7] 7
37 VSS13 VSS14 38
DDR_B_D16 39 40 DDR_B_D20 DDR_B_D[0..63] 7
DDR_B_D17 DQ16 DQ20 DDR_B_D21
41 DQ17 DQ21 42
43 VSS15 VSS16 44 DDR_B_DM[0..7] 7
DDR_B_DQS#2 45 46 DDR_B_DM2
DDR_B_DQS2 DQS#2 DM2
47 DQS2 VSS17 48 DDR_B_MA[0..15] 7
49 50 DDR_B_D22
DDR_B_D18 VSS18 DQ22 DDR_B_D23
51 DQ18 DQ23 52
DDR_B_D19 53 54
DQ19 VSS19 DDR_B_D28
55 VSS20 DQ28 56
DDR_B_D24 57 58 DDR_B_D29
DDR_B_D25 DQ24 DQ29
59 DQ25 VSS21 60
61 62 DDR_B_DQS#3
DDR_B_DM3 VSS22 DQS#3 DDR_B_DQS3
63 DM3 DQS3 64
65 VSS23 VSS24 66
DDR_B_D26 67 68 DDR_B_D30
DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 DQ27 DQ31 70
71 VSS25 VSS26 72

DDRB_CKE0 73 74 DDRB_CKE1
2
7 DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 7 2
75 VDD1 VDD2 76
77 78 DDR_B_MA15
DDR_B_BS2 NC1 A15 DDR_B_MA14
7 DDR_B_BS2 79 BA2 A14 80
81 VDD3 VDD4 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 A9 A7 86
87 VDD5 VDD6 88
DDR_B_MA8 89 90 DDR_B_MA6
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
93 VDD7 VDD8 94
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 VDD9 VDD10 100
DDRB_CLK0 101 102 DDRB_CLK1
7 DDRB_CLK0 CK0 CK1 DDRB_CLK1 7
DDRB_CLK0# 103 104 DDRB_CLK1#
7 DDRB_CLK0# CK0# CK1# DDRB_CLK1# 7
105 VDD11 VDD12 106
DDR_B_MA10 107 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 7
DDR_B_BS0 109 110 DDR_B_RAS#
7 DDR_B_BS0 BA0 RAS# DDR_B_RAS# 7
111 VDD13 VDD14 112
DDR_B_WE# 113 114 DDRB_SCS0#
7 DDR_B_WE# WE# S0# DDRB_SCS0# 7
DDR_B_CAS# 115 116 DDRB_ODT0
7 DDR_B_CAS# CAS# ODT0 DDRB_ODT0 7
117 VDD15 VDD16 118
DDR_B_MA13 DDRB_ODT1 +V_DDR3_DIMM_REF
119 A13 ODT1 120 DDRB_ODT1 7
DDRB_SCS1# 121 122
7 DDRB_SCS1# S1# NC2 R97
123 VDD17 VDD18 124
+DDR_VREF_CA_DIMMB
Layout Note: Layout Note: Place these 4 Caps near Layout Note:
125 NCTEST VREF_CA 126 1 2
127 128 0_0402_5% Place near JDDRH Command and Control signals of DIMMB Place near JDDRH.203 and 204
DDR_B_D32 VSS27 VSS28 DDR_B_D36
129 DQ32 DQ36 130
DDR_B_D33 131 132 DDR_B_D37
0.1U_0402_16V4Z
2.2U_0603_6.3V4Z

3 DQ33 DQ37 +1.5V 3

133 VSS29 VSS30 134
DDR_B_DQS#4 135 136 DDR_B_DM4 @ +1.5V +0.75VS
DQS#4 DM4 1 1
DDR_B_DQS4 C189 1 2 330U_B2_2.5VM_R15M

+
137 DQS4 VSS31 138
139 140 DDR_B_D38
VSS32 DQ38
C187

C188

DDR_B_D34 141 142 DDR_B_D39 C190 1 2 0.1U_0402_16V4Z C191 1 2 10U_0805_6.3V6M

DDR_B_D35 DQ34 DQ39 2 2 C192 1
143 DQ35 VSS33 144 2 10U_0805_6.3V6M
145 146 DDR_B_D44 C193 1 2 0.1U_0402_16V4Z
DDR_B_D40 VSS34 DQ44 DDR_B_D45 C194 1
147 DQ40 DQ45 148 2 10U_0805_6.3V6M C195 2 1 1U_0402_6.3V4Z
DDR_B_D41 149 150 C196 1 2 0.1U_0402_16V4Z
DQ41 VSS35 DDR_B_DQS#5 C197 1
151 VSS36 DQS#5 152 2 10U_0805_6.3V6M C198 2 1 1U_0402_6.3V4Z
DDR_B_DM5 153 154 DDR_B_DQS5 C199 1 2 0.1U_0402_16V4Z
DM5 DQS5 C200 1
155 VSS37 VSS38 156 close to JDDRH.126 2 10U_0805_6.3V6M C201 2 1 1U_0402_6.3V4Z
DDR_B_D42 157 158 DDR_B_D46
DDR_B_D43 DQ42 DQ46 DDR_B_D47 C202 1
159 DQ43 DQ47 160 2 10U_0805_6.3V6M C203 2 1 1U_0402_6.3V4Z
161 VSS39 VSS40 162
DDR_B_D48 163 164 DDR_B_D52 C204 1 2 10U_0805_6.3V6M
DDR_B_D49 DQ48 DQ52 DDR_B_D53
165 DQ49 DQ53 166
167 VSS41 VSS42 168
DDR_B_DQS#6 169 170 DDR_B_DM6
DDR_B_DQS6 DQS#6 DM6
171 DQS6 VSS43 172
173 174 DDR_B_D54
DDR_B_D50 VSS44 DQ54 DDR_B_D55
175 DQ50 DQ55 176
DDR_B_D51 177 178
DQ51 VSS45 DDR_B_D60
179 VSS46 DQ60 180
DDR_B_D56 181 182 DDR_B_D61
DDR_B_D57 DQ56 DQ61
183 DQ57 VSS47 184
185 186 DDR_B_DQS#7
DDR_B_DM7 VSS48 DQS#7 DDR_B_DQS7
187 DM7 DQS7 188
4 189 VSS49 VSS50 190 4
DDR_B_D58 191 192 DDR_B_D62
DDR_B_D59 DQ58 DQ62 DDR_B_D63
193 DQ59 DQ63 194
R98 1 2 195 196
10K_0402_5% VSS51 VSS52 PM_EXTTS#
197 SA0 EVENT# 198 PM_EXTTS# 5,11
199 200 PM_SMBDATA
+3VS VDDSPD SDA PM_SMBDATA 11,25,29,39
201 202 PM_SMBCLK
2.2U_0603_6.3V4Z
1 1 1 R99 2 +0.75VS 203
SA1 SCL
204 +0.75VS
PM_SMBCLK Security Classification
11,25,29,39 Compal Secret Data Compal Electronics, Inc.
10K_0402_5% VTT1 VTT2
Issued Date 200910/9 Deciphered Date 2010/01/23 Title
205 206
C207 C208 G1 G2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM1
2 2 TYCO_2-2013310-1_204P Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1U_0402_16V4Z CONN@ Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Wednesday, April 14, 2010 Sheet 12 of 57
A B C D E
 5 4 3 2 1

UV1A
PCIE_GTX_C_CRX_P[0..15]
PCIE_CTX_C_GRX_P0 6 PCIE_GTX_C_CRX_P[0..15]
150mA AP17 Part 1 of 7 K1
LV1 OPT@ PCIE_CTX_C_GRX_N0 PEX_RX0 GPIO0
AN17 PEX_RX0_N GPIO1 K2
1 2 0.1U_0402_16V4Z +PLLVDD PCIE_CTX_C_GRX_P1 AN19 K3 VGA_BL_PWM PCIE_GTX_C_CRX_N[0..15]
+1.05VS_DGPU PEX_RX1 GPIO2 6 PCIE_GTX_C_CRX_N[0..15]
100NH_LQW18ANR10J00D_5%_0603 PCIE_CTX_C_GRX_N1 AP19 H3 VGA_ENVDD
PCIE_CTX_C_GRX_P2 PEX_RX1_N GPIO3 VGA_ENBKL
1 1 1 1 AR19 H2
CV9 CV11 CV12 PCIE_CTX_C_GRX_N2 PEX_RX2 GPIO4 GPU_VID0 PCIE_CTX_C_GRX_P[0..15]
AR20 PEX_RX2_N GPIO5 H1 GPU_VID0 56 6 PCIE_CTX_C_GRX_P[0..15]
4.7U_0603_6.3V6K CV10 OPT@ OPT@ PCIE_CTX_C_GRX_P3 AP20 H4 GPU_VID1
PEX_RX3 GPIO6 GPU_VID1 56
OPT@ OPT@ 0.1U_0402_16V4Z PCIE_CTX_C_GRX_N3 AN20 H5
2 2 2 2 PCIE_CTX_C_GRX_P4 PEX_RX3_N GPIO7 PCIE_CTX_C_GRX_N[0..15]
AN22 H6 6 PCIE_CTX_C_GRX_N[0..15]
PCIE_CTX_C_GRX_N4 PEX_RX4 GPIO8 THERM#_VGA
AP22 J7 THERM#_VGA 14
1U_0402_6.3V4Z PCIE_CTX_C_GRX_P5 PEX_RX4_N GPIO9
AR22 PEX_RX5 GPIO10 K4
PCIE_CTX_C_GRX_N5 AR23 K5
PCIE_CTX_C_GRX_P6 PEX_RX5_N GPIO11
AP23 H7

GPIO
D PCIE_CTX_C_GRX_N6 PEX_RX6 GPIO12 TV1 D
AN23 J4 TV6
PCIE_CTX_C_GRX_P7 PEX_RX6_N GPIO13
LV2 OPT@
50mA PCIE_CTX_C_GRX_N7
AN25
PEX_RX7 GPIO14
J6
AP25 PEX_RX7_N GPIO15 L1
1 2 +SP_PLLVDD PCIE_CTX_C_GRX_P8 AR25 L2
+1.05VS_DGPU PEX_RX8 GPIO16
100NH_LQW18ANR10J00D_5%_0603 PCIE_CTX_C_GRX_N8 AR26 L4
PCIE_CTX_C_GRX_P9 PEX_RX8_N GPIO17 VGA_ENVDD
1 1 AP26 M4 1 @ 2
CV7 CV8 PCIE_CTX_C_GRX_N9 PEX_RX9 GPIO18 RV1 10K_0402_5%
AN26 L7
OPT@ OPT@ PCIE_CTX_C_GRX_P10 PEX_RX9_N GPIO19 VGA_ENBKL
AN28 L5 2 @ 1
1U_0402_6.3V4Z 4.7U_0603_6.3V6K PCIE_CTX_C_GRX_N10 PEX_RX10 GPIO20 RV2 10K_0402_5%
AP28 PEX_RX10_N GPIO21 K6
2 2 PCIE_CTX_C_GRX_P11 VGA_BL_PWM
AR28 L6 2 @ 1
PCIE_CTX_C_GRX_N11 PEX_RX11 GPIO22 RV3 10K_0402_5%
AR29 M6
PCIE_CTX_C_GRX_P12 PEX_RX11_N GPIO23
AP29
PCIE_CTX_C_GRX_N12 PEX_RX12
AN29
PCIE_CTX_C_GRX_P13 PEX_RX12_N
AN31 N1
PCIE_CTX_C_GRX_N13 PEX_RX13 MIOA_D0
AP31 PEX_RX13_N MIOA_D1 P4
PCIE_CTX_C_GRX_P14 AR31 P1
PCIE_CTX_C_GRX_N14 PEX_RX14 MIOA_D2
AR32 P2
PCIE_CTX_C_GRX_P15 PEX_RX14_N MIOA_D3
AR34 P3
PCIE_CTX_C_GRX_N15 PEX_RX15 MIOA_D4
AP34 T3
PEX_RX15_N MIOA_D5
MIOA_D6 T2
T1 +3VS_DGPU

PCI EXPRESS
PCIE_GTX_C_CRX_P0 CV13 OPT@ 0.1U_0402_16V7K PCIE_GTX_CRX_P0 MIOA_D7
1 2 AL17 U4
PCIE_GTX_C_CRX_N0 CV14 OPT@ 0.1U_0402_16V7K PCIE_GTX_CRX_N0 PEX_TX0 MIOA_D8
1 2 AM17 U1
PCIE_GTX_C_CRX_P1 CV15 OPT@ 0.1U_0402_16V7K PCIE_GTX_CRX_P1 PEX_TX0_N MIOA_D9
1 2 AM18 U2
PCIE_GTX_C_CRX_N1 CV16 OPT@ 0.1U_0402_16V7K PCIE_GTX_CRX_N1 PEX_TX1 MIOA_D10
1 2 AM19 PEX_TX1_N MIOA_D11 U3
PCIE_GTX_C_CRX_P2 CV17 OPT@ 1 2 0.1U_0402_16V7K PCIE_GTX_CRX_P2 AL19 R6
PCIE_GTX_C_CRX_N2 CV18 OPT@ 0.1U_0402_16V7K PCIE_GTX_CRX_N2 PEX_TX2 MIOA_D12
1 2 AK19 T6

DVO
PCIE_GTX_C_CRX_P3 CV19 OPT@ 0.1U_0402_16V7K PCIE_GTX_CRX_P3 PEX_TX2_N MIOA_D13
1 2 AL20 N6
PCIE_GTX_C_CRX_N3 CV20 OPT@ 0.1U_0402_16V7K PCIE_GTX_CRX_N3 PEX_TX3 MIOA_D14 SMB_CLK_GPU
1 2 AM20 1 OPT@ 2
PCIE_GTX_C_CRX_P4 CV21 OPT@ 0.1U_0402_16V7K PCIE_GTX_CRX_P4 PEX_TX3_N RV8 2.2K_0402_5%
1 2 AM21 PEX_TX4 MIOB_D0 Y1
PCIE_GTX_C_CRX_N4 CV22 OPT@ 1 2 0.1U_0402_16V7K PCIE_GTX_CRX_N4 AM22 Y2 SMB_DATA_GPU 1 OPT@ 2
PCIE_GTX_C_CRX_P5 CV23 OPT@ 0.1U_0402_16V7K PCIE_GTX_CRX_P5 PEX_TX4_N MIOB_D1 RV9 2.2K_0402_5%
1 2 AL22 Y3
C PCIE_GTX_C_CRX_N5 CV24 OPT@ 0.1U_0402_16V7K PCIE_GTX_CRX_N5 PEX_TX5 MIOB_D2 C
1 2 AK22 AB3
PCIE_GTX_C_CRX_P6 CV25 OPT@ 0.1U_0402_16V7K PCIE_GTX_CRX_P6 PEX_TX5_N MIOB_D3
1 2 AL23 PEX_TX6 MIOB_D4 AB2
PCIE_GTX_C_CRX_N6 CV26 OPT@ 1 2 0.1U_0402_16V7K PCIE_GTX_CRX_N6 AM23 AB1 THERM#_VGA 1 OPT@ 2
PCIE_GTX_C_CRX_P7 CV27 OPT@ 0.1U_0402_16V7K PCIE_GTX_CRX_P7 PEX_TX6_N MIOB_D5 RV10 100K_0402_5%
1 2 AM24 AC4
PCIE_GTX_C_CRX_N7 CV28 OPT@ 0.1U_0402_16V7K PCIE_GTX_CRX_N7 PEX_TX7 MIOB_D6
1 2 AM25 AC1
PCIE_GTX_C_CRX_P8 CV29 OPT@ 0.1U_0402_16V7K PCIE_GTX_CRX_P8 PEX_TX7_N MIOB_D7
1 2 AL25 AC2
PCIE_GTX_C_CRX_N8 CV30 OPT@ 0.1U_0402_16V7K PCIE_GTX_CRX_N8 PEX_TX8 MIOB_D8
1 2 AK25 AC3
PCIE_GTX_C_CRX_P9 CV31 OPT@ 0.1U_0402_16V7K PCIE_GTX_CRX_P9 PEX_TX8_N MIOB_D9
1 2 AL26 AE3
PCIE_GTX_C_CRX_N9 CV32 OPT@ 0.1U_0402_16V7K PCIE_GTX_CRX_N9 PEX_TX9 MIOBD_10
1 2 AM26 AE2
PCIE_GTX_C_CRX_P10CV33 OPT@ 0.1U_0402_16V7K PCIE_GTX_CRX_P10 PEX_TX9_N MIOB_D11
1 2 AM27 U6
PCIE_GTX_C_CRX_N10CV34 OPT@ 0.1U_0402_16V7K PCIE_GTX_CRX_N10 PEX_TX10 MIOB_D12
1 2 AM28 W6
PCIE_GTX_C_CRX_P11CV35 OPT@ 0.1U_0402_16V7K PCIE_GTX_CRX_P11 PEX_TX10_N MIOB_D13
1 2 AL28 Y6
PCIE_GTX_C_CRX_N11CV36 OPT@ 0.1U_0402_16V7K PCIE_GTX_CRX_N11 PEX_TX11 MIOB_D14 VGA_DDCDATA @
1 2 AK28 1 2
PCIE_GTX_C_CRX_P12CV37 OPT@ 0.1U_0402_16V7K PCIE_GTX_CRX_P12 PEX_TX11_N RV13 2.2K_0402_5%
1 2 AK29 PEX_TX12 MIOA_HSYNC N3
PCIE_GTX_C_CRX_N12CV38 OPT@ 1 2 0.1U_0402_16V7K PCIE_GTX_CRX_N12 AL29 L3 VGA_DDCCLK 1 @ 2
PCIE_GTX_C_CRX_P13CV39 OPT@ 0.1U_0402_16V7K PCIE_GTX_CRX_P13 PEX_TX12_N MIOA_VSYNC RV14 2.2K_0402_5%
1 2 AM29
PCIE_GTX_C_CRX_N13CV40 OPT@ 0.1U_0402_16V7K PCIE_GTX_CRX_N13 PEX_TX13
1 2 AM30 W1
PCIE_GTX_C_CRX_P14CV41 OPT@ 0.1U_0402_16V7K PCIE_GTX_CRX_P14 PEX_TX13_N MIOB_HSYNC
1 2 AM31 W2
PCIE_GTX_C_CRX_N14CV42 OPT@ 0.1U_0402_16V7K PCIE_GTX_CRX_N14 PEX_TX14 MIOB_VSYNC
1 2 AM32
PCIE_GTX_C_CRX_P15CV43 OPT@ 0.1U_0402_16V7K PCIE_GTX_CRX_P15 PEX_TX14_N
1 2 AN32 N2
PCIE_GTX_C_CRX_N15CV44 OPT@ 0.1U_0402_16V7K PCIE_GTX_CRX_N15 PEX_TX15 MIOA_DE
1 2 AP32 P5
PEX_TX15_N MIOA_CTL3
N5
MIOA_VREF
Y5
CLK_PCIE_VGA MIOB_DE
29 CLK_PCIE_VGA AR16 W3
CLK_PCIE_VGA# PEX_REFCLK MIOB_CTL3
29 CLK_PCIE_VGA# AR17 AF1
CLK_REQ_GPU# PEX_REFCLK_N MIOB_VREF
AR13
PEX_CLKREQ_N
MIOA_CLKIN N4 1 2
1 @ 2 PEX_TSTCLK_OUT AJ17 R4 RV15 @ 10K_0402_5%
RV16 200_0402_1% PEX_TSTCLK_OUT# PEX_TSTCLK_OUT MIOA_CLKOUT
Differential signal AJ18
PEX_TSTCLK_OUT_N
AE1 1 2 CV50 OPT@
MIOB_CLKIN RV17 @ 10K_0402_5% 10K_0402_5%
V4
B PLTRST_VGA_R# MIOB_CLKOUT B
1 OPT@ 2
32 PLTRST_VGA#
RV18 0_0402_5%
AM16
AG21
PEX_RST_N
T4
120mA LV3 CRT@
PEX_TERMP MIOA_CLKOUT_N +DACA_VDD 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 OPT@ 2 W4 4700P_0402_25V7K 1 2 +3VS_DGPU
RV19 2.49K_0402_1% MIOB_CLKOUT_N MMZ1608D301BT_0603
U5 1 1 1 1 1 1 1 1
@ +PLLVDD MIOACAL_PD_VDDQ CV51 CV49
AE9 T5
XTALSSIN PLLVDD MIOACAL_PU_GND CV81 CV73 CV72 CV48 CV80 CV50 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K
25 27M_SSC 1 2
RV105 0_0402_5% +SP_PLLVDD AF9 AA7 CRT@ CRT@ CRT@ CRT@ CRT@ CRT@ CRT@ CRT@
SP_PLLVDD MIOBCAL_PD_VDDQ 2 2 2 2 2 2 2 2
AA6
MIOBCAL_PU_GND
AD9
VID_PLLVDD 1U_0402_6.3V4Z 0.1U_0402_16V4Z 470P_0402_50V7K
CLK

25 27M_CLK RV103 1 OPT@ 2 0_0402_5% XTALIN B1 XTAL_IN VGA_CRT_R

B2 AM15 VGA_CRT_R 26
XTAL_OUT DACA_RED VGA_CRT_G
AM14 VGA_CRT_G 26
XTALOUT DACA_GREEN VGA_CRT_B
D1 AL14 VGA_CRT_B 26
XTAL_OUTBUFF DACA_BLUE
2 OPT@ 1 XTALSSIN D2
XTAL_SSIN
1

RV25 10K_0402_5% AM13 VGA_CRT_HSYNC

DACA_HSYNC VGA_CRT_VSYNC VGA_CRT_HSYNC 26
RV26 AL13
DACA_VSYNC VGA_CRT_VSYNC 26
10K_0402_5% Internal Thermal Sensor Close to GPU
OPT@ SMB_CLK_GPU E2 AJ12 +DACA_VDD
14 SMB_CLK_GPU I2CS_SCL DACA_VDD
SMB_DATA_GPU E1 AK12 +DACA_VREF
14 SMB_DATA_GPU
2

I2CS_SDA DACA_VREF DACA_RSET VGA_CRT_R

DACs

DACA_RSET AK13 1 CRT@ 2

E3 RV20 150_0402_1%
I2CC_SCL

1
E4 AK4 1 VGA_CRT_G 1 CRT@ 2
I2CC_SDA DACB_RED RV27 CV47 RV21 150_0402_1%
AL4
+3VS_DGPU DACB_GREEN 124_0402_1% 0.1U_0402_16V4Z VGA_CRT_B
33,46,56 DGPU_PWR_EN G3 AJ4 1 CRT@ 2
I2CB_SCL DACB_BLUE CRT@ CRT@ RV23 150_0402_1%
I2C

G2
I2CB_SDA 2
AM1

2
DACB_HSYNC
2

VGA_DDCCLK
Add Level Shifter for RV124 CRT 26 VGA_DDCCLK
26 VGA_DDCDATA
VGA_DDCDATA
G1
G4
I2CA_SCL DACB_VSYNC
AM2
I2CA_SDA
2

10K_0402_5% AG7 +DACB_VDD 2 1

CLK_REQ_VGA# at DVT OPT@ RV118 F6
DACB_VDD
AK6 RV31 10K_0402_5%
A 10K_0402_5% I2CH_SCL DACB_VREF A
G6 AH7 OPT@
2 1

OPT@ I2CH_SDA DACB_RSET

G

QV2 OPT@ N11P-GE1-A3 BGA 969P @

29 CLK_REQ_VGA# 1 3 CLK_REQ_GPU#
D

2N7002_SOT23-3
RV123
10K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/01 Deciphered Date 2010/01/01 Title
@ @
1 2 PCIE/DAC/GPIO
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RV110 0_0402_5% Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Wednesday, April 14, 2010 Sheet 13 of 59
5 4 3 2 1
 5 4 3 2 1

UV1D

Part 4 of 7
AM11 IFPA_TXC NC_0 A2
AM12 IFPA_TXC_N NC_1 A7 Internal Thermal Sensor
AM8 B7
AL8
AM10
IFPA_TXD0
IFPA_TXD0_N
NC_2
NC_3
C5
C7
External VGA Thermal Sensor SMB_CLK_GPU 13

IFPA_TXD1 NC_4 SMB_DATA_GPU 13

AM9 D5
IFPA_TXD1_N NC_5
AK10 IFPA_TXD2 NC_6 D6

1
AL10 IFPA_TXD2_N NC_7 D7
AK11 E5 RV33 RV34
IFPA_TXD3 NC_8
AL11 E7 0_0402_5% 0_0402_5%
D IFPA_TXD3_N NC_9 @ @ D
F4
NC_10
G5

2
NC_11 +3VS_DGPU
AP13
AN13
IFPB_TXC NC_12
G11
G12 OPT@ UV2
Address: 0x9A H
IFPB_TXC_N NC_13 VGA_SMB_CK2
AN8 G14 2 1 1 8
IFPB_TXD4 NC_14 CV53 0.1U_0402_16V4Z VDD SCLK
AP8 IFPB_TXD4_N NC_15 G15
AP10 G27 THERM_D+ 2 7 VGA_SMB_DA2
IFPB_TXD5 NC_16 CV54 D+ SDATA
AN10 G28
IFPB_TXD5_N NC_17 THERM#_VGA
AR11 G24 1 2 3 6 THERM#_VGA 13
IFPB_TXD6 NC_18 OPT@ D- ALERT#
AR10 G25
IFPB_TXD6_N NC_19 THERM_D- 2200P_0402_50V7K
AN11 H32 4 5
IFPB_TXD7 NC_20 THERM# GND
AP11 IFPB_TXD7_N NC_21 J18 1 OPT@ 2 +3VS_DGPU
J19 RV54 10K_0402_5%
NC_22

NC
J25 ADM1032ARMZ-2REEL_MSOP8
NC_23 OPT@
AM7 J26
IFPC_L0 NC_24
AM6 L29
IFPC_L0_N NC_25
AL5 M7
IFPC_L1 NC_26
AM5 M29
IFPC_L1_N NC_27
AM3 IFPC_L2 NC_28 P6
AM4 P29 1 @ 2 +1.05VS_DGPU
IFPC_L2_N NC_29 RV37 0_0402_5% +3VS_DGPU
AP1 R29
IFPC_L3 NC_30
AR2 U7
IFPC_L3_N NC_31 +3VS_DGPU
V6
NC_32
Y4
NC_33

2
AR8 AA4
IFPD_L0 NC_34 RV22 RV24
AR7 IFPD_L0_N NC_35 AB4
AP7 AB7 2.2K_0402_5% 2.2K_0402_5%
IFPD_L1 NC_36 OPT@ OPT@
AN7 AC5
IFPD_L1_N NC_37

5
OPT@

LVDS/TMDS
AN5 AD6

1
IFPD_L2 NC_38 QV1B
C AP5 AD29 C
IFPD_L2_N NC_39 VGA_SMB_CK2
AR5 AE29 4 3 EC_SMB_CK2 29,43
IFPD_L3 NC_40
AR4 AF6
IFPD_L3_N NC_41

2
AG6 OPT@ 2N7002DW-T/R7_SOT363-6
NC_42 QV1A
NC_43 AG20
AH6 AG29 VGA_SMB_DA2 1 6
IFPE_L0 NC_44 EC_SMB_DA2 29,43
AH5 AH29
IFPE_L0_N NC_45 2N7002DW-T/R7_SOT363-6
AH4 AJ5
IFPE_L1 NC_46
AG4 AK15
IFPE_L1_N NC_47
AF4 AL7
IFPE_L2 NC_48 VGA_SMB_CK2 EC_SMB_CK2
AF5 1 @ 2
IFPE_L2_N RV35 0_0402_5%
AE6 IFPE_L3
AE5 VGA_SMB_DA2 1 @ 2 EC_SMB_DA2
IFPE_L3_N RV36 0_0402_5%
D35 VDD_SENSE VDD_SENSE 56
VDD_SENSE_0
AL2 P7
IFPF_L0 VDD_SENSE_1
AL3 AD20
IFPF_L0_N VDD_SENSE_2
AJ3
IFPF_L1
AJ2
IFPF_L1_N
AJ1
IFPF_L2
AH1 AD19
IFPF_L2_N GND_SENSE_0
AH2 E35
IFPF_L3 GND_SENSE_1
AH3 R7
IFPF_L3_N GND_SENSE_2

AP2
IFPC_AUX_I2CW_SCL
AN3
IFPC_AUX_I2CW_SDA_N TEST
B B
AP4 AP35 TESTMODE
IFPD_AUX_I2CX_SCL TESTMODE
AN4 IFPD_AUX_I2CX_SDA_N JTAG_TCK AP14 TV2
AN14 TV3
JTAG_TDI

1
JTAG_TDO AN16 TV4
AE4 AR14 RV47
IFPE_AUX_I2CY_SCL JTAG_TMS TV5
AD4 AP16 1 2 OPT@
IFPE_AUX_I2CY_SDA_N JTAG_TRST_N RV41 @ 10K_0402_5% 10K_0402_5%

2
AF3
IFPF_AUX_I2CZ_SCL
AF2 IFPF_AUX_I2CZ_SDA_N SERIAL
C3
ROM_CS_N ROM_SI
D3 ROM_SI 24
ROM_SI ROM_SO
C4 ROM_SO 24
ROM_SO ROM_SCLK
D4 ROM_SCLK 24
ROM_SCLK

GENERAL A5
NC/SPDIF
A4
BUFRST_N
N9 1 OPT@ 2
MULTI_STRAP_REF0_GND
+3VS_DGPU 1 OPT@ 2 AB5 RV48 40.2K_0402_1%
RV49 10K_0402_5% CEC
M9 1 OPT@ 2
STRAP0 MULTI_STRAP_REF1_GND RV50 40.2K_0402_1%
24 STRAP0 W5 STRAP0
24 STRAP1 STRAP1 W7 B5 THERM_D+
STRAP2 STRAP1 THERMDP THERM_D-
24 STRAP2 V7 B4
STRAP2 THERMDN

A N11P-GE1-A3 BGA 969P @ A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/01 Deciphered Date 2010/01/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS/HDMI/DP/THM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Wednesday, April 14, 2010 Sheet 14 of 59
5 4 3 2 1
 5 4 3 2 1

N11P-GS1 Performance Mode N11P-GE1 Performance Mode N11M-GE1 Performance Mode

Mode NVCLK (MHz) MCLK (MHz) +VGA_CORE Mode NVCLK (MHz) MCLK (MHz) +VGA_CORE Mode NVCLK (MHz) MCLK (MHz) +VGA_CORE

P0 450 790 0.90 V P0 575 790 0.95 V P0 625 790 1.03 V

P8 405 324 0.85 V P8 405 324 0.85 V P8 405 405 0.85 V

D D
P12 135 135 0.80 V P12 135 135 0.80 V P12 135 135 0.85 V

+VGA_CORE +VGA_CORE
UV1G

AB11
AB13
VDD_0 Part 7 of 7 VDD_56 P21
P23
29A for N11P-GS1
VDD_1 VDD_57
AB15
AB17
VDD_2 VDD_58 P25
R11
28A for N11P-GE1 +VGA_CORE
VDD_3 VDD_59
AB19
AB21
VDD_4 VDD_60 R12
R13
16A for N11M-GE1
VDD_5 VDD_61
AB23 VDD_6 VDD_62 R14 1 1
AB25 VDD_7 VDD_63 R15
AC11 R16 CV57 + + CV58
VDD_8 VDD_64 OPT@ OPT@
AC12 VDD_9 VDD_65 R17
AC13 R18 330U_D2_2.5VM_R9M 330U_D2_2.5VM_R9M
VDD_10 VDD_66 2 2
AC14 VDD_11 VDD_67 R19
AC15 VDD_12 VDD_68 R20
AC16 VDD_13 VDD_69 R21
AC17 VDD_14 VDD_70 R22
AC18 VDD_15 VDD_71 R23
AC19 R24 +VGA_CORE
VDD_16 VDD_72
AC20 VDD_17 VDD_73 R25
AC21 T12 4.7U_0603_6.3V6K 1U_0402_6.3V4Z 4700P_0402_25V7K
VDD_18 VDD_74
C AC22 VDD_19 VDD_75 T14 C
AC23 VDD_20 VDD_76 T16

POWER
AC24 VDD_21 VDD_77 T18 2 2 1 1 1
AC25 T20 CV59 CV60 CV61 CV212 CV62 CV63 CV64
VDD_22 VDD_78 10U_0603_6.3V6M OPT@ N11M@ OPT@ OPT@ OPT@ N11M@ CV64 N11P@
AD12 VDD_23 VDD_79 T22
AD14 T24 OPT@ 0.1U_0402_16V7K
VDD_24 VDD_80 1 1 2 2 2
AD16 VDD_25 VDD_81 V11
AD18 VDD_26 VDD_82 V13
AD22 VDD_27 VDD_83 V15
AD24 V17 10U_0603_6.3V6M 4.7U_0603_6.3V6K 4700P_0402_25V7K
VDD_28 VDD_84
L11 VDD_29 VDD_85 V19
L12 VDD_30 VDD_86 V21
L13 VDD_31 VDD_87 V23
L14 VDD_32 VDD_88 V25
L15 VDD_33 VDD_89 W11
L16 W12 +VGA_CORE
VDD_34 VDD_90
L17 VDD_35 VDD_91 W13
L18 W14 0.047U_0402_25V6K 0.022U_0402_25V7K
VDD_36 VDD_92
L19 VDD_37 VDD_93 W15
L20 VDD_38 VDD_94 W16
L21 VDD_39 VDD_95 W17 1 1 1 1 1 1 1
L22 W18 CV66 CV67 CV68 CV69 CV70 CV71 CV65
VDD_40 VDD_96 OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@
L23 VDD_41 VDD_97 W19
L24 W20 0.047U_0402_25V6K 0.022U_0402_25V7K
VDD_42 VDD_98 2 2 2 2 2 2 2
L25 VDD_43 VDD_99 W21
M12 VDD_44 VDD_100 W22
M14 VDD_45 VDD_101 W23
B M16 W24 0.047U_0402_25V6K 0.022U_0402_25V7K 0.022U_0402_25V7K Add CV1 B
VDD_46 VDD_102
M18 W25
M20
VDD_47 VDD_103
Y12 Add CV123 and CV124 and CV2
VDD_48 VDD_104
M22 Y14
M24
VDD_49 VDD_105
Y16 for N11P-LP1
VDD_50 VDD_106 +VGA_CORE
P11 VDD_51 VDD_107 Y18
P13 VDD_52 VDD_108 Y20
P15 Y22 0.01U_0402_25V7K 0.01U_0402_25V7K 0.01U_0402_25V7K 0.22U_0402_6.3V6K
VDD_53 VDD_109
P17 VDD_54 VDD_110 Y24
P19 VDD_55
1 1 1 1 1 1 1 1

1
CV74 CV75 CV76 CV77 CV78 CV79 CV123 CV124 CV1 CV2
0.01U_0402_25V7K OPT@ OPT@ OPT@ OPT@ OPT@ N11P@ N11P@ OPT@ OPT@
OPT@

2
N11P-GE1-A3 BGA 969P @ 2 2 2 2 2 2 2 2

0.01U_0402_25V7K 0.01U_0402_25V7K 0.01U_0402_25V7K 0.01U_0402_25V7K 0.22U_0402_6.3V6K

A A

Security Classification
Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/01 Deciphered Date 2010/01/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA CORE
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Thursday, April 15, 2010 Sheet 15 of 59
5 4 3 2 1
 5 4 3 2 1

UV1E
Close to Pin
3.5A Part 5 of 7 2000mA
+VRAM_1.5VS 4.7U_0603_6.3V6K 0.1U_0402_16V4Z J23
1600mA AG11 0.1U_0402_16V4Z 1U_0402_6.3V4Z 10U_0603_6.3V6M +1.05VS_DGPU
FBVDDQ_0 PEX_IOVDDQ_0
J24 FBVDDQ_1 PEX_IOVDDQ_1 AG12
1 1 1 1 1 J29 FBVDDQ_2 PEX_IOVDDQ_2 AG13 1 1 1 1 1 1 1
CV82 CV83 CV84 CV85 CV86 AA27 AG15 CV3
OPT@ OPT@ OPT@ OPT@ OPT@ FBVDDQ_3 PEX_IOVDDQ_3 CV87 CV88 CV89 CV90 CV91 CV92 OPT@
AA29 FBVDDQ_4 PEX_IOVDDQ_4 AG16
4.7U_0603_6.3V6K 0.1U_0402_16V4Z AA31 AG17 OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ 22U_0805_6.3V6M
2 2 2 2 2 FBVDDQ_5 PEX_IOVDDQ_5 2 2 2 2 2 2 2
AB27 FBVDDQ_6 PEX_IOVDDQ_6 AG18
AB29 FBVDDQ_7 PEX_IOVDDQ_7 AG22
0.1U_0402_16V4Z AC27 AG23 0.1U_0402_16V4Z 1U_0402_6.3V4Z 4.7U_0603_6.3V6K
FBVDDQ_8 PEX_IOVDDQ_8
D
AD27 FBVDDQ_9 PEX_IOVDDQ_9 AG24 D
AE27 FBVDDQ_10 PEX_IOVDDQ_10 AG25 Add CV3 and CV4
AJ28 AG26 0.1U_0402_16V4Z 1U_0402_6.3V4Z 10U_0603_6.3V6M +1.05VS_DGPU
FBVDDQ_11 PEX_IOVDDQ_11
B18 FBVDDQ_12 PEX_IOVDDQ_12 AJ14
+VRAM_1.5VS 0.047U_0402_25V6K 0.01U_0402_25V7K 0.01U_0402_25V7K E21 AJ15 1 1 1 1 1 1 1
FBVDDQ_13 PEX_IOVDDQ_13 CV4
G17 FBVDDQ_14 PEX_IOVDDQ_14 AJ19
G18 AJ21 CV93 CV94 CV95 CV96 CV97 CV98 OPT@
1 1 1 1 1 1 1 FBVDDQ_15 PEX_IOVDDQ_15
CV99 CV100 CV101 CV102 CV103 CV104 CV218 G22 AJ22 OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ 22U_0805_6.3V6M
OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ FBVDDQ_16 PEX_IOVDDQ_16 2 2 2 2 2 2 2
G8 FBVDDQ_17 PEX_IOVDDQ_17 AJ24
0.047U_0402_25V6K G9 AJ25
2 2 2 2 2 2 2 FBVDDQ_18 PEX_IOVDDQ_18 0.1U_0402_16V4Z 1U_0402_6.3V4Z 4.7U_0603_6.3V6K
H29 FBVDDQ_19 PEX_IOVDDQ_19 AJ27

POWER
J14 FBVDDQ_20 PEX_IOVDDQ_20 AK18
0.047U_0402_25V6K 0.01U_0402_25V7K 0.01U_0402_25V7K J15 AK20
FBVDDQ_21 PEX_IOVDDQ_21
J16 FBVDDQ_22 PEX_IOVDDQ_22 AK23
J17 FBVDDQ_23 PEX_IOVDDQ_23 AK26 Close to Pin
Close to Pin J20
J21
FBVDDQ_24 PEX_IOVDDQ_24 AL16
100NH_LQW18ANR10J00D_5%_0603
FBVDDQ_25 0.1U_0402_16V4Z 1U_0402_6.3V4Z
J22 FBVDDQ_26 1 2 +1.05VS_DGPU
LV4 OPT@
N27
P27
FBVDDQ_27 500mA AK16 1 1 1 1 1
FBVDDQ_28 PEX_IOVDD_0 CV109
R27 FBVDDQ_29 PEX_IOVDD_1 AK17
T27 AK21 CV105 CV106 CV107 CV108 OPT@
FBVDDQ_30 PEX_IOVDD_2 @ @ OPT@ OPT@ 4.7U_0603_6.3V6K
U27 FBVDDQ_31 PEX_IOVDD_3 AK24
U29 AK27 2 2 2 2 4.7U_0603_6.3V6K 2
FBVDDQ_32 PEX_IOVDD_4
V27
V29
FBVDDQ_33 120mA 0.1U_0402_16V4Z
FBVDDQ_34
V34
W27
FBVDDQ_35 110mA AG14 +PEX_PLLVDD
FBVDDQ_36 PEX_PLLVDD
Y27 FBVDDQ_37 +3VS_DGPU
C
+IFPAB_PLLVDD AK9 AG19
120mA C

@ 1K_0402_1% IFPAB_PLLVDD PEX_SVDD_3V3_0

1 2 AJ11 IFPAB_RSET PEX_SVDD_3V3_1 F7
RV96 1 1
+3VS_DGPU
+IFPAB_IOVDD CV110 CV111
AG9
AG10
IFPA_IOVDD
J10
120mA 0.1U_0402_16V4Z 1U_0402_6.3V4Z OPT@ 0.1U_0402_16V4Z
IFPB_IOVDD VDD33_0 0.1U_0402_16V4Z 2 2 @
VDD33_1 J11
VDD33_2 J12 1 1 1 1 1
RV107 2 OPT@ 1 10K_0402_5% +IFPC_PLLVDD AJ9 J13 CV114
RV51 @ 2 1K_0402_1% IFPC_PLLVDD VDD33_3 CV217 CV216 CV112 CV113 OPT@
1 AK7 IFPC_RSET VDD33_4 J9
OPT@ OPT@ OPT@ OPT@ 4.7U_0603_6.3V6K
RV109 2 OPT@ 1 10K_0402_5% +IFPC_IOVDD AJ8 2 2 2 2 2
IFPC_IOVDD
P9 0.1U_0402_16V4Z 0.1U_0402_16V4Z
RV99 MIOA_VDDQ_0
2 OPT@ 1 10K_0402_5% +IFPD_PLLVDD AC6
IFPD_PLLVDD MIOA_VDDQ_1 R9
RV52 1 @ 2 1K_0402_1% AB6 T9
IFPD_RSET MIOA_VDDQ_2
MIOA_VDDQ_3 U9
RV97 2 OPT@ 1 10K_0402_5% +IFPD_IOVDD AK8 +MIO_VDDQ +3VS_DGPU
IFPD_IOVDD N11M@
AA9
240mA 1 2
RV101 MIOB_VDDQ_0
2 OPT@ 1 10K_0402_5% +IFPEF_PLLVDD AJ6
IFPEF_PLLVDD MIOB_VDDQ_1 AB9 1 1 LV6 100NH_LQW18ANR10J00D_5%_0603
RV53 1 @ 2 1K_0402_1% AL1 W9 CV116 CV125
IFPEF_RSET MIOB_VDDQ_2 N11M@ N11M@
MIOB_VDDQ_3 Y9
RV113 2 OPT@ 1 10K_0402_5% +IFPE_IOVDD AE7 0.1U_0402_16V4Z 0.1U_0402_16V4Z CV125
IFPE_IOVDD 2 2 10K_0402_5%
AD7 IFPF_IOVDD
LP@

N11P-GE1-A3 BGA 969P @

B B

+1.05VS_DGPU CV116 CV125

LV5 200mA 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 1 1U_0402_6.3V4Z +IFPAB_PLLVDD
BLM18PG181SN1D_0603 LP1@ LP1@
@

1 1 1 1 1 LV6
CV117 CV121 100NH_LQW18ANR10J00D_5%_0603
4.7U_0603_6.3V6K CV118 CV119 CV120 0.1U_0402_16V4Z
@ @ @ @ @ LP1@
2 2 2 2 2

CV120 OPT@
4.7U_0603_6.3V6K 0.1U_0402_16V4Z 10K_0402_5%

LV9
+3VS_DGPU 2 1 +IFPAB_IOVDD
BLM18PG181SN1D_0603
@

+1.8VS
LV8 285mA
A 2 1 4.7U_0603_6.3V6K 0.1U_0402_16V4Z +IFPAB_IOVDD A
BLM18PG181SN1D_0603
1 @ 1 1 1 1
CV132 CV213
4.7U_0603_6.3V6K CV133 CV134 CV135 0.1U_0402_16V4Z
@ @ @ @ @
2 2 2 2 2

1U_0402_6.3V4Z
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/01 Deciphered Date 2010/01/01 Title

CV213 OPT@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
POWER
10K_0402_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Wednesday, April 14, 2010 Sheet 16 of 59
5 4 3 2 1
 5 4 3 2 1

UV1F

B3 Part 6 of 7
GND_0
B6 GND_1 GND_97 V18
B9 GND_2 GND_98 V20
B12 GND_3 GND_99 V22
B15 GND_4 GND_100 V24
B21 GND_5 GND_101 V31
B24 GND_6 GND_102 Y11
B27 GND_7 GND_103 Y13
B30 GND_8 GND_104 Y15
B33 GND_9 GND_105 Y17
D
C2 GND_10 GND_106 Y19 D
C34 GND_11 GND_107 Y21
E6 GND_12 GND_108 Y23
E9 GND_13 GND_109 Y25
E12 GND_14 GND_110 AA2
E15 GND_15 GND_111 AA5
E18 GND_16 GND_112 AA11
E24 GND_17 GND_113 AA12
E27 GND_18 GND_114 AA13
E30 GND_19 GND_115 AA14
F2 GND_20 GND_116 AA15
F31 GND_21 GND_117 AA16
F34 GND_22 GND_118 AA17
F5 GND_23 GND_119 AA18
J2 GND_24 GND_120 AA19
J5 GND_25 GND_121 AA20
J31 GND_26 GND_122 AA21
J34 GND_27 GND_123 AA22
K9 GND_28 GND_124 AA23
L9 GND_29 GND_125 AA24
M2 GND_30 GND_126 AA25
M5 GND_31 GND_127 AA34
M11 GND_32 GND_128 AB12
M13 GND_33 GND_129 AB14
M15 GND_34 GND_130 AB16
M17 GND_35 GND_131 AB18
M19 GND_36 GND_132 AB20
M21 GND_37 GND_133 AB22
M23 GND_38 GND_134 AB24
M25 GND_39 GND_135 AC9
C M31 GND_40 GND_136 AD2 C
M34 GND_41 GND_137 AD5

GND
N11 GND_42 GND_138 AD11
N12 GND_43 GND_139 AD13
N13 GND_44 GND_140 AD15
N14 GND_45 GND_141 AD17
N15 GND_46 GND_142 AD21
N16 GND_47 GND_143 AD23
N17 GND_48 GND_144 AD25
N18 GND_49 GND_145 AD31
N19 GND_50 GND_146 AD34
N20 GND_51 GND_147 AE11
N21 GND_52 GND_148 AE12
N22 GND_53 GND_149 AE13
N23 GND_54 GND_150 AE14
N24 GND_55 GND_151 AE15
N25 GND_56 GND_152 AE16
P12 GND_57 GND_153 AE17
P14 GND_58 GND_154 AE18
P16 GND_59 GND_155 AE19
P18 GND_60 GND_156 AE20
P20 GND_61 GND_157 AE21
P22 GND_62 GND_158 AE22
P24 GND_63 GND_159 AE23
R2 GND_64 GND_160 AE24
R5 GND_65 GND_161 AE25
R31 GND_66 GND_162 AG2
R34 GND_67 GND_163 AG5
T11 GND_68 GND_164 AG31
B
T13 GND_69 GND_165 AG34 B
T15 GND_70 GND_166 AK2
T17 GND_71 GND_167 AK5
T19 GND_72 GND_168 AK14
T21 GND_73 GND_169 AK31
T23 GND_74 GND_170 AK34
T25 GND_75 GND_171 AL6
U11 GND_76 GND_172 AL9
U12 GND_77 GND_173 AL12
U13 GND_78 GND_174 AL15
U14 GND_79 GND_175 AL18
U15 GND_80 GND_176 AL21
U16 GND_81 GND_177 AL24
U17 GND_82 GND_178 AL27
U18 GND_83 GND_179 AL30
U19 GND_84 GND_180 AN2
U20 GND_85 GND_181 AN34
U21 GND_86 GND_182 AP3
U22 GND_87 GND_183 AP6
U23 GND_88 GND_184 AP9
U24 GND_89 GND_185 AP12
U25 GND_90 GND_186 AP15
V2 GND_91 GND_187 AP18
V5 GND_92 GND_188 AP21
V9 GND_93 GND_189 AP24
V12 GND_94 GND_190 AP27
V14 GND_95 GND_191 AP30
V16 GND_96 GND_192 AP33

A A
N11P-GE1-A3 BGA 969P @

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/01 Deciphered Date 2010/01/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Wednesday, March 24, 2010 Sheet 17 of 59
5 4 3 2 1
 5 4 3 2 1

UV1B

D Part 2 of 7 V32 CMDA0 D

MDA[0..63] FBA_CMD0 CMDA0 20
MDA0 L32 W31 CMDA1
20,21 MDA[0..63] FBA_D0 FBA_CMD1 CMDA1 20,21
MDA1 CMDA2
MDA2
N33
L33
FBA_D1
FBA_D2
FBA_CMD2
FBA_CMD3
U31
Y32 CMDA3
CMDA2 20
CMDA3 20,21
Mode C - Mirror Mode Mapping
MDA3 N34 AB35 CMDA4
FBA_D3 FBA_CMD4 CMDA4 20,21
MDA4 N35 AB34 CMDA5 DATA Bus
FBA_D4 FBA_CMD5 CMDA5 20,21
MDA5 P35 W35 CMDA6
FBA_D5 FBA_CMD6 CMDA6 20,21
MDA6 P33 W33 CMDA7
CMDA7 20,21
Address 0..31 32..63
MDA7 FBA_D6 FBA_CMD7 CMDA8
P34 FBA_D7 FBA_CMD8 W30 CMDA8 20,21
MDA8 K35 FBA_D8 FBA_CMD9 T34 CMDA9
CMDA9 20,21 CMD0 CKE_L
MDA9 K33 T35 CMDA10
FBA_D9 FBA_CMD10 CMDA10 20,21
MDA10 K34 AB31 CMDA11 CMD1 A8 A8
FBA_D10 FBA_CMD11 CMDA11 21
MDA11 H33 Y30 CMDA12
FBA_D11 FBA_CMD12 CMDA12 20,21
MDA12 G34 Y34 CMDA13 CMD2 CS0#_L
FBA_D12 FBA_CMD13 CMDA13 20,21
MDA13 G33 W32 CMDA14
FBA_D13 FBA_CMD14 CMDA14 20,21
MDA14 E34 AA30 CMD3 A7 A6
MDA15 FBA_D14 FBA_CMD15 CMDA16
E33 FBA_D15 FBA_CMD16 AA32 CMDA16 21
MDA16 G31 Y33 CMDA17 CMD4 A2 A1
FBA_D16 FBA_CMD17 CMDA17 20,21
MDA17 F30 U32 CMDA18
FBA_D17 FBA_CMD18 CMDA18 20,21
MDA18 G30 FBA_D18 FBA_CMD19 Y31 CMDA19
CMDA19 20,21 CMD5 A11 A9
MDA19 G32 U34 CMDA20
FBA_D19 FBA_CMD20 CMDA20 20,21
MDA20 K30 Y35 CMDA21 CMD6 A5 A4
FBA_D20 FBA_CMD21 CMDA21 20,21
MDA21 K32 W34 CMDA22
FBA_D21 FBA_CMD22 CMDA22 20,21
MDA22 H30 V30 CMD7 A0 A12
MDA23 FBA_D22 FBA_CMD23 CMDA24
K31 FBA_D23 FBA_CMD24 U35 CMDA24 20,21
MDA24 L31 U30 CMDA25 CMD8 CAS# CAS#
FBA_D24 FBA_CMD25 CMDA25 20
MDA25 L30 U33 CMDA26
FBA_D25 FBA_CMD26 CMDA26 20,21

MEMORY INTERFACE
C MDA26 M32 AB30 CMDA27 CMD9 BA1 A3 C
FBA_D26 FBA_CMD27 CMDA27 21
MDA27 N30 AB33 CMDA28
FBA_D27 FBA_CMD28 CMDA28 20,21
MDA28 M30 FBA_D28 FBA_CMD29 T33 CMDA29
CMDA29 20,21 CMD10 A9 A11
MDA29 P31 W29 CMDA30
FBA_D29 FBA_CMD30 CMDA30 20,21
MDA30 R32 CMD11 CS0#_H
MDA31 FBA_D30
R30 FBA_D31
MDA32 AG30 CMD12 BA0 BA0
MDA33 FBA_D32 DQMA0
AG32 FBA_D33 FBA_DQM0 P32 DQMA[7..0] 20,21
MDA34 AH31 H34 DQMA1 CMD13 BA2 A15
MDA35 FBA_D34 FBA_DQM1 DQMA2
AF31 FBA_D35 FBA_DQM2 J30
MDA36 AF30 P30 DQMA3 CMD14 A3 BA1
MDA37 FBA_D36 FBA_DQM3 DQMA4
AE30 FBA_D37 FBA_DQM4 AF32
MDA38 AC32 FBA_D38 FBA_DQM5 AL32 DQMA5 CMD15 CS1#_H
MDA39 AD30 AL34 DQMA6
+VRAM_1.5VS MDA40 FBA_D39 FBA_DQM6 DQMA7
AN33 FBA_D40 FBA_DQM7 AF35 CMD16 ODT_H
MDA41 AL31 FBA_D41

A
MDA42 AM33 CMD17 A4 A5
FBA_D42
1

MDA43 AL33
RV55 MDA44 FBA_D43 DQSA#0
AK30 FBA_D44 FBA_DQS_RN0 L35 DQSA#[7..0] 20,21 CMD18 A13 A14
1.1K_0402_1% MDA45 AK32 G35 DQSA#1
@ MDA46 FBA_D45 FBA_DQS_RN1 DQSA#2
AJ30 FBA_D46 FBA_DQS_RN2 H31 CMD19 WE# A10
12mil MDA47 AH30 N32 DQSA#3
2

FBA_D47 FBA_DQS_RN3
+FB_VREF MDA48 AH33 FBA_D48 FBA_DQS_RN4 AD32 DQSA#4 CMD20 A1 A2
MDA49 AH35 AJ31 DQSA#5
FBA_D49 FBA_DQS_RN5
1

1 MDA50 AH34 AJ35 DQSA#6 CMD21 A10 WE#

RV56 CV146 MDA51 FBA_D50 FBA_DQS_RN6 DQSA#7
AH32 FBA_D51 FBA_DQS_RN7 AC34
1.1K_0402_1% 0.01U_0402_25V7K MDA52 AJ33 CMD22 A12 A0
@ @ MDA53 FBA_D52
B AL35 FBA_D53 B
2 MDA54 AM34 CMD23 CS1#_L
2

MDA55 FBA_D54 DQSA0

AM35 FBA_D55 FBA_DQS_WP0 L34 DQSA[7..0] 20,21
MDA56 AF33 H35 DQSA1 CMD24 RAS# RAS#
MDA57 FBA_D56 FBA_DQS_WP1 DQSA2
AE32 FBA_D57 FBA_DQS_WP2 J32
MDA58 AF34 FBA_D58 FBA_DQS_WP3 N31 DQSA3 CMD25 ODT_L
MDA59 AE35 AE31 DQSA4
MDA60 FBA_D59 FBA_DQS_WP4 DQSA5
AE34 FBA_D60 FBA_DQS_WP5 AJ32 CMD26 A6 A7
MDA61 AE33 AJ34 DQSA6
MDA62 FBA_D61 FBA_DQS_WP6 DQSA7
+1.05VS_DGPU
AB32 FBA_D62 FBA_DQS_WP7 AC33 CMD27 CKE_H
MDA63 AC35 FBA_D63
CMD28 RST RST
MMZ1608D301BT_0603 20 mil
1 2 1U_0402_6.3V4Z +FB_AVDD AG27 CMD29 A14 A13
LV11 OPT@ FB_DLLAVDD CLKA0
AF27 FB_PLLAVDD FBA_CLK0 T32 CLKA0 20
1 1 1 1 FBA_CLK0_N T31 CLKA0#
CLKA0# 20 CMD30 A15 BA2
CV147 CV148 CV149 CV150
OPT@ OPT@ OPT@ @ +FB_VREF J27
4.7U_0603_6.3V6K 4.7U_0603_6.3V6K FB_VREF CLKA1
FBA_CLK1 AC31 CLKA1 21
2 2 2 2 CLKA1#
+VRAM_1.5VS 2 1 T30 FBA_DEBUG FBA_CLK1_N AC30 CLKA1# 21
1U_0402_6.3V4Z RV57 10K_0402_5%
OPT@
N11P-GE1-A3 BGA 969P @

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/01 Deciphered Date 2010/01/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MEM Interface A
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Wednesday, April 14, 2010 Sheet 18 of 59
5 4 3 2 1
 5 4 3 2 1

UV1C

Part 3 of 7
MDB[0..63] MDB0 B13 C17 CMDB0
22,23 MDB[0..63] FBC_D0 FBC_CMD0 CMDB0 22
MDB1 D13 B19 CMDB1
FBC_D1 FBC_CMD1 CMDB1 22,23
MDB2 CMDB2
MDB3
A13
A14
FBC_D2
FBC_D3
FBC_CMD2
FBC_CMD3
D18
F21 CMDB3
CMDB2 22
CMDB3 22,23
Mode C - Mirror Mode Mapping
MDB4 C16 A23 CMDB4
FBC_D4 FBC_CMD4 CMDB4 22,23
D MDB5 B16 D21 CMDB5 DATA Bus D
FBC_D5 FBC_CMD5 CMDB5 22,23
MDB6 A17 B23 CMDB6
FBC_D6 FBC_CMD6 CMDB6 22,23
MDB7 D16 E20 CMDB7
CMDB7 22,23
Address 0..31 32..63
MDB8 FBC_D7 FBC_CMD7 CMDB8
C13 FBC_D8 FBC_CMD8 G21 CMDB8 22,23
MDB9 B11 FBC_D9 FBC_CMD9 F20 CMDB9
CMDB9 22,23 CMD0 CKE_L
MDB10 C11 F19 CMDB10
FBC_D10 FBC_CMD10 CMDB10 22,23
MDB11 A11 F23 CMDB11 CMD1 A8 A8
FBC_D11 FBC_CMD11 CMDB11 23
MDB12 C10 A22 CMDB12
FBC_D12 FBC_CMD12 CMDB12 22,23
MDB13 C8 C22 CMDB13 CMD2 CS0#_L
FBC_D13 FBC_CMD13 CMDB13 22,23
MDB14 B8 B17 CMDB14
FBC_D14 FBC_CMD14 CMDB14 22,23
MDB15 A8 F24 CMD3 A7 A6
MDB16 FBC_D15 FBC_CMD15 CMDB16
E8 FBC_D16 FBC_CMD16 C25 CMDB16 23
MDB17 F8 E22 CMDB17 CMD4 A2 A1
FBC_D17 FBC_CMD17 CMDB17 22,23
MDB18 F10 C20 CMDB18
FBC_D18 FBC_CMD18 CMDB18 22,23
MDB19 F9 FBC_D19 FBC_CMD19 B22 CMDB19
CMDB19 22,23 CMD5 A11 A9
MDB20 F12 A19 CMDB20
FBC_D20 FBC_CMD20 CMDB20 22,23
MDB21 D8 D22 CMDB21 CMD6 A5 A4
FBC_D21 FBC_CMD21 CMDB21 22,23
MDB22 D11 D20 CMDB22
FBC_D22 FBC_CMD22 CMDB22 22,23
MDB23 E11 E19 CMD7 A0 A12
MDB24 FBC_D23 FBC_CMD23 CMDB24
D12 FBC_D24 FBC_CMD24 D19 CMDB24 22,23
MDB25 E13 F18 CMDB25 CMD8 CAS# CAS#
FBC_D25 FBC_CMD25 CMDB25 22
MDB26 F13 C19 CMDB26

MEMORY INTERFACE C
FBC_D26 FBC_CMD26 CMDB26 22,23
MDB27 F14 F22 CMDB27 CMD9 BA1 A3
FBC_D27 FBC_CMD27 CMDB27 23
MDB28 F15 C23 CMDB28
FBC_D28 FBC_CMD28 CMDB28 22,23
MDB29 E16 FBC_D29 FBC_CMD29 B20 CMDB29
CMDB29 22,23 CMD10 A9 A11
MDB30 F16 A20 CMDB30
FBC_D30 FBC_CMD30 CMDB30 22,23
MDB31 F17 CMD11 CS0#_H
MDB32 FBC_D31
C D29 FBC_D32 C
MDB33 F27 CMD12 BA0 BA0
MDB34 FBC_D33 DQMB0
F28 FBC_D34 FBC_DQM0 A16 DQMB[7..0] 22,23
MDB35 E28 D10 DQMB1 CMD13 BA2 A15
MDB36 FBC_D35 FBC_DQM1 DQMB2
D26 FBC_D36 FBC_DQM2 F11
MDB37 F25 D15 DQMB3 CMD14 A3 BA1
MDB38 FBC_D37 FBC_DQM3 DQMB4
D24 FBC_D38 FBC_DQM4 D27
MDB39 E25 FBC_D39 FBC_DQM5 D34 DQMB5 CMD15 CS1#_H
MDB40 E32 A34 DQMB6
MDB41 FBC_D40 FBC_DQM6 DQMB7
F32 FBC_D41 FBC_DQM7 D28 CMD16 ODT_H
MDB42 D33
MDB43 FBC_D42
E31 FBC_D43 CMD17 A4 A5
MDB44 C33 B14 DQSB#0
FBC_D44 FBC_DQS_RN0 DQSB#[7..0] 22,23
MDB45 F29 B10 DQSB#1 CMD18 A13 A14
MDB46 FBC_D45 FBC_DQS_RN1 DQSB#2
D30 FBC_D46 FBC_DQS_RN2 D9
MDB47 E29 E14 DQSB#3 CMD19 WE# A10
MDB48 FBC_D47 FBC_DQS_RN3 DQSB#4
B29 FBC_D48 FBC_DQS_RN4 F26
MDB49 C31 FBC_D49 FBC_DQS_RN5 D31 DQSB#5 CMD20 A1 A2
MDB50 C29 A31 DQSB#6
MDB51 FBC_D50 FBC_DQS_RN6 DQSB#7
B31 FBC_D51 FBC_DQS_RN7 A26 CMD21 A10 WE#
MDB52 C32
MDB53 FBC_D52
B32 FBC_D53 CMD22 A12 A0
MDB54 B35
MDB55 FBC_D54 DQSB0
B34 FBC_D55 FBC_DQS_WP0 C14 DQSB[7..0] 22,23 CMD23 CS1#_L
MDB56 A29 A10 DQSB1
MDB57 FBC_D56 FBC_DQS_WP1 DQSB2
B28 FBC_D57 FBC_DQS_WP2 E10 CMD24 RAS# RAS#
MDB58 A28 D14 DQSB3
FBC_D58 FBC_DQS_WP3
B MDB59 C28 FBC_D59 FBC_DQS_WP4 E26 DQSB4 CMD25 ODT_L B
MDB60 C26 D32 DQSB5
MDB61 FBC_D60 FBC_DQS_WP5 DQSB6
D25 FBC_D61 FBC_DQS_WP6 A32 CMD26 A6 A7
MDB62 B25 B26 DQSB7
MDB63 FBC_D62 FBC_DQS_WP7
A25 FBC_D63 CMD27 CKE_H
CMD28 RST RST
+VRAM_1.5VS 1 OPT@2 K27 FBCAL_PD_VDDQ FBC_CLK0 E17 CLKB0
CLKB0 22
RV58 40.2_0402_1% D17 CLKB0# CMD29 A14 A13
FBC_CLK0_N CLKB0# 22
1 OPT@ 2 L27 FBCAL_PU_GND
RV59 40.2_0402_1% D23 CLKB1 CMD30 A15 BA2
FBC_CLK1 CLKB1 23
1 N11M@ 2 M27 FBCAL_TERM_GND FBC_CLK1_N E23 CLKB1#
CLKB1# 23
RV60 40.2_0402_1%
FBC_DEBUG G19 1 OPT@ 2 +VRAM_1.5VS
10K_0402_5% RV61
RV60 N11P@
60.4_0402_1%
N11P-GE1-A3 BGA 969P @

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/01 Deciphered Date 2010/01/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MEM Interface C
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Wednesday, April 14, 2010 Sheet 19 of 59
5 4 3 2 1
 5 4 3 2 1

Memory Partition A - Lower 32 bits MDA[0..63] 18,21

CMDA[30..0] 18,21

DQMA[7..0] 18,21
UV5 UV6
DQSA[7..0] 18,21
+VRAM_1.5VS +FBA_VREF0 M8 E3 MDA3 +FBA_VREF0 M8 E3 MDA18
VREFCA DQL0 VREFCA DQL0 DQSA#[7..0] 18,21
H1 F7 MDA4 H1 F7 MDA19
VREFDQ DQL1 MDA2 VREFDQ DQL1 MDA23
DQL2 F2 DQL2 F2
1

D CMDA7 N3 F8 MDA7 CMDA7 N3 F8 MDA17 Group2 D

RV62 CMDA20 A0 DQL3 MDA0 CMDA20 A0 DQL3 MDA21
P7 A1 DQL4 H3 Group0 P7 A1 DQL4 H3
OPT@ CMDA4 P3 H8 MDA5 CMDA4 P3 H8 MDA16
1.1K_0402_1% CMDA14 A2 DQL5 MDA1 CMDA14 A2 DQL5 MDA20
N2 A3 DQL6 G2 N2 A3 DQL6 G2
CMDA17 MDA6 CMDA17 MDA22
P8 H7 P8 H7
Mode C - Mirror
2

+FBA_VREF0 CMDA6 A4 DQL7 CMDA6 A4 DQL7

P2 A5 P2 A5
CMDA26 R8 CMDA26 R8
A6 A6
Mode Mapping
1

1 CMDA3 R2 D7 MDA29 CMDA3 R2 D7 MDA12

RV63 CV151 CMDA1 A7 DQU0 MDA26 CMDA1 A7 DQU0 MDA11
T8 A8 DQU1 C3 T8 A8 DQU1 C3
OPT@ 0.01U_0402_25V7K CMDA10 R3 C8 MDA31 CMDA10 R3 C8 MDA14
1.1K_0402_1% OPT@ CMDA21 A9 DQU2 MDA28 CMDA21 A9 DQU2 MDA8
2
L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2 DATA Bus
CMDA5 R7 A7 MDA27 Group3 CMDA5 R7 A7 MDA13 Group1
2

CMDA22 A11 DQU4 MDA25 CMDA22 A11 DQU4 MDA10 Address

N7 A12 DQU5 A2 N7 A12 DQU5 A2 0..31 32..63
CMDA18 T3 B8 MDA30 CMDA18 T3 B8 MDA15
A13 DQU6 A13 DQU6
CMDA29 T7 A14 DQU7 A3 MDA24 CMDA29 T7 A14 DQU7 A3 MDA9 CMD0 CKE_L
CMDA30 M7 CMDA30 M7
A15/BA3 +VRAM_1.5VS A15/BA3 +VRAM_1.5VS
CMD1 A8 A8
CMDA12 M2 B2 CMDA12 M2 B2 CMD2 CS0#_L
CMDA9 BA0 VDD CMDA9 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9
CLKA0 CMDA13 M3 G7 CMDA13 M3 G7 CMD3 A7 A6
BA2 VDD BA2 VDD
VDD K2 VDD K2
VDD K8 VDD K8 CMD4 A2 A1
2

VDD N1 VDD N1
RV64 CLKA0 J7 N9 CLKA0 J7 N9 CMD5 A11 A9
18 CLKA0 CK VDD CK VDD
243_0402_1% CLKA0# K7 R1 CLKA0# K7 R1
18 CLKA0# CK VDD CK VDD
OPT@ CMDA0 K9 R9 CMDA0 K9 R9 CMD6 A5 A4
CKE/CKE0 VDD CKE/CKE0 VDD
C C
1

CMD7 A0 A12
CLKA0# CMDA25 K1 A1 CMDA25 K1 A1
CMDA2 ODT/ODT0 VDDQ CMDA2 ODT/ODT0 VDDQ
L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8 CMD8 CAS# CAS#
CMDA24 J3 C1 CMDA24 J3 C1
CMDA8 RAS VDDQ CMDA8 RAS VDDQ CMDA25
K3 CAS VDDQ C9 K3 CAS VDDQ C9 CMD9 BA1 A3
CMDA19 L3 D2 CMDA19 L3 D2
WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9 CMD10 A9 A11
F1 F1 CMDA0
DQSA0 VDDQ DQSA2 VDDQ
F3 DQSL VDDQ H2 F3 DQSL VDDQ H2 CMD11 CS0#_H
DQSA3 C7 H9 DQSA1 C7 H9
DQSU VDDQ DQSU VDDQ

2
CMD12 BA0 BA0
RV98 RV102
DQMA0 E7 A9 DQMA2 E7 A9 10K_0402_5% 10K_0402_5% CMD13 BA2 A15
DQMA3 DML VSS DQMA1 DML VSS OPT@ OPT@
D3 DMU VSS B3 D3 DMU VSS B3
E1 E1 CMD14 A3 BA1

1
VSS VSS
VSS G8 VSS G8
DQSA#0 G3 DQSL VSS J2 DQSA#2 G3 DQSL VSS J2 CMD15 CS1#_H
DQSA#3 B7 J8 DQSA#1 B7 J8
DQSU VSS DQSU VSS
VSS M1 VSS M1 CMD16 ODT_H
VSS M9 VSS M9
VSS P1 VSS P1 CMD17 A4 A5
CMDA28 T2 P9 CMDA28 T2 P9
RESET VSS RESET VSS
VSS T1 VSS T1 CMD18 A13 A14
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9
CMD19 WE# A10
1

1
B J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 CMD20 A1 A2 B
1

RV65 RV66 L1 B9 RV67 L1 B9

OPT@ NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1 CMD21 A10 WE#
10K_0402_5% OPT@ L9 D8 OPT@ L9 D8
NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2 CMD22 A12 A0
2

2
VSSQ VSSQ
E8 E8
2

VSSQ VSSQ
VSSQ F9 VSSQ F9 CMD23 CS1#_L
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9 CMD24 RAS# RAS#
96-BALL 96-BALL CMD25 ODT_L
SDRAM DDR3 SDRAM DDR3
H5TQ1G63BFR-12C FBGA 1.5V H5TQ1G63BFR-12C FBGA 1.5V CMD26 A6 A7
@
@ CMD27 CKE_H
+VRAM_1.5VS +VRAM_1.5VS CMD28 RST RST
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z CMD29 A14 A13
1 1 1 1 1 1 1 1 1 1 1 1 1 1 CMD30 A15 BA2
CV152 CV153 CV154 CV155 CV156 CV157 CV158 CV159 CV160 CV161 CV162 CV163 CV164 CV165
OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@
2 2 2 2 2 2 2 2 2 2 2 2 2 2
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/01 Deciphered Date 2010/01/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM A Lower
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Wednesday, April 14, 2010 Sheet 20 of 59
5 4 3 2 1
 5 4 3 2 1

Memory Partition A - Upper 32 bits

MDA[0..63] 18,20

CMDA[30..0] 18,20
UV8 UV7
+VRAM_1.5VS
DQMA[7..0] 18,20
+FBA_VREF1 M8 E3 MDA39 +FBA_VREF1 M8 E3 MDA58
VREFCA DQL0 MDA35 VREFCA DQL0 MDA59
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 DQSA[7..0] 18,20
1
F2 MDA37 F2 MDA56
RV68 CMDA22 DQL2 MDA33 CMDA22 DQL2 MDA63
D N3 A0 DQL3 F8 N3 A0 DQL3 F8 DQSA#[7..0] 18,20 D
OPT@ CMDA4 P7 H3 MDA38 Group4 CMDA4 P7 H3 MDA57 Group7
1.1K_0402_1% CMDA20 A1 DQL4 MDA32 CMDA20 A1 DQL4 MDA61
P3 A2 DQL5 H8 P3 A2 DQL5 H8
CMDA9 N2 G2 MDA36 CMDA9 N2 G2 MDA60
2

+FBA_VREF1 CMDA6 A3 DQL6 MDA34 CMDA6 A3 DQL6 MDA62

P8 A4 DQL7 H7 P8 A4 DQL7 H7
CMDA17 CMDA17
P2 A5 P2 A5 Mode C - Mirror Mode Mapping
1

1 CMDA3 R8 CMDA3 R8
RV69 CV166 CMDA26 A6 MDA42 CMDA26 A6 MDA49
R2 A7 DQU0 D7 R2 A7 DQU0 D7
OPT@ 0.01U_0402_25V7K CMDA1 T8 C3 MDA45 CMDA1 T8 C3 MDA53
1.1K_0402_1% OPT@ CMDA5 A8 DQU1 MDA40 CMDA5 A8 DQU1 MDA51
R3 A9 DQU2 C8 R3 A9 DQU2 C8
2 CMDA19 MDA44 CMDA19 MDA55
L7 C2 L7 C2 DATA Bus
2

CMDA10 A10/AP DQU3 MDA41 CMDA10 A10/AP DQU3 MDA48

R7 A11 DQU4 A7 Group5 R7 A11 DQU4 A7 Group6
CMDA7 N7 A2 MDA47 CMDA7 N7 A2 MDA54 Address 0..31 32..63
CMDA29 A12 DQU5 MDA43 CMDA29 A12 DQU5 MDA50
T3 A13 DQU6 B8 T3 A13 DQU6 B8
CMDA18 T7 A14 DQU7 A3 MDA46 CMDA18 T7 A14 DQU7 A3 MDA52 CMD0 CKE_L
CMDA13 M7 CMDA13 M7
A15/BA3 +VRAM_1.5VS A15/BA3 +VRAM_1.5VS
CMD1 A8 A8
CMDA12 M2 B2 CMDA12 M2 B2 CMD2 CS0#_L
CMDA14 BA0 VDD CMDA14 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9
CLKA1 CMDA30 M3 G7 CMDA30 M3 G7 CMD3 A7 A6
BA2 VDD BA2 VDD
VDD K2 VDD K2
VDD K8 VDD K8 CMD4 A2 A1
2

VDD N1 VDD N1
RV70 CLKA1 J7 N9 CLKA1 J7 N9 CMD5 A11 A9
18 CLKA1 CK VDD CK VDD
243_0402_1% CLKA1# K7 R1 CLKA1# K7 R1
18 CLKA1# CK VDD CK VDD
OPT@ CMDA27 K9 R9 CMDA27 K9 R9 CMD6 A5 A4
CKE/CKE0 VDD CKE/CKE0 VDD
C C
1

CMD7 A0 A12
CLKA1# CMDA16 K1 A1 CMDA16 K1 A1
CMDA11 ODT/ODT0 VDDQ CMDA11 ODT/ODT0 VDDQ
L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8 CMD8 CAS# CAS#
CMDA24 J3 C1 CMDA24 J3 C1
CMDA8 RAS VDDQ CMDA8 RAS VDDQ
K3 CAS VDDQ C9 K3 CAS VDDQ C9 CMD9 BA1 A3
CMDA21 L3 D2 CMDA21 L3 D2
WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9 CMD10 A9 A11
VDDQ F1 VDDQ F1
DQSA4 F3 H2 DQSA7 F3 H2 CMD11 CS0#_H
DQSA5 DQSL VDDQ DQSA6 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9
CMD12 BA0 BA0
DQMA4 E7 A9 DQMA7 E7 A9 CMD13 BA2 A15
CMDA27 DQMA5 DML VSS DQMA6 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3
VSS E1 VSS E1 CMD14 A3 BA1
VSS G8 VSS G8
CMDA16 DQSA#4 G3 DQSL VSS J2 DQSA#7 G3 DQSL VSS J2 CMD15 CS1#_H
DQSA#5 B7 J8 DQSA#6 B7 J8
DQSU VSS DQSU VSS
VSS M1 VSS M1 CMD16 ODT_H
VSS M9 VSS M9
2

VSS P1 VSS P1 CMD17 A4 A5

RV100 RV104 CMDA28 T2 P9 CMDA28 T2 P9
10K_0402_5% 10K_0402_5% RESET VSS RESET VSS
VSS T1 VSS T1 CMD18 A13 A14
OPT@ OPT@ L8 T9 L8 T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
CMD19 WE# A10
1

1
B J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 CMD20 A1 A2 B
RV71 L1 B9 RV72 L1 B9
NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1 CMD21 A10 WE#
OPT@ L9 D8 OPT@ L9 D8
NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2 CMD22 A12 A0
2

2
VSSQ VSSQ
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9 CMD23 CS1#_L
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9 CMD24 RAS# RAS#
96-BALL 96-BALL CMD25 ODT_L
SDRAM DDR3 SDRAM DDR3
H5TQ1G63BFR-12C FBGA 1.5V H5TQ1G63BFR-12C FBGA 1.5V CMD26 A6 A7
@ @
CMD27 CKE_H
+VRAM_1.5VS +VRAM_1.5VS
CMD28 RST RST
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
CMD29 A14 A13
1 1 1 1 1 1 1 1 1 1 1 1 1 1
CV167 CV168 CV169 CV170 CV171 CV172 CV173 CV174 CV175 CV176 CV177 CV178 CV179 CV180 CMD30 A15 BA2
OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@ OPT@
2 2 2 2 2 2 2 2 2 2 2 2 2 2
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/01 Deciphered Date 2010/01/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM A Upper
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Wednesday, April 14, 2010 Sheet 21 of 59
5 4 3 2 1
 5 4 3 2 1

Memory Partition C - Lower 32 bits MDB[0..63] 19,23

CMDB[30..0] 19,23

DQMB[7..0] 19,23

DQSB[7..0] 19,23
+VRAM_1.5VS UV9 UV10
DQSB#[7..0] 19,23
+FBB_VREF0 M8 E3 MDB3 +FBB_VREF0 M8 E3 MDB22
VREFCA DQL0 VREFCA DQL0
1
D H1 F7 MDB7 H1 F7 MDB16 D
RV73 VREFDQ DQL1 MDB1 VREFDQ DQL1 MDB18
DQL2 F2 DQL2 F2
CMDB7 N3 F8 MDB4 Group0 CMDB7 N3 F8 MDB19
1.1K_0402_1% CMDB20 A0 DQL3 MDB2 CMDB20 A0 DQL3 MDB23
P7 A1 DQL4 H3 P7 A1 DQL4 H3 Group2
8PCS@ CMDB4 MDB6 CMDB4 MDB17
P3 H8 P3 H8
Mode C - Mirror
2

+FBB_VREF0 CMDB14 A2 DQL5 MDB0 CMDB14 A2 DQL5 MDB20

N2 A3 DQL6 G2 N2 A3 DQL6 G2
CMDB17 P8 H7 MDB5 CMDB17 P8 H7 MDB21
A4 DQL7 A4 DQL7
Mode Mapping
1

1 CMDB6 P2 CMDB6 P2
RV74 CV181 CMDB26 A5 CMDB26 A5
R8 A6 R8 A6
0.01U_0402_25V7K CMDB3 R2 D7 MDB28 CMDB3 R2 D7 MDB13
1.1K_0402_1% 8PCS@ CMDB1 A7 DQU0 MDB24 CMDB1 A7 DQU0 MDB10
2
T8 A8 DQU1 C3 T8 A8 DQU1 C3 DATA Bus
8PCS@ CMDB10 R3 C8 MDB31 CMDB10 R3 C8 MDB14
2

CMDB21 A9 DQU2 MDB25 CMDB21 A9 DQU2 MDB9 Address

L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2 0..31 32..63
CMDB5 R7 A7 MDB29 Group3 CMDB5 R7 A7 MDB12 Group1
A11 DQU4 A11 DQU4
CMDB22 N7 A12 DQU5 A2 MDB27 CMDB22 N7 A12 DQU5 A2 MDB8 CMD0 CKE_L
CMDB18 T3 B8 MDB30 CMDB18 T3 B8 MDB15
CMDB29 A13 DQU6 MDB26 CMDB29 A13 DQU6 MDB11
T7 A14 DQU7 A3 T7 A14 DQU7 A3 CMD1 A8 A8
CMDB30 M7 CMDB30 M7
A15/BA3 +VRAM_1.5VS A15/BA3 +VRAM_1.5VS CMD2 CS0#_L
CMDB12 M2 B2 CMDB12 M2 B2 CMD3 A7 A6
CMDB9 BA0 VDD CMDB9 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9
CLKB0 CMDB13 M3 G7 CMDB13 M3 G7 CMD4 A2 A1
BA2 VDD BA2 VDD
VDD K2 VDD K2
VDD K8 VDD K8 CMD5 A11 A9
2

VDD N1 VDD N1
RV75 CLKB0 J7 N9 CLKB0 J7 N9 CMD6 A5 A4
19 CLKB0 CK VDD CK VDD
C 243_0402_1% CLKB0# K7 R1 CLKB0# K7 R1 C
19 CLKB0# CK VDD CK VDD
8PCS@ CMDB0 K9 R9 CMDB0 K9 R9 CMD7 A0 A12
CKE/CKE0 VDD CKE/CKE0 VDD
1

CMD8 CAS# CAS#

CLKB0# CMDB25 K1 A1 CMDB25 K1 A1
CMDB2 ODT/ODT0 VDDQ CMDB2 ODT/ODT0 VDDQ
L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8 CMD9 BA1 A3
CMDB24 J3 C1 CMDB24 J3 C1
RAS VDDQ RAS VDDQ
CMDB8 K3 CAS VDDQ C9 CMDB8 K3 CAS VDDQ C9 CMD10 A9 A11
CMDB19 L3 D2 CMDB19 L3 D2
WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9 CMD11 CS0#_H
VDDQ F1 VDDQ F1
DQSB0 F3 H2 DQSB2 F3 H2 CMDB25 CMD12 BA0 BA0
DQSB3 DQSL VDDQ DQSB1 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9
CMD13 BA2 A15
CMDB0
DQMB0 E7 A9 DQMB2 E7 A9 CMD14 A3 BA1
DQMB3 DML VSS DQMB1 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3
VSS E1 VSS E1 CMD15 CS1#_H

2
VSS G8 VSS G8
DQSB#0 G3 J2 DQSB#2 G3 J2 RV111 CMD16 ODT_H
DQSB#3 DQSL VSS DQSB#1 DQSL VSS RV106 10K_0402_5%
B7 DQSU VSS J8 B7 DQSU VSS J8
M1 M1 10K_0402_5% 8PCS@ CMD17 A4 A5
VSS VSS 8PCS@
M9 M9

1
VSS VSS
VSS P1 VSS P1 CMD18 A13 A14
CMDB28 T2 P9 CMDB28 T2 P9
RESET VSS RESET VSS
VSS T1 VSS T1 CMD19 WE# A10
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9
B CMD20 A1 A2 B
1

1
J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 CMD21 A10 WE#
1

RV76 RV77 L1 B9 RV78 L1 B9

NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1 CMD22 A12 A0
10K_0402_5% L9 D8 L9 D8
8PCS@ NCZQ1 VSSQ 8PCS@ NCZQ1 VSSQ
E2 E2 CMD23 CS1#_L
2

2
8PCS@ VSSQ VSSQ
E8 E8
2

VSSQ VSSQ
VSSQ F9 VSSQ F9 CMD24 RAS# RAS#
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9 CMD25 ODT_L
96-BALL 96-BALL CMD26 A6 A7
SDRAM DDR3 SDRAM DDR3
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96 CMD27 CKE_H
@ @
CMD28 RST RST
+VRAM_1.5VS +VRAM_1.5VS CMD29 A14 A13
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z CMD30 A15 BA2
1 1 1 1 1 1 1 1 1 1 1 1 1 1
CV182 CV183 CV184 CV185 CV186 CV187 CV188 CV189 CV190 CV191 CV192 CV193 CV194 CV195

8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 0.1U_0402_16V4Z 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 0.1U_0402_16V4Z
2 2 2 2 2 2 2 8PCS@ 2 2 2 2 2 2 2 8PCS@
A 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/01 Deciphered Date 2010/01/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM C Lower
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Wednesday, April 14, 2010 Sheet 22 of 59
5 4 3 2 1
 5 4 3 2 1

Memory Partition C - Upper 32 bits MDB[0..63] 19,22

CMDB[30..0] 19,22
UV11 UV12

+VRAM_1.5VS DQMB[7..0] 19,22

+FBB_VREF1 M8 E3 MDB39 +FBB_VREF1 M8 E3 MDB56
VREFCA DQL0 MDB33 VREFCA DQL0 MDB63
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 DQSB[7..0] 19,22
D F2 MDB38 F2 MDB57 D
DQL2 DQL2
1
CMDB22 N3 F8 MDB32 CMDB22 N3 F8 MDB60
A0 DQL3 A0 DQL3 DQSB#[7..0] 19,22
RV79 CMDB4 P7 H3 MDB36 Group4 CMDB4 P7 H3 MDB59 Group7
CMDB20 A1 DQL4 MDB34 CMDB20 A1 DQL4 MDB61
P3 A2 DQL5 H8 P3 A2 DQL5 H8
1.1K_0402_1% CMDB9 N2 G2 MDB37 CMDB9 N2 G2 MDB58
8PCS@ CMDB6 A3 DQL6 MDB35 CMDB6 A3 DQL6 MDB62
P8 H7 P8 H7
2

+FBB_VREF1 CMDB17 A4 DQL7 CMDB17 A4 DQL7

P2 A5 P2 A5
CMDB3 CMDB3
R8 A6 R8 A6 Mode C - Mirror Mode Mapping
1

1 CMDB26 R2 D7 MDB42 CMDB26 R2 D7 MDB48

RV80 CV196 CMDB1 A7 DQU0 MDB43 CMDB1 A7 DQU0 MDB55
T8 A8 DQU1 C3 T8 A8 DQU1 C3
0.01U_0402_25V7K CMDB5 R3 C8 MDB41 CMDB5 R3 C8 MDB49 DATA Bus
1.1K_0402_1% 8PCS@ CMDB19 A9 DQU2 MDB46 CMDB19 A9 DQU2 MDB52
L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2
8PCS@ 2 CMDB10 MDB40 CMDB10 MDB51 Address
R7 A7 Group5 R7 A7 Group6 0..31 32..63
2

CMDB7 A11 DQU4 MDB45 CMDB7 A11 DQU4 MDB54

N7 A12 DQU5 A2 N7 A12 DQU5 A2
CMDB29 T3 A13 DQU6 B8 MDB44 CMDB29 T3 A13 DQU6 B8 MDB50 CMD0 CKE_L
CMDB18 T7 A3 MDB47 CMDB18 T7 A3 MDB53
CMDB13 A14 DQU7 CMDB13 A14 DQU7
M7 A15/BA3 M7 A15/BA3 CMD1 A8 A8
+VRAM_1.5VS +VRAM_1.5VS
CMD2 CS0#_L
CMDB12 M2 B2 CMDB12 M2 B2
CMDB14 BA0 VDD CMDB14 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9 CMD3 A7 A6
CMDB30 M3 G7 CMDB30 M3 G7
CLKB1 BA2 VDD BA2 VDD
VDD K2 VDD K2 CMD4 A2 A1
VDD K8 VDD K8
VDD N1 VDD N1 CMD5 A11 A9
2

CLKB1 J7 N9 CLKB1 J7 N9
19 CLKB1 CK VDD CK VDD
RV81 CLKB1# K7 R1 CLKB1# K7 R1 CMD6 A5 A4
19 CLKB1# CK VDD CK VDD
C 243_0402_1% CMDB27 K9 R9 CMDB27 K9 R9 C
CKE/CKE0 VDD CKE/CKE0 VDD
8PCS@ CMD7 A0 A12
1

CMDB16 K1 A1 CMDB16 K1 A1 CMD8 CAS# CAS#

CLKB1# CMDB11 ODT/ODT0 VDDQ CMDB11 ODT/ODT0 VDDQ
L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8
CMDB24 J3 C1 CMDB24 J3 C1 CMD9 BA1 A3
CMDB8 RAS VDDQ CMDB8 RAS VDDQ
K3 CAS VDDQ C9 K3 CAS VDDQ C9
CMDB21 L3 WE VDDQ D2 CMDB21 L3 WE VDDQ D2 CMD10 A9 A11
VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 CMD11 CS0#_H
DQSB4 F3 H2 DQSB7 F3 H2
DQSB5 DQSL VDDQ DQSB6 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 CMD12 BA0 BA0
CMD13 BA2 A15
DQMB4 E7 A9 DQMB7 E7 A9
DQMB5 DML VSS DQMB6 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3 CMD14 A3 BA1
CMDB27 E1 E1
VSS VSS
VSS G8 VSS G8 CMD15 CS1#_H
DQSB#4 G3 J2 DQSB#7 G3 J2
CMDB16 DQSB#5 DQSL VSS DQSB#6 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8 CMD16 ODT_H
VSS M1 VSS M1
VSS M9 VSS M9 CMD17 A4 A5
2

VSS P1 VSS P1
RV108 RV112 CMDB28 T2 P9 CMDB28 T2 P9 CMD18 A13 A14
10K_0402_5% 10K_0402_5% RESET VSS RESET VSS
VSS T1 VSS T1
8PCS@ 8PCS@ L8 T9 L8 T9 CMD19 WE# A10
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1

B CMD20 A1 A2 B
1

1
J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1
RV82 L1 B9 RV83 L1 B9 CMD21 A10 WE#
NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1
L9 NCZQ1 VSSQ D8 L9 NCZQ1 VSSQ D8 CMD22 A12 A0
8PCS@ E2 8PCS@ E2
2

2
VSSQ VSSQ
VSSQ E8 VSSQ E8 CMD23 CS1#_L
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 CMD24 RAS# RAS#
VSSQ G9 VSSQ G9
CMD25 ODT_L
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 CMD26 A6 A7
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
@ @ CMD27 CKE_H
+VRAM_1.5VS CMD28 RST RST
+VRAM_1.5VS +VRAM_1.5VS
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z CMD29 A14 A13
1 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

+
1 1 1 1 1 1 1 CMD30 A15 BA2
CV122 1 1 1 1 1 1 1 CV205 CV206 CV207 CV208 CV209 CV210 CV211
330U_D2_2V_Y CV198 CV199 CV200 CV201 CV202 CV203 CV204
8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 0.1U_0402_16V4Z
2 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 0.1U_0402_16V4Z 2 2 2 2 2 2 2 8PCS@
8PCS@ 2 2 2 2 2 2 2 8PCS@ 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/01 Deciphered Date 2010/01/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM C Upper
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Wednesday, April 14, 2010 Sheet 23 of 59
5 4 3 2 1
 5 4 3 2 1

Physical Logical Logical Logical Logical

Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
+3VS_DGPU
ROM_SO +3VS_DGPU XCLK_417 FB_0_BAR_SIZE SMB_ALT_ADDR VGA_DEVICE
ROM_SCLK +3VS_DGPU PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLLEN_TERM
Need change to 20k for LP1
ROM_SI +3VS_DGPU RAMCFG[3] RAMCFG[2] RAMCFG[1] RAMCFG[0]

2
RV87 RV85 RV86 STRAP2 +3VS_DGPU PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
45.3K_0402_1% 34.8K_0402_1% 20K_0402_1%
OPT@ OPT@ LP1@ STRAP1 +3VS_DGPU 3GIO_PADCFG[3] 3GIO_PADCFG[2] 3GIO_PADCFG[1] 3GIO_PADCFG[0]
D RV86 D

1
34.8K_0402_1% STRAP0 +3VS_DGPU USER[3] USER[2] USER[1] USER[0]
14 STRAP0 STRAP0
14 STRAP1 STRAP1 LP@
14 STRAP2 STRAP2

Resistor Values Pull-up to +3VS Pull-down to Gnd VGA power up sequence

2
RV84 RV88 RV89 5K 1000 0000
only PU, do not need PD 45.3K_0402_1% 34.8K_0402_1% 4.99K_0402_1% +3VS_DGPU
0211 @ @ N11M@ 10K 1001 0001
1 VGA_CORE

1
15K 1010 0010
1.5VS_VRAM

+3VS_DGPU
20K 1011 0011
25K 1100 0100
30K 1101 0101
35K 1110 0110
2

2
RV90 RV92 RV92 45K 1111 0111
2

4.99K_0402_1% 15K_0402_1% 15K_0402_1%

only PU, do not need PD @ RV91
0212 4.99K_0402_1% N11M@ LP@
1

@ 1
C C
1

14 ROM_SI ROM_SI DeviceID ROM_SCLK STRAP2

14 ROM_SO ROM_SO
14 ROM_SCLK ROM_SCLK
N11M-GE2 Pull up 15K Pull down 5K
2

RV93 N11P-LP1 Pull down 15K Pull up 20K

15K_0402_1% RV94 RV95
@ 10K_0402_1%
OPT@
15K_0402_1%
N11P-LP TBD TBD SUB_VENDOR XCLK_417
1

LP1@
1

0 No VBIOS ROM (Default) 0 277MHz (Default)

this is VRAM strap pin,
we will add it into x76 bom 1 BIOS ROM is present 1 Reserved

FB_0_BAR_SIZE USER Straps

0 256MB (Default) User[3:0]

1 Reserved 1000-1100 Customer defined

B B

ROM SI 3GIO_PADCFG PEX_PLL_EN_TERM

512M SA000032400 64MX16 H5TQ1G63BFR-12C PD 15K 3GIO_PADCFG[3:0] 0
Hynix Disable (Default)
1G SA00003VS00 128MX16 H5TQ2G63BFR PD 35K
512M SA000035700 64Mx16 K4W1G1646E-HC12 PD 20K 1110 Notebook Default 1 Enable
Samsung
1G SA00003MQ00 128M16 K4W2G1646B-HC12 PD 45K
SLOT_CLOCK_CFG
ROM_SCLK 0 GPU and MCH don't share a common reference clock

N11M GE2 PU 15K 1 GPU and MCH share a common reference clock (Default)
N11P LP1 PD 15K
SMBUS_ALT_ADDR VGA_DEVICE
N11P LP PU 15K
0 0x9E (Default) 0 3D Device

A STRAP2 1 0x9C (Multi-GPU usage) 1 VGA Device (Default) A

N11M GE2 PD 5K
N11P LP1 PU 20K Security Classification Compal Secret Data Compal Electronics, Inc.
N11P LP PU35K Issued Date 2009/01/01 Deciphered Date 2010/01/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MSIC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Wednesday, April 14, 2010 Sheet 24 of 59
5 4 3 2 1
 A B C D E F G H

Clock Generator For SED

+3VS_CK505
For SED
FBMH1608HM601-T_0603 For SED
+3VS 1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z +3VS_CK505

1
R100 1 1 1 1 For SED

1
FBMH1608HM601-T_0603 R110

2
C209 C210 C211 C212 C251 +VTT 1 2 10U_0805_10V4Z 0.1U_0402_16V4Z +1.05VS_CK505 10K_0402_5%
R401 47P_0402_50V8J R101 1 1 1 1

1
0_0603_5% 2 2 2 2 C252

2
@ 10U_0805_10V4Z 0.1U_0402_16V4Z C219 C220 C221 C222 47P_0402_50V8J CK_PWRGD

2
2 2 2 2
FBMH1608HM601-T_0603 0.1U_0402_16V4Z 0.1U_0402_16V4Z

1
0.1U_0402_16V4Z D
+1.5VS 1 2 +1.5VS_CK505
R120 Q35 2
2N7002_SOT23-3 G CLK_ENABLE# 54
1 1 1
For SED S

3
1
C213 C214 C215 1
2 2 2
For RF
0.1U_0402_16V4Z 0.1U_0402_16V4Z
@
CPU_SEL C484 1 2 +3VS_CK505
+1.05VS_CK505 Silego Have Internal Pull-Up
33P_0402_50V8K
+1.05VS_CK505 +3VS_CK505
H_STP_CPU# 10K_0402_5% 2 1 R105
+1.5VS_CK505
U5
+3VS_CK505
1 32 PM_SMBCLK
VDD_USB_48 SCL PM_SMBCLK 11,12,29,39
2 31 PM_SMBDATA
VSS_48M SDA PM_SMBDATA 11,12,29,39
3 30 CPU_SEL 1 2
29 CLK_DOT DOT_96 REF_0/CPU_SEL CLK_14M_PCH 29
4 29 R102 33_0402_5%
29 CLK_DOT# DOT_96# VDD_REF CLK_XTAL_IN
5 28
R391 1 OPT@ 27M_CLK_R VDD_27 XTAL_IN CLK_XTAL_OUT
13 27M_CLK 2 33_0402_5% 6 27 10K_0402_5% 2 @ 1 R119 +VTT
R143 1 OPT@ 27M_SSC_R 27MHZ XTAL_OUT
13 27M_SSC 2 33_0402_5% 7 26
R144 1 27MHZ_SS VSS_REF CK_PWRGD
41 CLK_SD_48M 2 33_0402_5% 8 25
USB_48 CKPWRGD/PD#
9 24 CPU_SEL 10K_0402_5% 2 1 R106
VSS_27M VDD_CPU
29 CLK_SATA 10 23 CLK_BCLK 29
SATA CPU_0
29 CLK_SATA# 11 22 CLK_BCLK# 29
IDT Have Internal Pull-Down
SATA# CPU_0#
12 21
VSS_SRC VSS_CPU CLK_XTAL_OUT
29 PCH_CLK_DMI 13 20
SRC_1 CPU_1
29 PCH_CLK_DMI# 14 19
SRC_1# CPU_1#
15
VDD_SRC_IO VDD_CPU_IO
18 Y1 CPU_SEL CPU_0/0# CPU_1/1#
H_STP_CPU# 16 17 CLK_XTAL_IN 1 2
CPU_STOP# VDD_SRC +1.5VS_CK505
33
TGND 2 14.318MHZ_16PF_7A14300083 2 0 (Default) 133MHz 133MHz
RTM890N-631-GRT QFN 32P C223 C224
22P_0402_50V8J
1 1
22P_0402_50V8J 1 100MHz 100MHz
change PN to SA00003HQ10 in DVT 0301
change to SA00002XY00 for cost down 0324
Main source:SA00003HQ10, 2nd source:SA00003MF00

2 2
+LCD_VDD

LCD_TXOUT0+
31 LCD_TXOUT0+

1
LCD_TXOUT0- Reserve for EMI request R107
31 LCD_TXOUT0- +3VS
150_0603_5%
LCD_TXOUT1+
31 LCD_TXOUT1+
1 2

1
LCD_TXOUT1- R78 0_0402_5% R108 +3VS
31 LCD_TXOUT1-
L55 @ 100K_0402_5%
W=60mils

6
31 LCD_TXOUT2+ LCD_TXOUT2+ 32 USB20_N11 1 2 USB20_N11_R
1 2
2
LCD_TXOUT2- Q1A C228
31 LCD_TXOUT2-

2
32 USB20_P11 4 3 USB20_P11_R 2N7002DW-T/R7_SOT363-6 2 0.1U_0402_16V7K

3
4 3 S
LCD_TXCLK+ Q59
31 LCD_TXCLK+ 12 G
WCM-2012-900T_0805 1 R109 2

1
LCD_TXCLK- 47K_0402_5% 1
31 LCD_TXCLK-

3
1 2 AO3413_SOT23 D

1
LCD_CLK R96 0_0402_5% C229 +LCD_VDD
31 LCD_CLK
0.01U_0402_25V7K W=60mils
LCD_DATA LCD_ENVDD 5 2
31 LCD_DATA
Q1B 1
2N7002DW-T/R7_SOT363-6

4
C233

2
0.1U_0402_16V4Z
1 2 INV_PWM_R 1 @ 2 +3VS +LCD_VDD INVPWR_B+ R112 2
31 PCH_PWM INVT_PWM 43
R332 0_0402_5% R368 0_0402_5% 100K_0402_5%
1 2 LCD_ENVDD
31 UMA_ENVDD
R350 0_0402_5%

1
1 2 EC_ENBKL
31 UMA_ENBKL EC_ENBKL 43
R357 0_0402_5% C255 C258 C256
LVDS CONN & USB Camera + Dig Mic
Close to LVDS Connector
680P_0402_50V7K

680P_0402_50V7K

680P_0402_50V7K

1
1

1
2

2 B+ INVPWR_B+
JLVDS @
1 2 L19 1 2 0_0805_5%
3 1 2 LCD_TXOUT2- 3
3 4
3 4 LCD_TXOUT2+
5 6
5 6 L16
7 8 1 2
7 8 LCD_TXOUT1- FBMA-L11-201209-221LMA30T_0805
9 10
9 10 LCD_TXOUT1+
11 12
USB20_P11_R 11 12
USB20_N11_R
13
13 14
14
LCD_TXOUT0-
0308_Reserve L10 and install L11.
15 16
15 16 LCD_TXOUT0+
17 18
17 18
19 20
19 20 LCD_TXCLK-
21 22
DMIC_DAT 21 22 LCD_TXCLK+ B+
42 DMIC_DAT 23 24
DMIC_CLK 23 24
42 DMIC_CLK 25
25 26
26 For EMI
C472 27 28 +3VS
27 28
1 2INV_PWM_R 29 30
BKOFF# 680P_0402_50V7K 29 30
31 32

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
43 BKOFF# 31 32
33 34 1 1 1 1
33 34 C236 C268 C489 C490
+5VS 35 36
100P_0402_50V8J LCD_CLK 35 36
2 1 C1401 @ 37 38
100P_0402_50V8J LCD_DATA 37 38
2 1 C1402 @ 39 40 @ @ @ @
39 40 2 2 2 2
41 42
BKOFF# GND1GND2
ACES_87142-4041-BS
1

CONN@
R124
10K_0402_5%
2

、25
Must close JLVDS1pin 23、
DMIC_CLK

DMIC_DAT

1 1
C302 C312

220P_0402_25V8J 220P_0402_25V8J
2 2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CCLK GEN/LVDS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Thursday, April 15, 2010 Sheet 25 of 57
A B C D E F G H
 A B C D E

1
D3 @ D4 @ D5 @
RV1528 1 CRT@ 2 0_0402_5% +3VS
13 VGA_CRT_R
RV1529 1 CRT@ 2 0_0402_5% +5VS
13 VGA_CRT_G +CRT_VCC_R +CRT_VCC
D6
13 VGA_CRT_B RV1530 1 CRT@ 2 0_0402_5% DAN217_SC59 DAN217_SC59 DAN217_SC59 2 F1

3
1 1 2
1 3 RB491D_SOT23-3 1 1
1.1A_6V_MINISMDC110F-2
C237
@ 0.1U_0402_16V4Z
UMA_CRT_R RV1532 2
31 UMA_CRT_R 1 2 0_0402_5% UMA_CRT_R_R L3 1 2 NBQ100505T-800Y_0402 CRT_R_L

31 UMA_CRT_G UMA_CRT_G RV1533 1 2 0_0402_5% UMA_CRT_G_R L4 1 2 NBQ100505T-800Y_0402 CRT_G_L

31 UMA_CRT_B UMA_CRT_B RV1534 1 2 0_0402_5% UMA_CRT_B_R L5 1 2 NBQ100505T-800Y_0402 CRT_B_L

JCRT
6
11
R138 R139 R140 CRT_R_L 1

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C
150_0402_1%

150_0402_1%

150_0402_1%
1 1 1 1 1 1 7

1
CRT_DDC_DAT 12
C238 C239 C240 C241 C242 C243 CRT_G_L 2
8
2 2 2 2 2 2 HSYNC 13
CRT_B_L 3

2
+CRT_VCC 9
VSYNC 14
4
10
CRT_DDC_CLK 15
5

16 GND
17 GND
2 2
+CRT_VCC
SUYIN_070546FR015S265ZR
1 2
C244 0.1U_0402_16V4Z CONN@
RV1531 CRT@
1 2 0_0402_5% 2 1
13 VGA_CRT_HSYNC
R141 10K_0402_5%

5
1
OE#
P
UMA_CRT_HSYNC RV1535 1 2 0_0402_5% UMA_CRT_HSYNC_R 2 4 D_CRT_HSYNC 1 2 HSYNC
31 UMA_CRT_HSYNC A Y
+CRT_VCC L6 10_0402_5%

G
U6
SN74AHCT1G125GW_SOT353-5

5
1
OE#
P
UMA_CRT_VSYNC RV1537 1 2 0_0402_5% UMA_CRT_VSYNC_R 2 4 D_CRT_VSYNC 1 2 VSYNC
31 UMA_CRT_VSYNC A Y L7 10_0402_5%

10P_0402_50V8J

10P_0402_50V8J
1 1

G
U7
SN74AHCT1G125GW_SOT353-5 C245 C246

3
RV1536 CRT@
1 2 0_0402_5% @ @
13 VGA_CRT_VSYNC 2 2

3 3

+CRT_VCC

+3VS

2
R153 R159
4.7K_0402_5% 4.7K_0402_5%
RV1540 CRT@
1 2 0_0402_5%
13 VGA_DDCCLK

1
2
Q205A
31 UMA_CRT_CLK UMA_CRT_CLK RV1542 1 2 0_0402_5% 5 1 6 CRT_DDC_CLK

2N7002DW-T/R7_SOT363-6
Q205B
31 UMA_CRT_DATA UMA_CRT_DATA RV1543 1 2 0_0402_5% 4 3 CRT_DDC_DAT
1 1
1 1 2N7002DW-T/R7_SOT363-6
C284 C283
13 VGA_DDCDATA RV1541 CRT@
1 2 0_0402_5% C282 C285 470P_0402_50V8J 470P_0402_50V8J
33P_0402_50V8K 33P_0402_50V8K @ 2 2 @
@ 2 2 @

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Wednesday, April 14, 2010 Sheet 26 of 57
A B C D E
 5 4 3 2 1

D D

+3VS
+3VS
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 1 1 1 1 1 1

1
C314 C371 C292 C317 C339 C340 C319 C315
HDMI@ HDMI@ HDMI@ HDMI@ HDMI@ HDMI@ HDMI@ HDMI@ R303
10U_0805_10V4Z 0.1U_0402_16V4Z 10K_0402_5%
2 2 2 2 2 2 2 2 HDMI@
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

2
OE# +HDMI_5V_OUT

1
D
U18 Q25 2HDMI_HPD
VGA_DVI_TXC- 1 2 HDMI_R_CK- 2N7002_SOT23-3 G
R157 @ 0_0402_5% HDMI@ S

3
L8 HDMI@ +3VS 25 OE# 2 @ 1 0318 add HDMI_SCLK R304 2 HDMI@ 1 2.2K_0402_5%
OE*

1
1 2 R199 10K_0402_5% 1
1 2 C361 HDMI_SDATA R305 2 HDMI@ 1 2.2K_0402_5%
2
VCC3V HDMI_SCLK R133 HDMI@
11 28
VCC3V SCL_SINK 100K_0402_5% 0.1U_0402_16V4Z
4 3 15
4 3 VCC3V HDMI_SDATA HDMI@ 2 PVT 03/01 add
21 29

2
OCE2012120YZF VCC3V SDA_SINK
26
VGA_DVI_TXC+ HDMI_R_CK+ VCC3V
1 2 33
R173 @ 0_0402_5% VCC3V HDMI_HPD
40 30
VCC3V HPD_SINK
46
VCC3V DDC_EN R374 2 HDMI@ 1 4.7K_0402_5%
32 +3VS
VGA_DVI_TXD0+ HDMI_R_D0+ DDC_EN
1 2
R175 @ 0_0402_5%
C C
L9 HDMI@ +3VS R375 1 @ 2 0_0402_5% 3 34 R360 2 @ 1 0_0402_5% HDMI@ F2
R196 @ 0_0402_5% FUNCTION1 FUNCTION3 R371 @ 0_0402_5%
4 3 1 2 4 35 2 1 +3VS +5VS 2 1+HDMI_5V_OUT_F 2 1 +HDMI_5V_OUT
4 3 R367 @ 0_0402_5% FUCNTION2 FUNCTION4 R373
1 2 1 HDMI@ 2 0_0402_5% D53 1.1A_6V_MINISMDC110F-2 1
R154 1 HDMI@ 2 0_0402_5% R370 1 @ 2 0_0402_5% PMEG2010AEH_SOD123 HDMI@ C259
1 2 2 R161 1 6 HDMI@
1 2 HDMI@ 3.3K_0402_1% ANALOG1(REXT) 0.1U_0402_16V4Z
OCE2012120YZF PCH_HDMI_HPD 2
31 PCH_HDMI_HPD 7
VGA_DVI_TXD0- HDMI_R_D0- HPD_SOURCE
1 2
R180 @ 0_0402_5% UMA_HDMI_DATA 8
31 UMA_HDMI_DATA SDA_SOURCE
UMA_HDMI_CLK 9
31 UMA_HDMI_CLK SCL_SOURCE
VGA_DVI_TXD1- 1 2 HDMI_R_D1-
R182 @ 0_0402_5% R692 1 @ 2 0_0402_5% 10
L10 HDMI@ ANALOG2
1 2 JHDMI
1 2 VGA_DVI_TXC+ HDMI_TXC+ C430 HDMI@ 1
13 48 2 0.1U_0402_16V7K UMA_HDMI_TXC+ 31
HDMI_HPD 19
VGA_DVI_TXC- OUT_D4+ IN_D4+ HDMI_TXC- C374 HDMI@ 1 HP_DET
14 47 2 0.1U_0402_16V7K UMA_HDMI_TXC- 31 +HDMI_5V_OUT 18
OUT_D4- IN_D4- +5V
4 3 17
4 3 VGA_DVI_TXD2+ HDMI_TX2+ C456 HDMI@ 1 DDC/CEC_GND
16 45 2 0.1U_0402_16V7K UMA_HDMI_TX2+ 31
HDMI_SDATA 16
OCE2012120YZF VGA_DVI_TXD2- OUT_D3+ IN_D3+ HDMI_TX2- C432 HDMI@ 1 SDA
17 44 2 0.1U_0402_16V7K UMA_HDMI_TX2- 31
HDMI_SCLK 15
VGA_DVI_TXD1+ HDMI_R_D1+ OUT_D3- IN_D3- SCL
1 2 14
R183 @ 0_0402_5% VGA_DVI_TXD1+ HDMI_TX1+ C372 HDMI@ 1 Reserved
19 42 2 0.1U_0402_16V7K UMA_HDMI_TX1+ 31 13
VGA_DVI_TXD1- OUT_D2+ IN_D2+ HDMI_TX1- C434 HDMI@ 1 CEC
20 41 2 0.1U_0402_16V7K UMA_HDMI_TX1- 31
HDMI_R_CK- 12 20
OUT_D2- IN_D2- CK- GND
11 21
VGA_DVI_TXD2+ HDMI_R_D2+ VGA_DVI_TXD0+ HDMI_TX0+ C455 HDMI@ 1 CK_shield GND
1 2 22 39 2 0.1U_0402_16V7K UMA_HDMI_TX0+ 31
HDMI_R_CK+ 10 22
R187 @ 0_0402_5% VGA_DVI_TXD0- OUT_D1+ IN_D1+ HDMI_TX0- C373 HDMI@ 1 CK+ GND
23 38 2 0.1U_0402_16V7K UMA_HDMI_TX0- 31
HDMI_R_D0- 9 23
L11 HDMI@ OUT_D1- IN_D1- D0- GND
8
HDMI_R_D0+ D0_shield
4 3 7
4 3 R307 2.2K_0402_5% HDMI_R_D1- D0+
6
HDMI_TXC+ D1-
1 2 1 5
GND @ HDMI_R_D1+ D1_shield
1 2 5 4
1 2 GND HDMI_R_D2- D1+
12 3
OCE2012120YZF GND HDMI_TXC- D2-
B 18 2 HDMI@ 1 2 B
VGA_DVI_TXD2- HDMI_R_D2- GND HDMI_R_D2+ D2_shield
1 2 24 1
R188 @ 0_0402_5% GND R308 2.2K_0402_5% D2+
27 49
GND THERMAL_PAD SUYIN_100042MR019S153ZL_19P
31
GND CONN@
36
GND 0318 add for hdmi clk noise
37
GND
43
GND

ASM1442 QFN_48P_7X7 HDMI@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI Conn./CEC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Wednesday, April 14, 2010 Sheet 27 of 57
5 4 3 2 1
 5 4 3 2 1

C287
4.7P_0402_50V8J
JCMOS 2 1
+RTCVCC 1 2PCH_RTCRST# 1 2
R282 20K_0402_1% @ Y3

10M_0402_5%
1
1 2 3 NC OSC 4

R283
C288 1U_0402_6.3V4Z
2 NC OSC 1 U11A
J2
1 2PCH_SRTCRST# 1 2 32.768KHZ_12.5PF_Q13MC14610002

2
R284 20K_0402_1% @ PCH_RTCX1 B13 D33 LPC_AD0
RTCX1 FWH0 / LAD0 LPC_AD0 38,39,43
1 2 2 1 PCH_RTCX2 D13 B33 LPC_AD1
RTCX2 FWH1 / LAD1 LPC_AD1 38,39,43
C289 1U_0402_6.3V4Z C290 4.7P_0402_50V8J C32 LPC_AD2
FWH2 / LAD2 LPC_AD2 38,39,43
D A32 LPC_AD3 D
FWH3 / LAD3 LPC_AD3 38,39,43
PCH_RTCRST# C14 RTCRST# LPC_FRAME#
FWH4 / LFRAME# C34 LPC_FRAME# 38,39,43
+RTCVCC PCH_SRTCRST# D17 SRTCRST#
A34

RTC

LPC
SM_INTRUDER# LDRQ0#
Integrated SUS 1.05V VRM Enable 1
R285
2
1M_0402_5%
A16 INTRUDER# LDRQ1# / GPIO23 F34

High - Enable Internal VRs 1 2 PCH_INTVRMEN A14 AB9 SERIRQ

INTVRMEN SERIRQ SERIRQ 38,43
PCH_INTVRMEN (must be always pulled high) R275 330K_0402_5%
1 2 +3VS
R286 10K_0402_5%
AZ_BITCLK A30 HDA_BCLK
SATA0RXN AK7
AZ_SYNC
HDA_SYNC D29 HDA_SYNC SATA0RXP AK6
AK11
PCH_SPKR SATA0TXN
This signal has a weak internal pull down. 31,42 PCH_SPKR P1 SPKR SATA0TXP AK9
H=>On Die PLL is supplied by 1.5V
AZ_RST#
*L=>On Die PLL is supplied by 1.8V C30 HDA_RST#
SATA1RXN AH6 SATA_PRX_C_DTX_N1
SATA_PRX_C_DTX_N1 37
AH5 SATA_PRX_C_DTX_P1
SATA1RXP SATA_PRX_C_DTX_P1 37
AZ_SDIN0_HD SATA_PTX_DRX_N1
HDA_SDO 42 AZ_SDIN0_HD G30 HDA_SDIN0 SATA1TXN AH9
AH8 SATA_PTX_DRX_P1
SATA_PTX_DRX_N1 37
SATA1TXP SATA_PTX_DRX_P1 37
This signal has a weak internal pull down. PAD T62 AZ_SDIN1_MD F30 HDA_SDIN1
This signal can't PU +3VS SATA2RXN AF11
E32 AF9

IHDA
HDA_SDIN2 SATA2RXP
SATA2TXN AF7
F32 HDA_SDIN3 SATA2TXP AF6

1
Flash Descriptor Security Overide
SATA3RXN AH3
C
Low = Enabled R125 AZ_SDOUT B29 AH1 C
100K_0402_5% HDA_SDO SATA3RXP
HDA_DOCK_EN# High = Disabled * SATA3TXN AF3
AF1
2 IAMT_EN# SATA3TXP
H32

SATA
Q42 HDA_DOCK_EN# / GPIO33 SATA_PRX_C_DTX_N4
D SATA4RXN AD9 SATA_PRX_C_DTX_N4 37
1
2N7002_SOT23-3 @ R118 1K_0402_5% J30 AD8 SATA_PRX_C_DTX_P4
HDA_DOCK_RST# / GPIO13 SATA4RXP SATA_PRX_C_DTX_P4 37
2 1 2 AD6 SATA_PTX_DRX_N4
43 IAMT_EN SATA4TXN SATA_PTX_DRX_N4 37
G AD5 SATA_PTX_DRX_P4
SATA4TXP SATA_PTX_DRX_P4 37
2

S
3

R126 PCH_JTAG_TCK M3 AD3

100K_0402_5% JTAG_TCK SATA5RXN
SATA5RXP AD1
42 AZ_BITCLK_HD R288 1 2 33_0402_5% AZ_BITCLK PCH_JTAG_TMS K3 AB3
JTAG_TMS SATA5TXN
AB1
1

PCH_JTAG_TDI SATA5TXP
K1 JTAG_TDI
42 AZ_SYNC_HD R290 1 2 33_0402_5% AZ_SYNC

JTAG
PCH_JTAG_TDO J2 AF16
JTAG_TDO SATAICOMPO

42 AZ_RST_HD# R292 1 2 33_0402_5% AZ_RST# PCH_JTAG_RST# J4 AF15 SATAICOMP 1 2

TRST# SATAICOMPI +VTT
R295 37.4_0402_1%

R294 1 2 33_0402_5% AZ_SDOUT +3VS

42 AZ_SDOUT_HD
PCH_SPI_CLK BA2 SPI_CLK SATA_LED# R301 2 1 10K_0402_5%
PCH_SPI_CS0# AV3 SPI_CS0#
AY3 T3 SATA_LED# VGA_PWROK R306 1 2 10K_0402_5%
+3VS SPI_CS1# SATALED# SATA_LED# 38

2 @ 1PCH_SPI_MOSI AY1 Y9 PROJECT_ID0

B SPI_MOSI SATA0GP / GPIO21 PROJECT_ID0 33 B
R273 1K_0402_5%

SPI
PCH_SPI_MISO AV1 V1 VGA_PWROK
SPI_MISO SATA1GP / GPIO19 VGA_PWROK 32,46,56

IBEXPEAK-M QV20 A0_FCBGA1071

+3VALW +3VALW +3VALW +3VALW

1

@ @ @
R386 R363 @ R643
200_0402_5% 200_0402_5% R536 20K_0402_5% +3VS
200_0402_5% +RTCBATT
2

1
PCH_JTAG_TMS PCH_JTAG_TDO PCH_JTAG_TDI PCH_JTAG_RST#
1
1

@ @ @ U13 D13
R355 R535 @ R364 C293 8 4 PCH_SPI_CLK BAS40-04_SOT23-3
R537 10K_0402_5% VCC VSS +RTCVCC
100_0402_5% 100_0402_5% 0.1U_0402_16V4Z

1
100_0402_5% 2
3

2
W R385
+CHGRTC
2

7 HOLD 10_0402_5% 1
@
PCH_SPI_CS0# 1 C291

2
S 0.1U_0402_16V4Z
1 2
PCH_SPI_CLK 6 C86
C 10P_0402_50V8J
1 2 PCH_JTAG_TCK PCH_SPI_MOSI 5 2 PCH_SPI_MISO @
R156 51_0402_5% D Q 2
A A
MX25L3205DM2I-12G SO8

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH_SPI/SATA/LPC/RTC/HDA
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Wednesday, April 14, 2010 Sheet 28 of 57
5 4 3 2 1
 5 4 3 2 1

+3VALW 2 R229 1 2.2K_0402_5% +3VS

2 R230 1 2.2K_0402_5% R231 4.7K_0402_5%

5
Q3B R232 4.7K_0402_5%

PCH_SMBDATA 3 4 PM_SMBDATA 11,12,25,39

2
Q3A 2N7002DW-T/R7_SOT363-6

PCH_SMBCLK 6 1 PM_SMBCLK 11,12,25,39

2N7002DW-T/R7_SOT363-6
D D
U11B

PCIE_PRX_C_LANTX_N1 BG30 B9 EC_LID_OUT# EC_LID_OUT# 43 +3VALW 2 R233 1 2.2K_0402_5% +3VS

40 PCIE_PRX_C_LANTX_N1 PERN1 SMBALERT# / GPIO11
For LAN PCIE_PRX_C_LANTX_P1 BJ30
40 PCIE_PRX_C_LANTX_P1 PERP1
40 PCIE_PTX_C_LANRX_N1 C276 2 1 0.1U_0402_16V7K PCIE_PTX_LANRX_N1 BF29 H14 PCH_SMBCLK 2 R234 1 2.2K_0402_5%
PETN1 SMBCLK

5
40 PCIE_PTX_C_LANRX_P1 C273 2 1 0.1U_0402_16V7K PCIE_PTX_LANRX_P1 BH29 Q4B
PETP1 PCH_SMBDATA
C8
PCIE_PRX_WLANTX_N2 SMBDATA PCH_SMLDATA1
39 PCIE_PRX_WLANTX_N2 AW30 3 4 EC_SMB_DA2 14,43
PCIE_PRX_WLANTX_P2 PERN2
For WLAN 39 PCIE_PRX_WLANTX_P2 BA30
PERP2

2
39 PCIE_PTX_C_WLANRX_N2 C274 2 1 0.1U_0402_16V7K PCIE_PTX_WLANRX_N2 BC30 J14 PCH_GPIO60 Q4A 2N7002DW-T/R7_SOT363-6
C275 2 PCIE_PTX_WLANRX_P2 PETN2 SML0ALERT# / GPIO60
39 PCIE_PTX_C_WLANRX_P2 1 0.1U_0402_16V7K BD30
PETP2 PCH_SMLCLK0 PCH_SMLCLK1
SML0CLK C6 6 1 EC_SMB_CK2 14,43
AU30

SMBus
PERN3 PCH_SMLDATA0 2N7002DW-T/R7_SOT363-6
AT30 G8
PERP3 SML0DATA
AU32
PETN3
AV32
PETP3 PCH_GPIO74
M14
SML1ALERT# / GPIO74
BA32
PERN4 PCH_SMLCLK1
BB32 PERP4 SML1CLK / GPIO58 E10
BD32
PETN4 PCH_SMLDATA1
BE32 G12
PETP4 SML1DATA / GPIO75

PCI-E*
BF33
PERN5
BH33 T13
PERP5 CL_CLK1

Controller
BG32
PETN5
BJ32 PETP5 CL_DATA1 T11
+3VALW

Link
BA34 T9
PERN6 CL_RST1#
C AW34 PERP6 1 R263 2 10K_0402_5% C
BC34
PETN6
BD34
PETP6 CLK_REQ_VGA#
H1 CLK_REQ_VGA# 13
PEG_A_CLKRQ# / GPIO47
AT34
PERN7
AU34 PERP7

2
AU36 AD43 CLK_PCIE_VGA# @
PETN7 CLKOUT_PEG_A_N CLK_PCIE_VGA# 13
CLK_PCIE_VGA R243
AV36
PETP7 CLKOUT_PEG_A_P
AD45 CLK_PCIE_VGA 13 VGA
100K_0402_5%
NC BG34 AN4 CLK_PEG# +3VALW
PERN8 CLKOUT_DMI_N CLK_PEG# 5

PEG
BJ34 AN2 CLK_PEG
CLK_PEG 5

1
PERP8 CLKOUT_DMI_P
BG36
PETN8 PCH_SMLCLK0 2.2K_0402_5% R237
BJ36 PETP8 2 1
AT1 PCH_SMLDATA0 2.2K_0402_5% 2 1 R238
CLKOUT_DP_N / CLKOUT_BCLK1_N PCH_GPIO60 10K_0402_5% R239
AT3 2 1
CLK_LAN# CLKOUT_DP_P / CLKOUT_BCLK1_P PCH_GPIO74 10K_0402_5% R240
40 CLK_LAN# AK48 2 1
CLK_LAN CLKOUT_PCIE0N EC_LID_OUT# 10K_0402_5% R241
LAN 40 CLK_LAN AK47
CLKOUT_PCIE0P
2 1

From CLK BUFFER

AW24 PCH_CLK_DMI# PCH_CLK_DMI# 25
CLKREQ_LAN# CLKIN_DMI_N PCH_CLK_DMI
40 CLKREQ_LAN# P9 BA24 PCH_CLK_DMI 25
PCIECLKRQ0# / GPIO73 CLKIN_DMI_P

+3VS CLK_WLAN# AM43 AP3 CLK_BCLK#

39 CLK_WLAN# CLKOUT_PCIE1N CLKIN_BCLK_N CLK_BCLK# 25
WLAN CLK_WLAN AM45 AP1 CLK_BCLK CLK_BCLK 25
39 CLK_WLAN CLKOUT_PCIE1P CLKIN_BCLK_P
1 2 PCH_GPIO20
10K_0402_5% R246 CLKREQ_WLAN# U4
39 CLKREQ_WLAN# PCIECLKRQ1# / GPIO18
F18 CLK_DOT# CLK_DOT# 25
CLKIN_DOT_96N
1 2 CLKREQ_WLAN# E18 CLK_DOT CLK_DOT 25
10K_0402_5% R248 CLKIN_DOT_96P
AM47
CLKOUT_PCIE2N
AM48
B CLKOUT_PCIE2P CLK_SATA# B
AH13 CLK_SATA# 25
PCH_GPIO20 CLKIN_SATA_N / CKSSCD_N CLK_SATA
N4 AH12
+3VALW PCIECLKRQ2# / GPIO20 CLKIN_SATA_P / CKSSCD_P CLK_SATA 25 From CLK GEN For: 133/100/96/14.318 MHZ
R247 2 1 1M_0402_5%
1 2 CLKREQ_LAN# AH42 P41 CLK_14M_PCH CLK_14M_PCH 25
10K_0402_5% R244 CLKOUT_PCIE3N REFCLK14IN Y2
AH41 CLKOUT_PCIE3P PCH_X1 1 2 PCH_X2
1 2 PCH_GPIO25 PCH_GPIO25 A8 J42 CLK_PCILOOP
CLK_PCILOOP 32
10K_0402_5% R245 PCIECLKRQ3# / GPIO25 CLKIN_PCILOOPBACK 25MHZ_20PF_7A25000012 1
1
C277 C278
1 2 PCH_GPIO26 AM51 AH51 PCH_X1 27P_0402_50V8J 27P_0402_50V8J
10K_0402_5% R249 CLKOUT_PCIE4N XTAL25_IN PCH_X2
AM53 CLKOUT_PCIE4P XTAL25_OUT AH53
2 2
1 2 PCH_GPIO44 PCH_GPIO26 M9 AF38 XCLK_RCOMP 1 2 +VTT
10K_0402_5% R250 PCIECLKRQ4# / GPIO26 XCLK_RCOMP R252 90.9_0402_1%

1 2 PCH_GPIO56 AJ50 T45 CLK_48M_PCH 41

10K_0402_5% R251 CLKOUT_PCIE5N CLKOUTFLEX0 / GPIO64
AJ52
CLKOUT_PCIE5P
PCH_GPIO44 H6 P43
Clock Flex

PCIECLKRQ5# / GPIO44 CLKOUTFLEX1 / GPIO65

AK53
AK51
CLKOUT_PEG_B_N CLKOUTFLEX2 / GPIO66
T42 For EMI
CLKOUT_PEG_B_P
PCH_GPIO56 P13 N50 @
PEG_B_CLKRQ# / GPIO56 CLKOUTFLEX3 / GPIO67 CLK_PCILOOP @
2 1 2 1
R400 10_0402_5% C474 22P_0402_50V8J
A
IBEXPEAK-M QV20 A0_FCBGA1071 @ A
CLK_14M_PCH 1 @ 2 2 1
R70 100_0402_5%
C206 100P_0402_50V8J

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH_CLK/PCIE/SMBUS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Wednesday, April 14, 2010 Sheet 29 of 57
5 4 3 2 1
 5 4 3 2 1

D D

U11C
BA18 FDI_CTX_PRX_N0
FDI_RXN0 FDI_CTX_PRX_N0 6
DMI_CTX_PRX_N0 BC24 BH17 FDI_CTX_PRX_N1
6 DMI_CTX_PRX_N0 DMI0RXN FDI_RXN1 FDI_CTX_PRX_N1 6
DMI_CTX_PRX_N1 BJ22 BD16 FDI_CTX_PRX_N2
6 DMI_CTX_PRX_N1 DMI1RXN FDI_RXN2 FDI_CTX_PRX_N2 6
DMI_CTX_PRX_N2 AW20 BJ16 FDI_CTX_PRX_N3
6 DMI_CTX_PRX_N2 DMI2RXN FDI_RXN3 FDI_CTX_PRX_N3 6
DMI_CTX_PRX_N3 BJ20 BA16 FDI_CTX_PRX_N4
6 DMI_CTX_PRX_N3 DMI3RXN FDI_RXN4 FDI_CTX_PRX_N4 6
BE14 FDI_CTX_PRX_N5
FDI_RXN5 FDI_CTX_PRX_N5 6
DMI_CTX_PRX_P0 BD24 BA14 FDI_CTX_PRX_N6
6 DMI_CTX_PRX_P0 DMI0RXP FDI_RXN6 FDI_CTX_PRX_N6 6
DMI_CTX_PRX_P1 BG22 BC12 FDI_CTX_PRX_N7
6 DMI_CTX_PRX_P1 DMI1RXP FDI_RXN7 FDI_CTX_PRX_N7 6
DMI_CTX_PRX_P2 BA20
6 DMI_CTX_PRX_P2 DMI2RXP
DMI_CTX_PRX_P3 BG20 BB18 FDI_CTX_PRX_P0
6 DMI_CTX_PRX_P3 DMI3RXP FDI_RXP0 FDI_CTX_PRX_P0 6
BF17 FDI_CTX_PRX_P1
FDI_RXP1 FDI_CTX_PRX_P1 6
DMI_PTX_CRX_N0 BE22 BC16 FDI_CTX_PRX_P2
6 DMI_PTX_CRX_N0 DMI0TXN FDI_RXP2 FDI_CTX_PRX_P2 6
DMI_PTX_CRX_N1 BF21 BG16 FDI_CTX_PRX_P3
+3VALW 6 DMI_PTX_CRX_N1 DMI1TXN FDI_RXP3 FDI_CTX_PRX_P3 6
DMI_PTX_CRX_N2 BD20 AW16 FDI_CTX_PRX_P4
6 DMI_PTX_CRX_N2 DMI2TXN FDI_RXP4 FDI_CTX_PRX_P4 6
DMI_PTX_CRX_N3 BE18 BD14 FDI_CTX_PRX_P5
6 DMI_PTX_CRX_N3 DMI3TXN FDI_RXP5 FDI_CTX_PRX_P5 6
BB14 FDI_CTX_PRX_P6
FDI_RXP6 FDI_CTX_PRX_P6 6
1 2 SUS_PWR_ACK DMI_PTX_CRX_P0 BD22 BD12 FDI_CTX_PRX_P7
6 DMI_PTX_CRX_P0 DMI0TXP FDI_RXP7 FDI_CTX_PRX_P7 6
R316 10K_0402_5% DMI_PTX_CRX_P1 BH21
6 DMI_PTX_CRX_P1 DMI1TXP
1 2 GPIO72 DMI_PTX_CRX_P2 BC20
6 DMI_PTX_CRX_P2 DMI2TXP
R318 10K_0402_5% DMI_PTX_CRX_P3 BD18 BJ14 FDI_INT
6 DMI_PTX_CRX_P3 DMI3TXP FDI_INT FDI_INT 6
1 2 IBEX_RI#

DMI
FDI
R320 10K_0402_5% BF13 FDI_FSYNC0
FDI_FSYNC0 FDI_FSYNC0 6
+VTT 1 2 DMI_COMP BH25
R311 49.9_0402_1% DMI_ZCOMP FDI_FSYNC1
FDI_FSYNC1 BH13 FDI_FSYNC1 6
2 1 PM_PWROK BF25
R329 10K_0402_5% DMI_IRCOMP FDI_LSYNC0
C 2 1 PWROK Close to PCH FDI_LSYNC0 BJ12 FDI_LSYNC0 6 C
R322 10K_0402_5% BG14 FDI_LSYNC1
FDI_LSYNC1 FDI_LSYNC1 6
2 1 LAN_RST#
R323 10K_0402_5%
+3VALW

2 @ 1
0_0402_5% R256
EC_SWI# 1 2
+3VS XDP_DBRESET# T6 J12 EC_SWI# R313 10K_0402_5%
5 XDP_DBRESET# SYS_RESET# WAKE# EC_SWI# 39,40
0.1U_0402_16V4Z
1 2
C230 VGATE M6 Y1 PM_CLKRUN# 2 1 +3VS
54 VGATE SYS_PWROK CLKRUN# / GPIO32
5

U12 R319 8.2K_0402_5%

1
P

43 PM_PWROK IN1

System Power Management

4 PWROK B17
O PWROK PM_CLKRUN# 38,43
VGATE 2 IN2
G

SN74AHC1G08DCKR_SC70-5 1 2 K5 P8 SUS_STAT#
SUS_STAT# 38
3

R321 0_0402_5% MEPWROK SUS_STAT# / GPIO61

LAN_RST# A10 F3 SUS_CLK_R 1 2

LAN_RST# SUSCLK / GPIO62 SUS_CLK 43
R334 0_0402_5% @

DRAMPWROK D9 E4 PM_SLP_S5#
5 DRAMPWROK DRAMPWROK SLP_S5# / GPIO63 PM_SLP_S5# 43

PCH_RSMRST# C16 H7 PM_SLP_S4#

RSMRST# SLP_S4# PM_SLP_S4# 43
B B
SUS_PWR_ACK M1 P12 PM_SLP_S3#
43 SUS_PWR_ACK SUS_PWR_DN_ACK / GPIO30 SLP_S3# PM_SLP_S3# 43

PBTN_OUT# P5 K8
43 PBTN_OUT# PWRBTN# SLP_M#

+3VALW 1 2 PCH_ACIN P7 N2
R324 330K_0402_5% ACPRESENT / GPIO31 TP23

D26 GPIO72 A6 BJ10 PMSYNCH

BATLOW# / GPIO72 PMSYNCH PMSYNCH 5
43,49 ACIN 1 2

CH751H-40PT_SOD323-2 IBEX_RI# F14 F6

RI# SLP_LAN# / GPIO29

IBEXPEAK-M QV20 A0_FCBGA1071

+3VALW

1 2
R691 1K_0402_5% 0_0402_5% 1 @ 2 R325

Q26 1 PCH_RSMRST#
C

43 EC_RSMRST# 3
E

2 1
MMBT3906_SOT23-3 R326
10K_0402_5%
B
2

+3VALW 2 1
A
R327 A
1

4.7K_0402_5%
D15A D15B
BAV99DW-7_SOT363 BAV99DW-7_SOT363

Security Classification Compal Secret Data Compal Electronics, Inc.

6

RSMRST# circuit 1
R328
2.2K_0402_5%
2
Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH_DMI/FDI/PWM
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Wednesday, April 14, 2010 Sheet 30 of 57
5 4 3 2 1
 5 4 3 2 1

U11D
UMA_ENBKL T48 BJ46
25 UMA_ENBKL L_BKLTEN SDVO_TVCLKINN
UMA_ENVDD T47 BG46
25 UMA_ENVDD L_VDD_EN SDVO_TVCLKINP
PCH_PWM Y48 BJ48
25 PCH_PWM L_BKLTCTL SDVO_STALLN
SDVO_STALLP BG48
LCD_CLK AB48
25 LCD_CLK L_DDC_CLK
LCD_DATA Y45 BF45
25 LCD_DATA L_DDC_DATA SDVO_INTN
SDVO_INTP BH45
1 2 LCTL_CLK AB46
R55 L_CTRL_CLK
+3VS 1 2 10K_0402_5% LCTL_DATA V48 L_CTRL_DATA
R54 10K_0402_5%
1 2 LVDS_IBG AP39 T51
R68 2.37K_0402_1% LVD_IBG SDVO_CTRLCLK
D AP41 LVD_VBG SDVO_CTRLDATA T53 D
T40 PAD
1 2 UMA_ENBKL AT43
R127 100K_0402_5% LVD_VREFH
AT42 LVD_VREFL DDPB_AUXN BG44
DDPB_AUXP BJ44
AU38 R83 2 @ 1 10K_0402_5%
DDPB_HPD

LVDS
LCD_TXCLK- AV53
25 LCD_TXCLK- LVDSA_CLK# +3VS
LCD_TXCLK+ AV51 BD42
25 LCD_TXCLK+ LVDSA_CLK DDPB_0N
DDPB_0P BC42
LCD_TXOUT0- BB47 BJ42
25 LCD_TXOUT0- LVDSA_DATA#0 DDPB_1N
LCD_TXOUT1- BA52 BG42

Digital Display Interface

25 LCD_TXOUT1- LVDSA_DATA#1 DDPB_1P

1
+3VS LCD_TXOUT2- AY48 BB40
25 LCD_TXOUT2- LVDSA_DATA#2 DDPB_2N
AV47 BA40 R128 R130
LVDSA_DATA#3 DDPB_2P 2.2K_0402_5% 2.2K_0402_5%
DDPB_3N AW38
2 1 LCD_CLK LCD_TXOUT0+ BB48 BA38 HDMI@ HDMI@
25 LCD_TXOUT0+ LVDSA_DATA0 DDPB_3P
R82 2.2K_0402_5% LCD_TXOUT1+ BA50
25 LCD_TXOUT1+

2
LCD_TXOUT2+ LVDSA_DATA1
25 LCD_TXOUT2+ AY49 LVDSA_DATA2
2 1 LCD_DATA AV48 Y49
LVDSA_DATA3 DDPC_CTRLCLK UMA_HDMI_CLK 27
R60 2.2K_0402_5% AB49
DDPC_CTRLDATA UMA_HDMI_DATA 27
AP48 LVDSB_CLK#
AP47 LVDSB_CLK DDPC_AUXN BE44 1 R132 2 100K_0402_5%
DDPC_AUXP BD44
AY53 AV40 PCH_HDMI_HPD
LVDSB_DATA#0 DDPC_HPD PCH_HDMI_HPD 27
AT49 LVDSB_DATA#1
AU52 BE40 UMA_HDMI_TX2-
+3VS LVDSB_DATA#2 DDPC_0N UMA_HDMI_TX2- 27
AT53 BD40 UMA_HDMI_TX2+
LVDSB_DATA#3 DDPC_0P UMA_HDMI_TX2+ 27
BF41 UMA_HDMI_TX1-
DDPC_1N UMA_HDMI_TX1- 27
UMA_HDMI_TX1+
C 2 1 UMA_CRT_CLK
AY51
AT48
LVDSB_DATA0
LVDSB_DATA1
DDPC_1P
DDPC_2N
BH41
BD38 UMA_HDMI_TX0-
UMA_HDMI_TX1+
UMA_HDMI_TX0-
27
27
HDMI C
R63 2.2K_0402_5% AU50 BC38 UMA_HDMI_TX0+
LVDSB_DATA2 DDPC_2P UMA_HDMI_TX0+ 27
AT51 BB36 UMA_HDMI_TXC-
LVDSB_DATA3 DDPC_3N UMA_HDMI_TXC- 27
2 1 UMA_CRT_DATA BA36 UMA_HDMI_TXC+
DDPC_3P UMA_HDMI_TXC+ 27
R61 2.2K_0402_5%

UMA_CRT_B AA52 U50

26 UMA_CRT_B CRT_BLUE DDPD_CTRLCLK
UMA_CRT_G AB53 U52
26 UMA_CRT_G CRT_GREEN DDPD_CTRLDATA
1 2 UMA_CRT_B UMA_CRT_R AD53
26 UMA_CRT_R CRT_RED
R56 150_0402_1%
DDPD_AUXN BC46
1 2 UMA_CRT_G 26 UMA_CRT_CLK UMA_CRT_CLK V51 BD46
R57 150_0402_1% UMA_CRT_DATA CRT_DDC_CLK DDPD_AUXP R86 @
26 UMA_CRT_DATA V53 CRT_DDC_DATA DDPD_HPD AT38 2 1 10K_0402_5%

1 2 UMA_CRT_R BJ40
R58 150_0402_1% UMA_CRT_HSYNC Y53 DDPD_0N
26 UMA_CRT_HSYNC CRT_HSYNC DDPD_0P BG40
UMA_CRT_VSYNC Y51 BJ38
26 UMA_CRT_VSYNC CRT_VSYNC DDPD_1N
DDPD_1P BG38

CRT
R266 BF37
CRT_IREF DDPD_2N
2 1 AD48 DAC_IREF DDPD_2P BH37
AB51 CRT_IRTN DDPD_3N BE36
1K_0402_1% BD36
DDPD_3P
IBEXPEAK-M QV20 A0_FCBGA1071

Internal: Pull down 20k

B
PCH Strap Pin +1.8VS_PCH_NAND During Reset: Low
Initial: Low
Danbury Technology Enabled
B
High = Enabled
+3VS
NV_ALE Low = Disabled (Default)
2 @ 1 NV_ALE NV_ALE 32
Internal: Pull down 20k NO REBOOT Strap R267 1K_0402_5%
During Reset: HZ @ NV_CLE
PCH_SPKR Low= Disable 2 1 NV_CLE 32
Initial: Low R268 1K_0402_5% DMI Termination Voltage
@ PCH_SPKR
High= Enable
1 2 PCH_SPKR 28,42
R269 1K_0402_5% Internal: Pull down 20k Low= Set to Vss (Default)
Internal: Pull up 20k During Reset: Low NV_CLE High= Set to Vcc
During Reset: High Boot BIOS Strap
Initial: Low
Initial: High PCI_GNT#1 PCI_GNT#0 Boot BIOS Loaction
1K_0402_5% @ 1 R270 PCI_GNT#0
2 PCI_GNT#0 32 0 0 LPC (Default)
1K_0402_5% @ 1 R271 PCI_GNT#1
2 PCI_GNT#1 32 0 1 Reserved (NAND)
Internal: Pull up 20k 1 0 PCI
During Reset: High
Initial: High 1 1 SPI
2 @ 1 PCI_GNT#3
PCI_GNT#3 32
R272 1K_0402_5% A16 Swap Override Strap
Internal: Pull up 20k
During Reset: High Low= A16 swap override Enable
Initial: High
PCI_GNT#3 High= A16 swap override Disable
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH_CRT/LVDS/HDMI/STRAP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Wednesday, April 14, 2010 Sheet 31 of 57
5 4 3 2 1
 5 4 3 2 1

@
2 1
R253 0_0402_5%

+3VS

U11E
H40 AD0 NV_CE#0 AY9

5
N34 BD1 U8
AD1 NV_CE#1 PLT_RST#
D C44 AP15 1 D

P
AD2 NV_CE#2 IN1
A38 AD3 NV_CE#3 BD8 O 4 BUF_PLT_RST# 5,38
C36 AD4 2 IN2

G
2

1
J34 AD5 NV_DQS0 AV9
A40 BG8 R84 SN74AHC1G08DCKR_SC70-5 R129

3
AD6 NV_DQS1

1
D45 100K_0402_5% 100K_0402_5%
AD7 R403 @
E36 AD8 NV_DQ0 / NV_IO0 AP7
H48 AP6 0_0402_5%

2
AD9 NV_DQ1 / NV_IO1 @
E40 AD10 NV_DQ2 / NV_IO2 AT6
C40 AT9

2
AD11 NV_DQ3 / NV_IO3
M48 AD12 NV_DQ4 / NV_IO4 BB1
M45 AV6 +3VS
AD13 NV_DQ5 / NV_IO5
F53 AD14 NV_DQ6 / NV_IO6 BB3
M40 AD15 NV_DQ7 / NV_IO7 BA4 1 2
C477 0.1U_0402_16V4Z

NVRAM
M43 AD16 NV_DQ8 / NV_IO8 BE4

5
J36 BB6 @ 0_0402_5% U20
AD17 NV_DQ9 / NV_IO9 OPT@
K48 BD6 2 1 1

P
AD18 NV_DQ10 / NV_IO10 28,46,56 VGA_PWROK IN1
F40 BB7 R404 4 2 1
+3VS AD19 NV_DQ11 / NV_IO11 O PLTRST_VGA# 13
C42 BC8 DGPU_RST# 2 R399 0_0402_5%
AD20 NV_DQ12 / NV_IO12 IN2

G
RP1 K46 BJ8
AD21 NV_DQ13 / NV_IO13

1
1 8 PCI_REQ#1 M51 BJ6 SN74AHC1G08DCKR_SC70-5

3
AD22 NV_DQ14 / NV_IO14

2
2 7 J52 BG6 OPT@
PCI_PIRQD# AD23 NV_DQ15 / NV_IO15 R390 R405
3 6 K51 AD24
4 5 PCI_IRDY# L34 BD3 NV_ALE NV_ALE 31 100K_0402_5%
AD25 NV_ALE NV_CLE OPT@
F42 AY6 NV_CLE 31

2
8.2K_0804_8P4R_5% AD26 NV_CLE 1K_0402_5%
J40

1
AD27
G46 AD28
RP2 F44 AU2 NV_RCOMP 1 @ 2
PCI_PIRQH# AD29 NV_RCOMP R276 32.4_0402_1%
1 8 M47 AD30

PCI
C 2 7 PCI_TRDY# H36 AV7 C
PCI_FRAME# AD31 NV_RB# @
3 6
4 5 PCI_PIRQA# J50 AY8 PLT_RST# 2 1 PLTRST_VGA#
C/BE0# NV_WR#0_RE# R402 0_0402_5%
G42 C/BE1# NV_WR#1_RE# AY5
8.2K_0804_8P4R_5% H47 C/BE2#
G34 C/BE3# NV_WE#_CK0 AV11
RP3
1 8 PCI_STOP#
PCI_PIRQE#
PCI_PIRQA#
PCI_PIRQB#
G38 PIRQA#
NV_WE#_CK1 BF5
For Optimus
2 7 H51 PIRQB#
3 6 PCI_PIRQC# PCI_PIRQC# B37 H18 USB20_N0
PIRQC# USBP0N USB20_N0 37
4 5 PCI_PIRQG# PCI_PIRQD# A44 J18 USB20_P0 USB-RIGHT1
PIRQD# USBP0P USB20_P0 37
A18 USB20_N1
USBP1N USB20_N1 37
8.2K_0804_8P4R_5% PCI_REQ#0 F51 C18 USB20_P1 USB-RIGHT2
REQ0# USBP1P USB20_P1 37
PCI_REQ#1 A46 N20 USB20_N2
REQ1# / GPIO50 USBP2N USB20_N2 37
DGPU_SELECT# B45 P20 USB20_P2 USB-Left1
T38 PAD REQ2# / GPIO52 USBP2P USB20_P2 37
PCI_REQ#3 M53 J20
REQ3# / GPIO54 USBP3N
USBP3P L20
PCI_GNT#0 F48 F20
31 PCI_GNT#0 GNT0# USBP4N
PCI_GNT#1 K45 G20
31 PCI_GNT#1 GNT1# / GPIO51 USBP4P
DGPU_RST# F36 A20 USB20_N5
GNT2# / GPIO53 USBP5N USB20_N5 38
PCI_GNT#3 H53 C20 USB20_P5 BT
31 PCI_GNT#3 GNT3# / GPIO55 USBP5P USB20_P5 38
USBP6N M22
+3VS PCI_PIRQE# B41 N22
RP4 PCI_PIRQF# PIRQE# / GPIO2 USBP6P
K53 PIRQF# / GPIO3 USBP7N B21
1 8 PCI_REQ#3 PCI_PIRQG# A36 D21
PCI_PIRQF# PCI_PIRQH# PIRQG# / GPIO4 USBP7P
2 7 A48 PIRQH# / GPIO5 USBP8N H22
3 6 PCI_PIRQB# J22
USBP8P

USB
4 5 PCI_REQ#0 PCI_RST# K6 E22
39 PCI_RST# PCIRST# USBP9N
USBP9P F22
B 8.2K_0804_8P4R_5% PCI_SERR# B
E44 SERR# USBP10N A22
PCI_PERR# E50 C22
PERR# USBP10P USB20_N11
USBP11N G24 USB20_N11 25
H24 USB20_P11 Int. Camera
USBP11P USB20_P11 25
PCI_IRDY# A42 L24 USB20_N12
+3VS IRDY# USBP12N USB20_N12 41
H44 M24 USB20_P12 CardReader
PAR USBP12P USB20_P12 41
RP5 PCI_DEVSEL# F46 A24 USB20_N13 39
PCI_SERR# PCI_FRAME# DEVSEL# USBP13N
1 8 C46 FRAME# USBP13P C24 USB20_P13 39
2 7 PCI_PERR#
3 6 PCI_DEVSEL# PCI_PLOCK# D49
PCI_PLOCK# PLOCK# +3VALW
4 5 USBRBIAS# B25
PCI_STOP# D41 STOP# RP6
8.2K_0804_8P4R_5% PCI_TRDY# C48 D25 USBBIAS 2 1 Within 500 mils
TRDY# USBRBIAS R278 22.6_0402_1% USB_OC#0 4 5
M7 USB_OC#1 3 6
43 EC_PME# PME#
OC0# / GPIO59 N16 USB_OC#0
USB_OC#0 37 (USB-Right) USB_OC#2 2 7
39,40,43 PLT_RST#
PLT_RST# D5 PLTRST# OC1# / GPIO40 J16 USB_OC#1 (USB-Left & eSATA) USB_OC#3 1 8
F16 USB_OC#2 USB_OC#2 37
OC2# / GPIO41 USB_OC#3 10K_0804_8P4R_5%
N52 CLKOUT_PCI0 OC3# / GPIO42 L16
22_0402_5% 2 R287 1 CLK_DEBUG P53 E14 USB_OC#4
39 CLK_PCI_DEBUG 22_0402_5% R280 CLK_TPM CLKOUT_PCI1 OC4# / GPIO43 USB_OC#5
2 1 P46 CLKOUT_PCI2 OC5# / GPIO9 G16 RP8
38 CLK_PCI_TPM 22_0402_5% R281 CLK_EC USB_OC#6
2 1 P51 CLKOUT_PCI3 OC6# / GPIO10 F12
43 CLK_PCI_EC 22_0402_5% R279 CLK_PCH USB_OC#7 USB_OC#4
2 1 P48 CLKOUT_PCI4 OC7# / GPIO14 T15 4 5
29 CLK_PCILOOP USB_OC#5 3 6
USB_OC#6 2 7
IBEXPEAK-M QV20 A0_FCBGA1071 USB_OC#7 1 8

10K_0804_8P4R_5%
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH_USB/PCI/NAND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Wednesday, April 14, 2010 Sheet 32 of 57
5 4 3 2 1
 5 4 3 2 1

GPIO8
Not pull down
Internal: Pull up 20k
U11F
During Reset: High
Initial: High PCH_GPIO0 Y3 AH45
BMBUSY# / GPIO0 CLKOUT_PCIE6N
CLKOUT_PCIE6P AH46
D GPIO15 PCH_GPIO1 C38 D
TACH1 / GPIO1
a Strong pull up may be needed
PCH_GPIO6 D37
for GPIO Functionality TACH2 / GPIO6
CLKOUT_PCIE7N AF48

MISC
Internal: Pull down 20k 43 EC_SCI# EC_SCI# J32 AF47
TACH3 / GPIO7 CLKOUT_PCIE7P
During Reset: Low EC_SMI#
43 EC_SMI# F10 GPIO8
Initial: Low
PCH_GPIO12 K9 U2 GATEA20
LAN_PHY_PWR_CTRL / GPIO12 A20GATE GATEA20 43
PCH_GPIO15
For Optimus T7 GPIO15
DGPU_PWR_EN2 R14 1 DGPU_PWR_EN_R AA2 CLK_CPU_BCLK#
13,46,56 DGPU_PWR_EN
0_0402_5% SATA4GP / GPIO16 CLKOUT_BCLK0_N / CLKOUT_PCIE8N AM3 CLK_CPU_BCLK# 5
PCH_GPIO17 F38 CLK_CPU_BCLK
TACH0 / GPIO17 CLKOUT_BCLK0_P / CLKOUT_PCIE8P AM1 CLK_CPU_BCLK 5
PROJECT_ID1 Y7 BG10 PECI
SCLOCK / GPIO22 PECI PECI 5

GPIO
H10 T1 KB_RST#
GPIO24 RCIN# KB_RST# 43
On-Die PLL VR H_PWRGOOD
AB12 GPIO27 PROCPWRGD BE10 H_PWRGOOD 5

CPU
High = Enabled (Default)
PCH_GPIO27 PCH_GPIO28 V13 BD10 THRMTRIP_PCH# 1 2
Low = Disabled GPIO28 THRMTRIP# H_THERMTRIP# 5
R212 56_0402_1%
PROJECT_ID2 M11 STP_PCI# / GPIO34
1 2 +VTT
GPIO35 V6 R210 56_0402_1%
SATACLKREQ# / GPIO35
+3VS DGPU_PWR_EN 2 @ R35 1GPIO36 AB7 BA22
C 0_0402_5% SATA2GP / GPIO36 TP1 C
1 2 PCH_GPIO1 VGA_PRSNT_L# AB13 SATA3GP / GPIO37 TP2 AW22
R214 10K_0402_5%
1 2 PCH_GPIO6 PCH_GPIO38 V3 SLOAD / GPIO38 TP3 BB22
R218 10K_0402_5% +3VS +3VS +3VS
1 2 EC_SCI# PCH_GPIO39 P3 SDATAOUT0 / GPIO39 TP4 AY45
R224 10K_0402_5%

2
1 @ 2 DGPU_PWR_EN_R PCH_GPIO45 H3 AY46
R221 10K_0402_5% PCIECLKRQ6# / GPIO45 TP5 R255 R216 R330
1 2 PCH_GPIO17 5 RST_GATE
RST_GATE F1 PCIECLKRQ7# / GPIO46 TP6 AV43 10K_0402_5% 10K_0402_5% 10K_0402_5%
R220 10K_0402_5% OPT@ NHDMI@ TPM@
1 2 VGA_PRSNT_L# GPIO48 AB6 AV45

1
R215 8.2K_0402_5% SDATAOUT1 / GPIO48 TP7 PROJECT_ID2 PROJECT_ID1 PROJECT_ID0
28 PROJECT_ID0
1 2 PCH_GPIO38 43 THM_ALT#
THM_ALT# AA4 SATA5GP / GPIO49 TP8 AF13

2
R217 10K_0402_5%
1 2 PCH_GPIO39 OPTIMUS_DET# F8 GPIO57 TP9 M18 R416 R415 R331
R254 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
1 2 PCH_GPIO0 TP10 N18 UMA@ HDMI@ NTPM@
R260 10K_0402_5%

1
2 @ 1GPIO36 A4 AJ24
R274 1K_0402_5% VSS_NCTF_1 TP11
A49
NCTF

@ VSS_NCTF_2 RSVD
1 2 GPIO48 A5 VSS_NCTF_3 TP12 AK41
R257 10K_0402_5% A50 VSS_NCTF_4
1 2 THM_ALT# A52 VSS_NCTF_5 TP13 AK42
R259 10K_0402_5% A53 VSS_NCTF_6
B2 VSS_NCTF_7 TP14 M32
+3VALW B4 VSS_NCTF_8
B52 VSS_NCTF_9 TP15 N32
PROJECT_ID2PROJECT_ID1 PROJECT_ID0 SKU.
B53 VSS_NCTF_10
B B
1 2 EC_SMI# BE1 VSS_NCTF_11 TP16 M30
R225 10K_0402_5% BE53 VSS_NCTF_12 0 0 0 NCL60 UMA with HDMI; w/o
1 UMA@ 2 OPTIMUS_DET# BF1 VSS_NCTF_13 TP17 N30
R226 10K_0402_5% BF53 VSS_NCTF_14 TPM.
1
R227
2 PCH_GPIO15
1K_0402_5%
BH1 VSS_NCTF_15 TP18 H12 0 1 0 NCL60 UMA without HDMI; w/o
BH2 VSS_NCTF_16
1 2 PCH_GPIO28 BH52 VSS_NCTF_17 TP19 AA23 TPM.
R242 10K_0402_5% BH53 VSS_NCTF_18 1 0 1 NCL61 SW with HDMI; with
1 2 PCH_GPIO45 BJ1 AB45
R222 10K_0402_5% BJ2
VSS_NCTF_19
VSS_NCTF_20
NC_1
TPM.
1
R223
2 RST_GATE
10K_0402_5%
BJ4 VSS_NCTF_21 NC_2 AB38 1 0 0 NCL61 SW with HDMI; w/o
BJ49 VSS_NCTF_22
1 2 PCH_GPIO12 BJ5 VSS_NCTF_23 NC_3 AB42 TPM.
R219 10K_0402_5% BJ50 VSS_NCTF_24
BJ52 VSS_NCTF_25 NC_4 AB41
BJ53 VSS_NCTF_26
D1 VSS_NCTF_27 NC_5 T39
D2 VSS_NCTF_28 Not pull low
D53 VSS_NCTF_29
E1 P6 internal pull up
VSS_NCTF_30 INIT3_3V#
E53 VSS_NCTF_31
1 OPT@ 2 OPTIMUS_DET# TP24 C10 Internal: Pull up 20k
R235 10K_0402_5%
During Reset: High
1 OPT@ 2 DGPU_PWR_EN IBEXPEAK-M QV20 A0_FCBGA1071
R59 1K_0402_5% Initial: High
1 2 GPIO48
R160 47K_0402_5%
1 @ 2 GPIO35
A
R228 10K_0402_5% A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH_CPU/GPIO
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Wednesday, April 14, 2010 Sheet 33 of 57
5 4 3 2 1
 5 4 3 2 1

U11J POWER +VTT

AP51 V24
VCCACLK[1] VCCIO[5]
52mA VCCIO[6]
V26 1
AP53 3062mA Y24 C316
VCCACLK[2] VCCIO[7]
VCCIO[8] Y26
1U_0402_6.3V4Z
2
AF23 V28
VCCLAN[1] VCCSUS3_3[1]
U28
VCCSUS3_3[2]
VccLAN connect to GND if Intel LAN is disabled AF24
VCCLAN[2] 320mA VCCSUS3_3[3]
U26
VCCSUS3_3[4] U24
VCCSUS3_3[5] P28
2 1 +TP_PCH_VCCDSW Y20 P26 +3VALW
D C320 0.1U_0402_16V4Z DCPSUSBYP VCCSUS3_3[6] D
N28
VCCSUS3_3[7]

+VTT
Near AD38 AD38
VCCSUS3_3[8]
N26
M28
VCCME[1] VCCSUS3_3[9]
1 1 1 VCCSUS3_3[10] M26 2 2
AD39 L28 C321 C325

USB
C391 C322 C318 VCCME[2] VCCSUS3_3[11]
L26
VCCSUS3_3[12]
If two VccME rails can be 22U_0805_6.3V6M 22U_0805_6.3V6M 1U_0402_6.3V4Z AD41
VCCME[3] VCCSUS3_3[13]
J28 0.1U_0402_16V4Z 0.1U_0402_16V4Z
@ 2 2 2 J26 1 1
combined, only total 2 x 22 µF and AF43
VCCSUS3_3[14]
H28
2 x 1 µF caps are necessary VCCME[4] VCCSUS3_3[15]
163mA VCCSUS3_3[16]
H26
AF41 G28
VCCME[5] VCCSUS3_3[17]
1849mA VCCSUS3_3[18]
G26
AF42 F28
VCCME[6] VCCSUS3_3[19]
Near V39 V39
VCCSUS3_3[20]
F26
E28 +3VALW +5VALW
VCCME[7] VCCSUS3_3[21]
1 1 1 E26

Clock and Miscellaneous

VCCSUS3_3[22]

CH751H-40PT_SOD323-2
V41 C28
C447 C323 C324 VCCME[8] VCCSUS3_3[23]
C26
VCCSUS3_3[24]

1
22U_0805_6.3V6M 22U_0805_6.3V6M 1U_0402_6.3V4Z V42 B27
2 @ 2 2 VCCME[9] VCCSUS3_3[25] R344
VCCSUS3_3[26] A28
Y39 A26 D16
VCCME[10] VCCSUS3_3[27] 100_0402_1%
Y41 U23

2
VCCME[11] VCCSUS3_3[28] +3VS +5VS
Y42 VCCME[12] VCCIO[56] V23 +VTT

1
F24 +PCH_VCC5REFSUS 2 1
V5REF_SUS C326 1U_0402_6.3V4Z D17 R346
+VCCRTCEXT
> 1mA
1 2 V9 CH751H-40PT_SOD323-2
C327 0.1U_0402_16V4Z DCPRTC 100_0402_1%

2
L17 1 2 196mA > 1mA K49 +PCH_VCC5REF +PCH_VCC5REF
C +VTT V5REF C
10UH_LB2012T100MR_20% 1 +PCH_VRM AU24

PCI/GPIO/LPC
VCCVRM[3]
1 1
1

C328 + C329 +3VS C330

+1.05VS_PCHDPLL_A
68mA VCC3_3[8]
J38
220U_B2_2.5VM_R15 1U_0402_6.3V4Z R347 BB51
0_0603_5% VCCADPLLA[1] 1U_0402_6.3V4Z
BB53 L38
2 2 @ VCCADPLLA[2] VCC3_3[9] 2
2
69mA M36 C333
2

L18 1 +1.05VS_PCHDPLL_B VCC3_3[10] 0.1U_0402_16V4Z

2 BD51
VCCADPLLB[1] 375mA
10UH_LB2012T100MR_20% 1 BD53 N36
VCCADPLLB[2] VCC3_3[11] 1
1
C331 + C332 +VTT 1U_0402_6.3V4Z AH23 P36
220U_B2_2.5VM_R15 1U_0402_6.3V4Z VCCIO[21] VCC3_3[12]
1 1 1 AJ35
VCCIO[22]
AH35 U35
2 2 C334 C335 C336 VCCIO[23] VCC3_3[13] +3VS
1U_0402_6.3V4Z AF34 3062mA
2 2 2 VCCIO[2]
AD13 2 1
1U_0402_6.3V4Z VCC3_3[14] C337 0.1U_0402_16V4Z
AH34
VCCIO[3]
Short AF34, AH34 and AF32 power
AF32
for HDMI Deep Color VCCIO[4]
AK3
+VCCSST VCCSATAPLL[1]
1 2 V12
DCPSST 31mA VCCSATAPLL[2]
AK1
C338 0.1U_0402_16V4Z
+VTT
1 2 +V1.1A_INT_VCCSUS Y22
C341 0.1U_0402_16V4Z DCPSUS
AH22
VCCIO[9]

+3VALW 163mA
P18
VCCSUS3_3[29] 196mA VCCVRM[4] AT20 +PCH_VRM
1 2 U19

SATA
C343 0.1U_0402_16V4Z VCCSUS3_3[30]

PCI/GPIO/LPC
AH19 +VTT
B VCCIO[10] B
U20 VCCSUS3_3[31] 1
AD20 C342
VCCIO[11] 1U_0402_6.3V4Z
U22
VCCSUS3_3[32]
For HDA power rail to +1.5VALW +3VS VCCIO[12]
AF22
2
375mA VCCIO[13]
AD19
1 2 V15
VCC3_3[5] 3062mA VCCIO[14]
AF20
C344 0.1U_0402_16V4Z AF19
U54 @ VCCIO[15]
V16 AH20
VCC3_3[6] VCCIO[16]
+3VALW +VTT
2 3 +1.5VALW Y16 AB19
IN OUT VCC3_3[7] VCCIO[17]
VCCIO[18] AB20
1 2 AB22
GND C345 4.7U_0603_6.3V6K VCCIO[19] +VTT
> 1mA VCCIO[20]
AD22
1

APL5301-15DC-TRL_SOT89-3 1 2 AT18
C485 1 C486 C346 0.1U_0402_16V4Z V_CPU_IO[1] +PCH_VCCME1 R351 0_0402_5%
AA34 1 2
CPU

1U_0603_10V6K 4.7U_0805_6.3V6K VCCME[13] +PCH_VCCME2 R352 0_0402_5%

1 2 Y34 1 2
2

@ @ C347 0.1U_0402_16V4Z VCCME[14] +PCH_VCCME3 R353 0_0402_5%

AU18
V_CPU_IO[2] 1849mA VCCME[15]
Y35
+PCH_VCCME4 R354
1 2
0_0402_5%
AA35 1 2
+RTCVCC VCCME[16]
RTC

1 2 A12 2mA 6mA L30 +VCC_HDA 1 2 +3VALW

VCCRTC VCCSUSHDA
HDA

C351 0.1U_0402_16V4Z R384 0_0402_5%

1 2 IBEXPEAK-M QV20 A0_FCBGA1071 1 @ 2 +1.5VALW

C348 1U_0402_6.3V4Z R437 0_0402_5%

1 2 1 Reserve +1.5VALW for HDA

C349 0.1U_0402_16V4Z C350

1U_0402_6.3V4Z
2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH_POWER-2
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Wednesday, March 24, 2010 Sheet 34 of 57
5 4 3 2 1
 5 4 3 2 1

+VTT +3VS
U11G POWER +3VS_VCCADAC
L12
AB24 VCCCORE[1] VCCADAC[1] AE50 2 1
1 1 AB26 69mA 2 1 BLM18PG181SN1D_0603
C295 C294 VCCCORE[2]
AB28 VCCCORE[3] VCCADAC[2] AE52
10U_0805_10V4Z 1U_0402_6.3V4Z AD26 C296 C297 C298
VCCCORE[4]

CRT
D AD28 AF53 0.01U_0402_25V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z D
2 2 VCCCORE[5] VSSA_DAC[1] 1 2
AF26 VCCCORE[6]

VCC CORE
AF28 VCCCORE[7] VSSA_DAC[2] AF51
AF30 VCCCORE[8] close to AE50
AF31 VCCCORE[9]
AH26 VCCCORE[10]
AH28 VCCCORE[11]
AH30 VCCCORE[12]
AH31 > 1mA AH38 +VCCA_LVDS 1 2 +3VS
VCCCORE[13] VCCALVDS R343 0_0402_5%
AJ30 VCCCORE[14]
AJ31 VCCCORE[15] VSSA_LVDS AH39

+VTT 1432mA +VCCTX_LVDS

VCCTX_LVDS[1] AP43 1 2 +1.8VS
59mA AP45 R137 0_0603_5%
VCCTX_LVDS[2]
AT46

LVDS
VCCTX_LVDS[3] C300 C299
AK24 VCCIO[24] VCCTX_LVDS[4] AT45
0.01U_0402_25V4Z 0.01U_0402_25V4Z
+3VS
BJ24 VCCAPLLEXP 40mA
VCC3_3[2] AB34

AN20 VCCIO[25] 375mA VCC3_3[3] AB35

AN22 2

HVCMOS
VCCIO[26] 0.1U_0402_16V4Z
AN23 VCCIO[27] VCC3_3[4] AD35
AN24 C303
VCCIO[28]
AN26 VCCIO[29] 1
AN28 VCCIO[30] close to AB34
BJ26 VCCIO[31]
C BJ28 C
VCCIO[32]
AT26 VCCIO[33]
AT28 +PCH_VRM +1.8VS
+VTT VCCIO[34]
AU26 VCCIO[35]
AU28 VCCIO[36] 2 1
1 2 AV26 R336 0_0402_5%
C304 10U_0805_10V4Z VCCIO[37]
AV28 VCCIO[38] 196mA VCCVRM[2] AT24 +PCH_VRM
1 2 AW26 VCCIO[39]
C305 1U_0402_6.3V4Z AW28 3062mA
VCCIO[40] +VTT

DMI
1 2 BA26 VCCIO[41] VCCDMI[1] AT16
C306 1U_0402_6.3V4Z BA28 61mA
VCCIO[42] +PCH_VCCDMI
1 2 BB26 VCCIO[43] VCCDMI[2] AU16 1 2
C307 1U_0402_6.3V4Z BB28 1 R335 0_0603_5%
VCCIO[44] C309
1 2 BC26 VCCIO[45]

PCI E*
C308 1U_0402_6.3V4Z BC28 1U_0402_6.3V4Z
VCCIO[46]
BD26 VCCIO[47] 2
BD28 VCCIO[48] close to AT16
BE26 VCCIO[49] VCCPNAND[1] AM16
BE28 VCCIO[50] VCCPNAND[2] AK16
BG26 VCCIO[51] VCCPNAND[3] AK20
BG28 AK19 +1.8VS_PCH_NAND +1.8VS
VCCIO[52] VCCPNAND[4]
BH27 VCCIO[53] VCCPNAND[5] AK15
156mA VCCPNAND[6] AK13 1
R338
2
0_0603_5%
AN30 VCCIO[54] VCCPNAND[7] AM12 2

NAND / SPI
AN31 VCCIO[55] VCCPNAND[8] AM13
+3VS AM15 C311
VCCPNAND[9] 0.1U_0402_16V4Z
1
2 1 AN35 VCC3_3[1] 375mA close to Ak13
C310 0.1U_0402_16V4Z
B B

+PCH_VRM AT22 VCCVRM[1] +3VS

BJ18 VCCFDIPLL 37mA VCCME3_3[1] AM8
VCCME3_3[2] AM9
FDI

+VTT AM23 VCCIO[1] 85mA VCCME3_3[3] AP11 2

VCCME3_3[4] AP9
C313 0.1U_0402_16V4Z
1
close to AM8
IBEXPEAK-M QV20 A0_FCBGA1071

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH_POWER-1
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Wednesday, March 24, 2010 Sheet 35 of 57
5 4 3 2 1
 5 4 3 2 1

U11I
AY7 VSS[159] VSS[259] H49
B11 H5 U11H
VSS[160] VSS[260]
B15 VSS[161] VSS[261] J24 AB16 VSS[0]
B19 VSS[162] VSS[262] K11
B23 VSS[163] VSS[263] K43 AA19 VSS[1] VSS[80] AK30
B31 VSS[164] VSS[264] K47 AA20 VSS[2] VSS[81] AK31
B35 VSS[165] VSS[265] K7 AA22 VSS[3] VSS[82] AK32
B39 VSS[166] VSS[266] L14 AM19 VSS[4] VSS[83] AK34
B43 VSS[167] VSS[267] L18 AA24 VSS[5] VSS[84] AK35
B47 VSS[168] VSS[268] L2 AA26 VSS[6] VSS[85] AK38
D B7 VSS[169] VSS[269] L22 AA28 VSS[7] VSS[86] AK43 D
BG12 VSS[170] VSS[270] L32 AA30 VSS[8] VSS[87] AK46
BB12 VSS[171] VSS[271] L36 AA31 VSS[9] VSS[88] AK49
BB16 VSS[172] VSS[272] L40 AA32 VSS[10] VSS[89] AK5
BB20 VSS[173] VSS[273] L52 AB11 VSS[11] VSS[90] AK8
BB24 VSS[174] VSS[274] M12 AB15 VSS[12] VSS[91] AL2
BB30 VSS[175] VSS[275] M16 AB23 VSS[13] VSS[92] AL52
BB34 VSS[176] VSS[276] M20 AB30 VSS[14] VSS[93] AM11
BB38 VSS[177] VSS[277] N38 AB31 VSS[15] VSS[94] BB44
BB42 VSS[178] VSS[278] M34 AB32 VSS[16] VSS[95] AD24
BB49 VSS[179] VSS[279] M38 AB39 VSS[17] VSS[96] AM20
BB5 VSS[180] VSS[280] M42 AB43 VSS[18] VSS[97] AM22
BC10 VSS[181] VSS[281] M46 AB47 VSS[19] VSS[98] AM24
BC14 VSS[182] VSS[282] M49 AB5 VSS[20] VSS[99] AM26
BC18 VSS[183] VSS[283] M5 AB8 VSS[21] VSS[100] AM28
BC2 VSS[184] VSS[284] M8 AC2 VSS[22] VSS[101] BA42
BC22 VSS[185] VSS[285] N24 AC52 VSS[23] VSS[102] AM30
BC32 VSS[186] VSS[286] P11 AD11 VSS[24] VSS[103] AM31
BC36 VSS[187] VSS[287] AD15 AD12 VSS[25] VSS[104] AM32
BC40 VSS[188] VSS[288] P22 AD16 VSS[26] VSS[105] AM34
BC44 VSS[189] VSS[289] P30 AD23 VSS[27] VSS[106] AM35
BC52 VSS[190] VSS[290] P32 AD30 VSS[28] VSS[107] AM38
BH9 VSS[191] VSS[291] P34 AD31 VSS[29] VSS[108] AM39
BD48 VSS[192] VSS[292] P42 AD32 VSS[30] VSS[109] AM42
BD49 VSS[193] VSS[293] P45 AD34 VSS[31] VSS[110] AU20
BD5 VSS[194] VSS[294] P47 AU22 VSS[32] VSS[111] AM46
BE12 VSS[195] VSS[295] R2 AD42 VSS[33] VSS[112] AV22
BE16 VSS[196] VSS[296] R52 AD46 VSS[34] VSS[113] AM49
BE20 VSS[197] VSS[297] T12 AD49 VSS[35] VSS[114] AM7
C BE24 T41 AD7 AA50 C
VSS[198] VSS[298] VSS[36] VSS[115]
BE30 VSS[199] VSS[299] T46 AE2 VSS[37] VSS[116] BB10
BE34 VSS[200] VSS[300] T49 AE4 VSS[38] VSS[117] AN32
BE38 VSS[201] VSS[301] T5 AF12 VSS[39] VSS[118] AN50
BE42 VSS[202] VSS[302] T8 Y13 VSS[40] VSS[119] AN52
BE46 VSS[203] VSS[303] U30 AH49 VSS[41] VSS[120] AP12
BE48 VSS[204] VSS[304] U31 AU4 VSS[42] VSS[121] AP42
BE50 VSS[205] VSS[305] U32 AF35 VSS[43] VSS[122] AP46
BE6 VSS[206] VSS[306] U34 AP13 VSS[44] VSS[123] AP49
BE8 VSS[207] VSS[307] P38 AN34 VSS[45] VSS[124] AP5
BF3 VSS[208] VSS[308] V11 AF45 VSS[46] VSS[125] AP8
BF49 VSS[209] VSS[309] P16 AF46 VSS[47] VSS[126] AR2
BF51 VSS[210] VSS[310] V19 AF49 VSS[48] VSS[127] AR52
BG18 VSS[211] VSS[311] V20 AF5 VSS[49] VSS[128] AT11
BG24 VSS[212] VSS[312] V22 AF8 VSS[50] VSS[129] BA12
BG4 VSS[213] VSS[313] V30 AG2 VSS[51] VSS[130] AH48
BG50 VSS[214] VSS[314] V31 AG52 VSS[52] VSS[131] AT32
BH11 VSS[215] VSS[315] V32 AH11 VSS[53] VSS[132] AT36
BH15 VSS[216] VSS[316] V34 AH15 VSS[54] VSS[133] AT41
BH19 VSS[217] VSS[317] V35 AH16 VSS[55] VSS[134] AT47
BH23 VSS[218] VSS[318] V38 AH24 VSS[56] VSS[135] AT7
BH31 VSS[219] VSS[319] V43 AH32 VSS[57] VSS[136] AV12
BH35 VSS[220] VSS[320] V45 AV18 VSS[58] VSS[137] AV16
BH39 VSS[221] VSS[321] V46 AH43 VSS[59] VSS[138] AV20
BH43 VSS[222] VSS[322] V47 AH47 VSS[60] VSS[139] AV24
BH47 VSS[223] VSS[323] V49 AH7 VSS[61] VSS[140] AV30
BH7 VSS[224] VSS[324] V5 AJ19 VSS[62] VSS[141] AV34
C12 VSS[225] VSS[325] V7 AJ2 VSS[63] VSS[142] AV38
C50 VSS[226] VSS[326] V8 AJ20 VSS[64] VSS[143] AV42
B B
D51 VSS[227] VSS[327] W2 AJ22 VSS[65] VSS[144] AV46
E12 VSS[228] VSS[328] W52 AJ23 VSS[66] VSS[145] AV49
E16 VSS[229] VSS[329] Y11 AJ26 VSS[67] VSS[146] AV5
E20 VSS[230] VSS[330] Y12 AJ28 VSS[68] VSS[147] AV8
E24 VSS[231] VSS[331] Y15 AJ32 VSS[69] VSS[148] AW14
E30 VSS[232] VSS[332] Y19 AJ34 VSS[70] VSS[149] AW18
E34 VSS[233] VSS[333] Y23 AT5 VSS[71] VSS[150] AW2
E38 VSS[234] VSS[334] Y28 AJ4 VSS[72] VSS[151] BF9
E42 VSS[235] VSS[335] Y30 AK12 VSS[73] VSS[152] AW32
E46 VSS[236] VSS[336] Y31 AM41 VSS[74] VSS[153] AW36
E48 VSS[237] VSS[337] Y32 AN19 VSS[75] VSS[154] AW40
E6 VSS[238] VSS[338] Y38 AK26 VSS[76] VSS[155] AW52
E8 VSS[239] VSS[339] Y43 AK22 VSS[77] VSS[156] AY11
F49 VSS[240] VSS[340] Y46 AK23 VSS[78] VSS[157] AY43
F5 VSS[241] VSS[341] P49 AK28 VSS[79] VSS[158] AY47
G10 VSS[242] VSS[342] Y5
G14 Y6 IBEXPEAK-M QV20 A0_FCBGA1071
VSS[243] VSS[343]
G18 VSS[244] VSS[344] Y8
G2 VSS[245] VSS[345] P24
G22 VSS[246] VSS[346] T43
G32 VSS[247] VSS[347] AD51
G36 VSS[248] VSS[348] AT8
G40 VSS[249] VSS[349] AD47
G44 VSS[250] VSS[350] Y47
G52 VSS[251] VSS[351] AT12
AF39 VSS[252] VSS[352] AM6
H16 VSS[253] VSS[353] AT13
H20 VSS[254] VSS[354] AM5
A H30 VSS[255] VSS[355] AK45 A
H34 VSS[256] VSS[356] AK39
H38 VSS[257] VSS[366] AV14
H42 VSS[258]

Security Classification Compal Secret Data Compal Electronics, Inc.

IBEXPEAK-M QV20 A0_FCBGA1071 200910/9 2010/01/23 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH_GND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Wednesday, March 24, 2010 Sheet 36 of 57
5 4 3 2 1
 5 4 3 2 1

SATA HDD
Conn. +5VS
Place closely JHDD SATA CONN.
1.2A
SATA ODD Conn
1 1 1 1
C356 C357 C358 C359
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 JODD
Close to JODD
GND 1
2 SATA_PTX_C_DRX_P4 C378 1 2 0.01U_0402_25V7K
D A+ SATA_PTX_DRX_P4 28 D
SSD HDD need 400mA for 3V(PHISON) 3 SATA_PTX_C_DRX_N4 C377 1 2 0.01U_0402_25V7K
+3VS A- SATA_PTX_DRX_N4 28
GND 4
+3VS rail reserve for SSD 5 SATA_PRX_DTX_N4 C376 1 2 0.01U_0402_25V7K
B- SATA_PRX_C_DTX_N4 28
6 SATA_PRX_DTX_P4 C375 1 2 0.01U_0402_25V7K
B+ SATA_PRX_C_DTX_P4 28
1 1 1 1 GND 7
C363 C364 C365 C366
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
@ @ @ @ 8
2 2 2 2 DP
+5V 9 +5VS_ODD
+5V 10
MD 11
15 GND GND 12
14 GND GND 13
Close to JHDD
JHDD SANTA_204901-1
1 CONN@
GND SATA_PTX_C_DRX_P1 C369 1
A+ 2 2 0.01U_0402_25V7K SATA_PTX_DRX_P1 28
3 SATA_PTX_C_DRX_N1 C367 1 2 0.01U_0402_25V7K
A- SATA_PTX_DRX_N1 28
GND 4
5 SATA_PRX_DTX_N1 C368 1 2 0.01U_0402_25V7K
B- SATA_PRX_C_DTX_N1 28
6 SATA_PRX_DTX_P1 C370 1 2 0.01U_0402_25V7K
B+ SATA_PRX_C_DTX_P1 28
GND 7

V33 8 +3VS
V33 9
V33 10
11 +5VS +5VS_ODD Place components closely ODD CONN.
GND
GND 12 1.1A
GND 13 2 1
14 R77 0_0805_5% 1 1 1 1 1
C V5 +5VS C
15 C352 C353 C354
V5 @ C355 C360
V5 16
17 10U_0805_10V4Z 10U_0805_10V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
GND 2 2 2 2 2
Reserved 18
GND 19
V12 20
23 NC V12 21
24 NC V12 22

SANTA_191901-1
CONN@

+5VALW USB/B to M/B Conn. +5VALW

C778

0.01U_0402_25V7K
1
1 +USB_VCCA
1
@ C301 + C80 U30
2 1 8
150U_B2_6.3V-M~D 470P_0402_50V7K~D @ GND OUT
2 IN OUT 7
2 2 3 6 R598
IN OUT +USB_VCCA
1 4 EN# FLG 5 2 1 USB_OC#2 32
C710 G528P1UF_SOP8 0_0402_5% C426 1 2 220U_6.3V_M_R17

+
1
B JUSB1 4.7U_0805_10V4Z C711 B
MIC_R 1 2 @
42 MIC_R 1
MIC_L 2 0.1U_0402_16V4Z C428 1 2 1000P_0402_50V7K
42 MIC_L 2 2
MIC_JD 3
42 MIC_JD 3
4 USB_EN#
HP_L 4 C389 1
42 HP_L 5 5 2 0.1U_0402_16V4Z
HP_R 6 W=60mils
42 HP_R 6
HP_JD 7
42 HP_JD 7
8 8
9 9
32 USB20_N1 10 10
32 USB20_P1 11 JUSB2
11
12 12 2 1 8 GND
32 USB20_N0 13 R190 0_0402_5% 7
13 GND
32 USB20_P0 14 14 6 GND
15 L15 @ 5
USB_OC#0 15 +5VALW GND
32 USB_OC#0 16 16 32 USB20_N2 3 3 4 4 4 VCC
USB_EN# 17 USB20_N2_R 3
17 USB20_P2_R USB_N
18 18 2 USB_P
+5VALW 19 19 32 USB20_P2 2 2 1 1 1 GND

1
20 20
21 R541 WCM2012F2SF-900T04_0805 SUYIN_020173MR004S52KZL
21 CONN@
22 22 10K_0402_5% 2 1
2 R189 0_0402_5%
23 GND1
24 USB_EN#
GND2
1

ACES_87213-2200G D Q58 D23 @

CONN@ 2 USB20_N2_R 2
G USB_EN 43
1
A S 2N7002_SOT23-3 USB20_P2_R 3 A
3

PJDLC05C_SOT23-3

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SATA-HDD/ODD/eSATA/USB
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Wednesday, April 14, 2010 Sheet 37 of 57
5 4 3 2 1
 5 4 3 2 1

D54
BLUE
28 SATA_LED# 1 2 1
R1098
2
820_0402_5%
+5VS SATA LED
HT-191NB_BLUE_0603

LED1
BLUE
43,45 PWR_ON_LED#
PWR_ON_LED# 1 2 1
R1101
2
820_0402_5%
+5VALW System Power LED
D HT-191NB_BLUE_0603 D

Amber LED3 R151

WL_BT_LED# 1 22 1 2 1
43 WL_BT_LED#
HT-191UD_Amber_0603
453_0402_1% R972
2 1
0_0603_5%
+3VS

+5VS
BT/WLAN LED
R973 0_0603_5%
@

LED2

BATT_CHG_LED#
Blue R970 1
43 BATT_CHG_LED# 1 B 2 2 1 2 0_0603_5% +3VALW
R131 220_0402_5% @

BATT_LOW_LED# 3 4 2 1 R971 2 1 0_0603_5%

Battery Charge LED
43 BATT_LOW_LED# A +5VALW
R148 453_0402_1%
Amber
HT-297UD/CB _BLUE/AMB_0603

C C

BlueTooth Interface TPM 1.2

+3VS +3VS Let C764 close pin 24

+3VS
2

2
R361 C396 Base I/O Address
100K_0402_5% 0.1U_0402_16V7K +3VALW
1
C764 0 = 02Eh
3

1 S +3VS TPM@
* 1 = 04Eh
1

G
43 BT_ON# 1 2 2 Q28 0.1U_0402_16V4Z
R362 47K_0402_5% 1 AO3413_SOT23 2
C390 D
1

B 0.01U_0402_25V7K B
+3VS
2

24
19
10
+BT_VCC

5
U36 R727 1 TPM@ 2 10K_0402_5% +3VS
2

VDD
VDD
VDD

VSB
R365
100K_0402_5%
LPC_AD0 SUS_STAT#_R R726 1 SUS_STAT# 30
28,39,43 LPC_AD0 26 LAD0 LPCPD# 28 2 0_0402_5%
LPC_AD1 23 9 @ 1 2 +3VS
28,39,43 LPC_AD1
1

LPC_AD2 LAD1 TESTB1/BADD TPM_TEST1 R661 1 R659 4.7K_0402_5%

28,39,43 LPC_AD2 20 LAD2 TEST1 8 2

1
R728 1 2 0_0402_5% LPC_AD3 17 0_0402_5% TPM@
BT_OFF# 39 28,39,43 LPC_AD3 LAD3
14 TPM_XTALO TPM@ R662
XTALO TPM_XTALI 4.7K_0402_5%
D XTALI 13
1

TPM @
BT_ON# 2 Q37 CLK_PCI_TPM 21 SLB 9635 TT 1.1

2
G 2N7002_SOT23-3 32 CLK_PCI_TPM LPC_FRAME# LCLK
28,39,43 LPC_FRAME# 22 LFRAME# GPIO2 2
S BUF_PLT_RST# 16 6
3

5,32 BUF_PLT_RST# SERIRQ LRESET# GPIO

28,43 SERIRQ PM_CLKRUN# 27 SERIRQ
2 1 R773 15 C766 TPM@
30,43 PM_CLKRUN# 0_0402_5% CLKRUN# 15P_0402_50V8J
+3VS 1 2 7 PP NC 1
R665 4.7K_0402_5% 3 TPM_XTALI CLK_PCI_TPM
NC
2

JBT TPM@ 12

GND
GND
GND
GND
NC

2
(MAX=200mA) R772 X3

10M_0402_5%
+BT_VCC 1 1 GND 9

1
1 2 @ 0_0402_5% 1 2 R669
USB20_P5 2 TPM@ SLB-9635-TT-1.2_TSSOP28 IN NC @ 10_0402_5%
32 USB20_P5 3

4
11
18
25
C398 C399 USB20_N5 3
32 USB20_N5 4 4 3
1

4 OUT NC

R668
4.7U_0805_10V4Z 0.1U_0402_16V4Z 5
39 BT_ACTIVE

1
2 5 TPM@ 32.768KHZ_12.5P_1TJS125BJ2A251
39 WLAN_ACTIVE 6 2

2
6 TPM@
A 7 7 A
8 10 TPM_XTALO C768
8 GND @ 15P_0402_50V8J
ACES_87213-0800G C767 1
CONN@ 15P_0402_50V8J
TPM@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BT/FP/B-CAS/Felica/MDC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Wednesday, April 14, 2010 Sheet 38 of 57
5 4 3 2 1
 Slot 1 Half PCIe Mini Card-WLAN

+3VS +3V_WLAN
40 mils +1.5VS +1.5VS_WLAN
For SED For SED
2 1 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z
R72 0_0805_5% 1 1 1 R73 0_0805_5% 1 1 1

1
CM1 CM2 CM3 C253 CM7 CM8 CM9 C254
47P_0402_50V8J 47P_0402_50V8J

2
2 2 2 @ 2 2 2 @
0.01U_0402_25V4Z 4.7U_0805_10V4Z 0.01U_0402_25V4Z 4.7U_0805_10V4Z

+1.5VS_WLAN +3V_WLAN
38 BT_OFF#
JWLAN1
R45 1 @ 2 0_0402_5% 1 2
30,40 EC_SWI# 1 2
R32 1 2 0_0402_5% 3 4
38 WLAN_ACTIVE 3 4
R22 1 2 0_0402_5% 5 6
38 BT_ACTIVE 5 6
7 8 LPC_FRAME#
29 CLKREQ_WLAN# 7 8 LPC_FRAME# 28,38,43
@ 9 10 LPC_AD3
9 10 LPC_AD3 28,38,43
11 12 LPC_AD2
29 CLK_WLAN# 11 12 LPC_AD2 28,38,43
13 14 LPC_AD1
29 CLK_WLAN 13 14 LPC_AD1 28,38,43
15 16 LPC_AD0
15 16 LPC_AD0 28,38,43
17 17 18 18
32 PCI_RST#
32 CLK_PCI_DEBUG 19 19 20 20 WL_OFF# 43
21 22 PLT_RST#
21 22 PLT_RST# 32,40,43
29 PCIE_PRX_WLANTX_N2 23 23 24 24
29 PCIE_PRX_WLANTX_P2 25 25 26 26
27 27 28 28
29 30 R24 1 @ 2 0_0402_5% PM_SMBCLK 11,12,25,29
29 30 R37 @
29 PCIE_PTX_C_WLANRX_N2 31 31 32 32 1 2 0_0402_5% PM_SMBDATA 11,12,25,29
29 PCIE_PTX_C_WLANRX_P2 33 33 34 34
35 36 USB20_N13_R R43 1 2 0_0402_5%
35 36 USB20_N13 32
37 38 USB20_P13_R R44 1 2 0_0402_5%
37 38 USB20_P13 32
+3V_WLAN 39 39 40 40
41 41 42 42 1 2 +3VS
43 44 RM6 100K_0402_5%
43 44
45 45 46 46
47 47 48 48
43 E51_TXD 1 2 49 49 50 50
43 E51_RXD 1R16 0_0402_5%
2 51 51 52 52
R17 0_0402_5% 53 54
NPTH NPTH
Debug card using 55 GND GND 56

ACES_88914-5204
CONN@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCIe-WLAN/JET/3G/TV/NewCard
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Wednesday, April 14, 2010 Sheet 39 of 57
 A B C D E

UL1
+3V_AVDDXTAL 1 RL8 2 +3V_LAN
29 PCIE_PRX_C_LANTX_P1 CL1 1 2 0.1U_0402_16V7K PCIE_PRX_LANTX_P1 22 HSOP LED3/EEDO 31 0_0402_5%
LED1/EESK 37
29 PCIE_PRX_C_LANTX_N1 CL2 1 2 0.1U_0402_16V7K PCIE_PRX_LANTX_N1 23 HSON LED0 40 1 RL9 2 +LAN_VDD10
+LAN_VDD10 @ 0_0402_5%
PCIE_PTX_C_LANRX_P1 17 30 RL2 2 1 10K_0402_5%
29 PCIE_PTX_C_LANRX_P1 HSIP EECS/SCL
PCIE_PTX_C_LANRX_N1 18 32 RL1 2 1 10K_0402_5% LL1 1
+3V_LAN 29 PCIE_PTX_C_LANRX_N1 HSIN EEDI/SDA +LAN_REGOUT 1 2
@ 4.7UH_1008HC-472EJFS-A_5%_1008 CL11 +3V_LAN
1 2 EC_SWI# RL19
1 0_0402_5%
2 16 1 LAN_MDI0+ 1 2 0.1U_0402_16V4Z
29 CLKREQ_LAN# CLKREQB MDIP0 2
RL3 100K_0402_5% 2 LAN_MDI0-
PLT_RST# MDIN0 LAN_MDI1+ CL13 CL9
1 32,39,43 PLT_RST# 25 PERSTB MDIP1 4 1 2 1
5 LAN_MDI1- 22U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z CL10
CLK_LAN MDIN1 LAN_MDI2+ 2 1
29 CLK_LAN 19 REFCLK_P NC/MDIP2 7 1 2
CLK_LAN# 20 8 LAN_MDI2- 0.1U_0402_16V4Z CL4
29 CLK_LAN# REFCLK_N NC/MDIN2
10 LAN_MDI3+ 1 2
+3VS NC/MDIP3 LAN_MDI3- 0.1U_0402_16V4Z CL5
NC/MDIN3 11
LAN_X1 43 1 2
CKXTAL1 0.1U_0402_16V4Z CL6

1
LAN_X2 44 13 1 2
CKXTAL2 DVDD10 +LAN_VDD10
RL6 29 0.1U_0402_16V4Z CL7
1K_0402_1% DVDD10
DVDD10 41
EC_SWI# 28 +LAN_VDD10 +LAN_EVDD10
30,39 EC_SWI# LANWAKEB

2
ISOLATEB 26 27 2 1
ISOLATEB DVDD33 +3V_LAN
39 0_0603_5% LL2 1 2
DVDD33 +3V_LAN
RL28 1 2 1K_0402_5% 14 12 +3V_LAN CL18 CL17
RL7 RL21 2 NC/SMBCLK AVDD33 +3V_AVDDXTAL
1 10K_0402_5% 15 NC/SMBDATA AVDD33 42 1U_0402_6.3V4Z 0.1U_0402_16V4Z

1
15K_0402_5% RL22 1 2 1K_0402_5% 38 47 2 1
+3V_LAN GPO/SMBALERT AVDD33 +LAN_VDD10
48 RL4
AVDD33
0_0402_5%
ENSWREG 33 1 2
ENSWREG 0.1U_0402_16V4Z CL19
21 +LAN_EVDD10

2
EVDD10 ENSWREG
+LAN_VDDREG 34 VDDREG 1 2
+3VALW 35 3 0.1U_0402_16V4Z CL20
VDDREG AVDD10 +LAN_VDD10

1
AVDD10 6 1 2
+3VALW 9 RL23 0.1U_0402_16V4Z CL21
AVDD10
1 2 46 RSET AVDD10 45 0_0402_5% 1 2
RL5 2.49K_0402_1% +3V_LAN +LAN_VDDREG 0.1U_0402_16V4Z CL22
@
1

2 2 24 36 +LAN_REGOUT 1 2 2

2
R147 C483 GND REGOUT 0.1U_0402_16V4Z CL23
49 PGND 2 1
100K_0402_5% 0.1U_0402_16V7K 0_0603_5% LL3 1 2 1 2
0.1U_0402_16V4Z CL24
2

1 RTL8111E-GR_QFN48_6X6 CL28 CL29 1 2

2

S
R432 Q51 PJ29 4.7U_0603_6.3V6K 0.1U_0402_16V4Z 0.1U_0402_16V4Z CL25
2

1 2 2
G 2 1
43 WOL_EN# JUMP_43X79
@
1

47K_0402_5% 2
D
1

AO3413_SOT23
1

C482 +3V_LAN YL1

@ 0.01U_0402_25V7K LAN_X1 1 2 LAN_X2
1
1 1 25MHZ_20PF_7A25000012
1 1
C681 C682
4.7U_0805_10V4Z 1U_0402_6.3V4Z CL26 CL27
@ 2 2 27P_0402_50V8J 27P_0402_50V8J
2 2

JLAN

RJ45_MIDI3- 8 PR4-
+LAN_VDD10 +AVDD_CEN RJ45_MIDI3+ 7
3 PR4+ 3
RJ45_MIDI1- 6 PR2-
2 1
0_0603_5% LL4 RJ45_MIDI2- 5 PR3-
RJ45_MIDI2+ 4 PR3+
UL4 RJ45_MIDI1+ 3
CL45 1 +AVDD_CEN MCT3 PR2+
2 0.1U_0402_16V4Z 1 TCT1 MCT1 24 RL26 2 1 75_0402_5%
LAN_MDI3- 2 23 RJ45_MIDI3- RJ45_MIDI0- 2
LAN_MDI3+ TD1+ MX1+ RJ45_MIDI3+ PR1-
3 TD1- MX1- 22 GND 10
CL35 1 2 0.1U_0402_16V4Z 4 21 MCT2 RL24 2 1 75_0402_5% RJ45_MIDI0+ 1
LAN_MDI2- TCT2 MCT2 RJ45_MIDI2- PR1+
5 TD2+ MX2+ 20 GND 9
LAN_MDI2+ 6 19 RJ45_MIDI2+
CL44 1 TD2- MX2- MCT1
2 0.1U_0402_16V4Z 7 TCT3 MCT3 18 RL25 2 1 75_0402_5%
LAN_MDI1- 8 17 RJ45_MIDI1-
LAN_MDI1+ TD3+ MX3+ RJ45_MIDI1+
9 TD3- MX3- 16
CL43 1 2 0.1U_0402_16V4Z 10 15 MCT0 RL27 2 1 75_0402_5% RJ45_GND TYCO_1734819_8P-T
LAN_MDI0- TCT4 MCT4 RJ45_MIDI0- CONN@
11 TD4+ MX4+ 14
LAN_MDI0+ 12 13 RJ45_MIDI0+
TD4- MX4-
GSL5009LF
Place close to TCT pin RJ45_GND 1 2 1000P_1808_3KV7K LANGND
CL36 1 1
CL37 CL38

0.1U_0402_16V4Z 4.7U_0603_6.3V6K
2 2
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/05 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCIe-LAN-RTL8105E/8111E
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Wednesday, April 14, 2010 Sheet 40 of 57
A B C D E
 5 4 3 2 1

SD,MMC,MS muti-function pin define

MDIO SD Card MMC Card MS Card
PIN Name PIN Name PIN Name PIN Name
SD_WP/MS_CLK SD_CLK/MSD2 SP1 SP1 SP1

1
SP2
R515 R517
SP3
10_0402_5% 10_0402_5%
SP4

2
D 1 1 SP5 D
C610 C611
SP6
10P_0402_50V8J 10P_0402_50V8J
2 2
SP7
SP8
SP9
SP10
change to 100p
2 1 C616 @ 100P_0402_50V8J U23 SP11
R527 1 2 6.19K_0402_1% 1 AV_PLL 20mil (+1.8V internal regulator)
REFE
+3VS_CR_VCC GPIO0 17 SP12
USB20_N12 2
32 USB20_N12 DM
USB20_P12 CLK_SD_48M_R 1 R528 2 0_0402_5% SP13
40mil 32 USB20_P12 3 DP CLK_IN 24 CLK_SD_48M 25

+3VS 1 R533 2 0_0603_5% 4 3V3_IN XD_D7 23 1 R529 2 0_0402_5%

CLK_48M_PCH 29 SP14
+VCC_OUT 5 @
@ CARD_3V3 MS_BS
+3VALW 1 2 6 V18 SP14 22 SP15
R520 0_0603_5% 1 C618 21 SDDAT2

1U_0603_10V4Z
1 SP13
C614 7 20 SDDAT3/MSD1 SP16
C617 XD_CD# SP12
SP11 19
4.7U_0805_10V4Z 0.1U_0402_16V4Z SD_WP/MS_CLK 8 18 SD_CMD SP17
2 2 MS_INS# SP1 SP10 MSD0
9 SP2 SP9 16
SDDAT1 10 15 SD_CLK/MSD2 SP18
SP3 SP8

EPAD
SDDAT0 11 14
MSD3 SP4 SP7 SD_CD#
12 SP5 SP6 13 SP19
C C
RTS5138-GR_QFN24_4X4

25
SD_CLK/MSD2 1 R538 2 0_0402_5% SD_CLK/MSD2_R
SD_WP/MS_CLK1 R539 2 0_0402_5% SD_WP/MS_CLK_R

+VCC_3IN1

JREAD
B SD_WP/MS_CLK_R B
1 SD-WP
SDDAT1 2
SDDAT0 SD-DAT1
3 SD-DAT0
4 SD-GND
5 MS-GND
C878 MS_BS 6
+VCC_3IN1 SD_CLK/MSD2_R MS-BS
100P_0402_50V8J 2 1 @ CLK_SD_48M_R 7 SD-CLK
SDDAT3/MSD1
40mil MSD0
8
9
MS-DAT1
+VCC_OUT MS-DAT0
1 R532 2 10 SD-VCC
0_0603_5% SD_CLK/MSD2_R 11

10U_0805_10V4Z
MS-DAT2
1 1 12 SD-GND
MS_INS# 13
C623 C624 C625 MSD3 MS-INS
14 MS-DAT3
4.7U_0805_10V4Z @ SD_CMD 15
@ 2 2 0.1U_0402_16V4Z SD_WP/MS_CLK_R SD-CMD
16 MS-SCLK
17 MS-VCC
SDDAT3/MSD1 18 SD-DAT3
19 MS-GND
SDDAT2 20 22
SD_CD# SD-DAT2 GND1
21 SD-CD GND2 23

TAITW_R009-025-LR_NR
CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RTS5138-GR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Thursday, April 15, 2010 Sheet 41 of 59
5 4 3 2 1
 5 4 3 2 1

+5VS +VDDA R020 LINE_OUT# SPKL+

1 2
U39 +VDDA 1 2 +5VS R439 15K_0603_1%
3 4 0_0805_5%
@ VIN VOUT LINE_OUT SPKR+
R1422 1 2
+3VS_HD_DVDD

0.1U_0402_16V7K

0.1U_0402_16V7K
4.7U_0805_10V4Z

4.7U_0805_10V4Z
1 1 1 2 1 1 1 R440 15K_0603_1%
C1775 EN C1777
C1774 @ 10K_0402_5% 2 5 C1776 @ +DVDD_IO 1 2 +1.5VS
@ GND NC @ R1290 0_0603_5%
2 2 RT9198-4GPBG_SOT23-5 2 2
@ 1 2
R1300 @ 0_0603_5%

+3VS
U31
D +3VS_HD_DVDD R1280 1 D
2 9
MUTE# GND2 SPKL+ +5VAMP +5VS
1 8 J1
+AVDD_HD SD# OUTN
+VDDA 0_0603_5% C506 2 1 0.22U_0603_10V7K BYPASS 2 BYPASS GND1 7

0.1U_0402_16V7K

0.1U_0402_16V7K
L108 1 1 1 2 1 2 LINE_OUT# 3 6 2 1
C1397 C1398 C504 0.22U_0603_10V7K R438 5K_0603_1% INP VDD SPKR+ 2 1
1 2 4 5 1 1
FBM-L11-160808-800LMT_0603 10U_0805_10V6K INN OUTP JUMP_43X79

0.1U_0402_16V7K
1 LINE_OUTR 1 2 LINE_C_OUTR 1 2 LINE_OUT APA0715QBI-TRG_TDFN8_3X3 C1495 C1496
2 2

0.1U_0402_16V7K

0.1U_0402_16V7K
C3199 C503 0.1U_0402_50V4Z R428 10K_0603_1% 10U_0805_10V4Z 0.1U_0402_16V4Z

+DVDD_IO
1 1 1 2 2
C1440 C1470 LINE_OUTL 1 2 LINE_C_OUTL 1 2
C1450 C505 0.1U_0402_50V4Z R427 10K_0603_1%
2
2 2 2

25

38

9
U38
+3VS

DVDD_IO
AVDD1

AVDD2

DVDD
C1784 @ 1 2 1000P_0402_50V7K

1
R2405
14 35 LINEL 1 2 LINE_OUTL
LINE2_L LOUT1_L R1427 0_0402_5% 100K_0402_5%
15 36 LINER 1 2 LINE_OUTR
LINE2_R LOUT_R R1429 0_0402_5% D18

2
16 39 1 2 1000P_0402_50V7K EC_MUTE# 1 2 MUTE# 2 1 EAPD
MIC2_L LOUT2_L 43 EC_MUTE#
R261 1K_0402_5%
17 41 C1785 @ CH751H-40PT_SOD323-2
MIC2_R LOUT2_R
23 45
LINE1_L SPDIFO2
24 LINE1_R DMIC_CLK1/2 46 DMIC_CLK 25
18 43 @
C LINE1_VREFO NC R417 C
@
20 LINE2_VREFO DMIC_CLK3/4 44 1 2 1 2
10_0402_5% C023 10P_0402_50V8J
19 6 AZ_BITCLK_HD
MIC2_VREFO BITCLK AZ_BITCLK_HD 28
R08
MIC_L 1 2 1 2 C025 MIC_LEFT 21 8 SDIN_CODEC 1 2
MIC1_L SDATA_IN AZ_SDIN0_HD 28
R262 1K_0402_5% 2.2U_0603_10V6K 33_0402_5%
MIC_R 1 2 1 2 C024 MIC_RIGHT 22 30 C1042 2 1
R258 1K_0402_5% 2.2U_0603_10V6K MIC1_R CBN
MONO_IN 12 29 2.2U_0603_10V6K JP13
PCBEEP_IN CBP SPKR+ 1
SPKL+ 1
37 2
MONO_OUT C1786 @ 2
28 AZ_RST_HD# 11
RESET#

47P_0402_50V8J

47P_0402_50V8J
MIC1_VREFO 28 +MIC1_VREFO 1 2 1000P_0402_50V7K 3 GND

2
28 AZ_SYNC_HD 10 1 1 4
SYNC HP_RIGHT HP_R GND
32 1 R1360 2 75_0603_1% HP_R 37 @D45
@ D45
HPOUT_R

C1492

C1493
5 PSOT24C_SOT23 ACES_88231-02001
28 AZ_SDOUT_HD SDATA_OUT HP_LEFT HP_L
33 1 R1361 2 75_0603_1% HP_L 37
HPOUT_L 2 2
2 CONN@
25 DMIC_DAT 20K_0402_1% GPIO0/DMIC_DATA1/2
3 1 2 1000P_0402_50V7K

1
SENSE_A GPIO1/DMIC_DATA3/4
37 MIC_JD 1 R892 2 13 @ C1787
SENSE_B SENSE A
37 HP_JD 1 R013 2 34 27
5.1K_0402_1% SENSE B VREF
EAPD 47 40 1 R893 2 20K_0402_1% 1 10U_0805_10V6K 2
EAPD JDREF
48 31 C82 C1413
SPDIFO1 CPVEE
1U_0402_6.3V6K
2 1
2.2U_0603_10V6K

4 DVSS1 AVSS1 26 2
7 42
DVSS2 AVSS2
ALC272-GR_LQFP48_7X7 C1414
1
B R1441 1 B
2 0_0603_5%

R1105 1 2 0_0603_5%
+MIC1_VREFO
R1106 1 2 0_0603_5%
R1348 1

R1349 1
1 2.2U_0603_10V6K
4.7K_0402_5% @
C1043
4.7K_0402_5%

2
MIC_R 2

2
MIC_L

MIC_R 37

MIC_L 37

A A

C1471
R1183 2 1 10K_0402_5% 1 2 MONO_IN
43 EC_BEEP

R1188 0.1U_0402_16V7K
28,31 PCH_SPKR 2 1 10K_0402_5%
Security Classification Compal Secret Data
2

1
C1472 200910/9 2010/01/23 Title
Issued Date Deciphered Date
R1433
10K_0402_5% 0.1U_0402_16V7K
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDA CODEC ALC269
2 Size Document Number Rev
1

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Wednesday, April 14, 2010 Sheet 42 of 57
5 4 3 2 1
 5 4 3 2 1

+3VL
+3VL
0.1U_0402_16V4Z 0.1U_0402_16V4Z BATT_TEMPA 1 2
1 1 1 1 2 2 C442 C445 100P_0402_50V8J
C436 1 2 ACIN_D 1 2
C437 C438 C439 C440 C441 C446 100P_0402_50V8J
For EMI 0.1U_0402_16V4Z
2 2 2 2 1 1
1000P_0402_50V7K 0.1U_0402_16V4Z

111
125
0.1U_0402_16V4Z 1000P_0402_50V7K

22
33
96

67
9
CLK_PCI_EC U19

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
1
R377 TV tuner +3VS
10_0402_5% temperature
@ GATEA20 1 21 KB_LED
D 33 GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F T47 PAD D
KB_RST# 2 23 EC_BEEP R754 10K_0402_5%
2
33 KB_RST# SERIRQ KBRST#/GPIO01 BEEP#/PWM2/GPIO10 SM_SENSE# EC_BEEP 42 TMPTU1_SXP
1 28,38 SERIRQ 3 SERIRQ# FANPWM1/GPIO12 26 T48 PAD 1 2
LPC_FRAME# 4 27 ACOFF
28,38,39 LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF 49
C443 LPC_AD3 5 R757 10K_0402_5%
28,38,39 LPC_AD3 LPC_AD2 LAD3 TMPTU2_SXP
22P_0402_50V8J
2 28,38,39 LPC_AD2 7 LAD2 PWM Output 1 2
@ LPC_AD1 8 63 BATT_TEMPA
28,38,39 LPC_AD1 LPC_AD0 LAD1 BATT_TEMP/AD0/GPIO38 TMPTU1_SXP BATT_TEMPA 48
28,38,39 LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
ADP_I
T58 PAD +3VL
ADP_I/AD2/GPIO3A 65 ADP_I 49
CLK_PCI_EC 12 AD Input 66 ADP_V
32 CLK_PCI_EC PCICLK AD3/GPIO3B ADP_V 49
PLT_RST# 13 75 TMPTU2_SXP
32,39,40 PLT_RST# PCIRST#/GPIO05 AD4/GPIO42 T57 PAD
ECRST# 37 76 HDPACT
ECRST# SELIO2#/AD5/GPIO43 T56 PAD
EC_SCI# 20
33 EC_SCI# SCI#/GPIO0E
PM_CLKRUN# 1 2 38
30,38 PM_CLKRUN# R348 0_0402_5% CLKRUN#/GPIO1D VTTP_EN CAP_INT# @
DAC_BRIG/DA0/GPIO3C 68 VTTP_EN 51 1 2
@ 70 EN_DFAN1 R172 4.7K_0402_5%
EN_DFAN1/DA1/GPIO3D EN_DFAN1 6
DA Output 71 IREF
IREF/DA2/GPIO3E IREF 49
KSI0 55 72 CHGVADJ
KSI0/GPIO30 DA3/GPIO3F CHGVADJ 49
KSI1 56
KSI2 KSI1/GPIO31 +5VS
57 KSI2/GPIO32
KSI3 58 83 EC_MUTE#
+3VL KSI3/GPIO33 PSCLK1/GPIO4A EC_MUTE# 42
R378 KSI4 59 84 USB_EN
+3VL KSI4/GPIO34 PSDAT1/GPIO4B USB_EN 37
47K_0402_5% KSI5 60 85 TP_CLK 1 2
ECRST# KSI6 KSI5/GPIO35 PSCLK2/GPIO4C WL_BT_LED# R379 4.7K_0402_5%
2 1 61 KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D 86 WL_BT_LED# 38
1 2 KSO1 KSI7 62 87 TP_CLK TP_DATA 1 2
KSO0 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_DATA TP_CLK 45
2 1 R380 47K_0402_5% 39 88 R381 4.7K_0402_5%
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA 45
C444 0.1U_0402_16V4Z 1 2 KSO2 KSO1 40
R382 47K_0402_5% KSO2 KSO1/GPIO21
41 KSO2/GPIO22
KSO3 42 97 +3VALW
KSO3/GPIO23 SDICS#/GPXOA00 KILL_SW# 44
to avoid EC entry ENE test mode KSO4 43 98 WOL_EN#
KSO4/GPIO24 SDICLK/GPXOA01 WOL_EN# 40
KSO5 IAMT_EN LID_SW#
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
LID_SW#
IAMT_EN 28 2
47K_0402_5%
1
R383
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 LID_SW# 44
C KSO7 C
46 KSO7/GPIO27 SPI Device Interface
KSO8 47
KSO9 KSO8/GPIO28 EC_SI_SPI_SO
48 KSO9/GPIO29 SPIDI/RD# 119 EC_SI_SPI_SO 44
KSI[0..7] KSO10 49 120 EC_SO_SPI_SI
44 KSI[0..7] KSO10/GPIO2A SPIDO/WR# EC_SO_SPI_SI 44
KSO11 50 SPI Flash ROM 126 SPI_CLK SYSON 1 2
KSO[0..15] KSO11/GPIO2B SPICLK/GPIO58 SPI_CLK 44
KSO12 51 128 SPI_CS# R5 4.7K_0402_5%
44 KSO[0..15] KSO12/GPIO2C SPICS# SPI_CS# 44
KSO13 52
KSO14 KSO13/GPIO2D
53 KSO14/GPIO2E
KSO15 54 73 BT_ON# R349 330K_0402_5%
KSO15/GPIO2F CIR_RX/GPIO40 BT_ON# 38
RP7 81 74 CAP_INT# 1 @ 2
KSO16/GPIO48 CIR_RLC_TX/GPIO41 T46 PAD +3VALW
1 8 EC_SMB_CK1 82 89 FSTCHG
+3VL KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG 49
2 7 EC_SMB_DA1 90 BATT_FULL_LED# R341 330K_0402_5%
BATT_CHGI_LED#/GPIO52 BATT_CHG_LED# 38
3 6 EC_SMB_CK2 91 CAPS_LED# 1 2
+3VS CAPS_LED#/GPIO53 CAPS_LED# 45 +3VL
4 5 EC_SMB_DA2 EC_SMB_CK1 77 GPIO 92 BATT_LOW_LED#
48 EC_SMB_CK1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 BATT_LOW_LED# 38
EC_SMB_DA1 78 93 PWR_ON_LED# D21
48 EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 PWR_ON_LED# 38,45
2.2K_0804_8P4R_5% EC_SMB_CK2 79 SM Bus 95 SYSON ACIN_D 2 1
14,29 EC_SMB_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON 53 ACIN 30,49
EC_SMB_DA2 80 121 VR_ON
14,29 EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON 54
127 ACIN_D CH751H-40PT_SOD323-2
AC_IN/GPIO59

PM_SLP_S3# 6 100 EC_RSMRST#

30 PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# 30
PM_SLP_S5# 14 101 EC_LID_OUT#
30 PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# 29 +3VALW
EC_SMI# 15 102 EC_ON
33 EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON 45,50
For EMI THM_ALT# 16 103 TP_LED
33 THM_ALT# LID_SW#/GPIO0A EC_SWI#/GPXO06 T52 PAD
ESB_CK 17 104 PM_PWROK
PAD T49 SUSP#/GPIO0B ICH_PWROK/GPXO06 PM_PWROK 30
ESB_DAT 18 GPO 105 BKOFF# SLP_CHG# 2 1
PAD T50 PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# 25
@ SUS_PWR_ACK 19 GPIO 106 WL_OFF# R1428 10K_0402_5%
30 SUS_PWR_ACK EC_PME#/GPIO0D WL_OFF#/GPXO09 WL_OFF# 39
1 2 PLT_RST# INVT_PWM 25 107 EC_REV_SEL
25 INVT_PWM EC_THERM#/GPIO11 GPXO10
C819 0.1U_0402_16V4Z FAN_SPEED1 28 108
6 FAN_SPEED1 FAN_SPEED1/FANFB1/GPIO14 GPXO11
HDPLOCK 29
PAD T51 FANFB2/GPIO15
@ E51_TXD 30
39 E51_TXD EC_TX/GPIO16
B 1 2 SUSP# E51_RXD 31 110 PM_SLP_S4# B
39 E51_RXD EC_RX/GPIO17 PM_SLP_S4#/GPXID1 PM_SLP_S4# 30
C820 0.1U_0402_16V4Z ON/OFFBTN# 32 112 EC_ENBKL SUSP# R423 2 1 10K_0402_5%
45 ON/OFFBTN# ON_OFF/GPIO18 ENBKL/GPXID2 EC_ENBKL 25
PWR_SUSP_LED# 34 114
PAD T65 PWR_LED#/GPIO19 GPXID3
NUM_LED# 36 GPI 115 SLP_CHG# T44 PAD
45 NUM_LED# NUMLED#/GPIO1A GPXID4
116 SUSP#
GPXID5 SUSP# 46,52,56
117 PBTN_OUT#
GPXID6 PBTN_OUT# 30
118 EC_PME#_R 1 2
GPXID7 EC_PME# 32
Close to EC CRY1 122 @ R345 0_0402_5%
XCLK1
30 SUS_CLK 1 2 CRY2 123 XCLK0 V18R 124 +EC_V18R 1 2 +3VL
R333 0_0402_5% @ R542 10K_0402_5%
AGND
GND
GND
GND
GND
GND

C448
4.7U_0805_10V4Z
KB926QFD3_LQFP128_14X14
11
24
35
94
113

69

R389
CRY1 1 2CRY2 +3VL

10M_0402_5%
@
2

R435
1 100K_0402_5%
1

C449 C450 EC_REV_SEL H L

1
18P_0402_50V8J

Y4 EC_REV_SEL
15P_0402_50V8J
OSC

OSC

2
2

R436 EC ver. KB926D3 KB926E0

100K_0402_5%
NC

NC

A A
@
2

1 2 VTTP_EN
R337 100K_0402_5%

1 2 E51_TXD 32.768KHZ_12.5PF_Q13MC14610002
R342 100K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ENE-KB926 RevD2
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Monday, April 19, 2010 Sheet 43 of 57
5 4 3 2 1
 +3VL

1
C451 U22
8 VCC VSS 4
0.1U_0402_16V4Z +3VALW
2
3 W U21
7 APX9132ATI-TRL_SOT23-3
HOLD
SPI_CS# 1 2 3

GND
43 SPI_CS# S VDD VOUT LID_SW# 43
SPI_CLK 6
43 SPI_CLK C
1 1

1
EC_SO_SPI_SI 5 2 EC_SI_SPI_SO
43 EC_SO_SPI_SI D Q EC_SI_SPI_SO 43
C453 C452
MX25L2005CMI-12G SO8 0.1U_0402_16V4Z 10P_0402_50V8J
2 2

SPI_CLK 1 R394 2 1 2
10_0402_5% C454 10P_0402_50V8J
@ @

KSO2 1 2
C404 100P_0402_50V8J
KSO1 1 2
C405 100P_0402_50V8J
KSO0 1 2

KSO4
C406
1
100P_0402_50V8J
2
Kill SWITCH
C407 100P_0402_50V8J
KSO3 1 2
C408 100P_0402_50V8J
KSO5 1 2
KSI[0..7] C409 100P_0402_50V8J
KSI[0..7] 43
KSO14 1 2
KSO[0..15] C410 100P_0402_50V8J
KSO[0..15] 43
KSO6 1 2
C411 100P_0402_50V8J
KSO7 1 2 +3VALW
JP19 C412 100P_0402_50V8J
KSI1 1 KSO13 1 2
KSI7 1 C413 100P_0402_50V8J
2 2
KSI6 3 KSO8 1 2
3

2
KSO9 4 C415 100P_0402_50V8J
KSI4 4 KSO9 D24 +3VALW
5 5 1 2
KSI5 6 C416 100P_0402_50V8J DAN217_SC59
6

2
KSO0 7 KSO10 1 2 @
KSI2 7 C417 100P_0402_50V8J R580
8 8
KSI3 9 KSO11 1 2

1
KSO5 9 C418 100P_0402_50V8J 100K_0402_5%
10 10
KSO1 11 KSO12 1 2

1
KSI0 11 C419 100P_0402_50V8J KILL_SW#
12 12 KILL_SW# 43
KSO2 13 KSO15 1 2
KSO4 13 C420 100P_0402_50V8J
14 14
KSO7 15 KSI7 1 2
KSO8 15 C421 100P_0402_50V8J
16 16
KSO6 17 KSI2 1 2
17

3
KSO3 18 C422 100P_0402_50V8J
KSO12 18 KSI3
19 1 2

3
KSO13 19 C423 100P_0402_50V8J
20 20
KSO14 21 KSI4 1 2
KSO11 21 C424 100P_0402_50V8J
22 22 SW5
KSO10 23 KSI0 1 2
KSO15 23 C425 100P_0402_50V8J 1BS003-1211L_3P
24 24
25 KSI5 1 2
25 C427 100P_0402_50V8J
26 26 KSI6 1 2
C429 100P_0402_50V8J
27 KSI1 1 2
GND1 C431 100P_0402_50V8J
28 GND2 Security Classification Compal Secret Data
Issued Date 200910/9 Deciphered Date 2010/01/23 Title
ACES_88514-2601 CONN@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SPI ROM/LID/Debug/KB/G-Sen
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Wednesday, April 14, 2010 Sheet 44 of 57
 5 4 3 2 1

+3VL
Power Button Touchpad Connector

2
debug phase using R395
SW1
100K_0402_5% SW_L 1 3
51_ON# 47
SW2 D19 @

1
1 3 ON/OFFBTN# 2 2 4
ON/OFFBTN# 43

6
BTM side 1
2 4 1 Q7A <BOM Structure> 3 SMT1-05_4P

6
5
C458 2N7002DW-T/R7_SOT363-6
SMT1-05-A_4P 0.1U_0402_25V6 2 PACDN042Y3R_SOT23-3
6
5
43,50 EC_ON

2
2 JTP

1
SW3 R396 8
D @ GND D
1 3 10K_0402_5% 7
GND
6
+5VS 6
TOP side 2 4 For EMI request 43 TP_CLK 5

1
5
43 TP_DATA 4
SMT1-05-A_4P SW_L 4
3
6
5

@ SW_R 3 SW4
2
+5VALW 2 SW_R
1 1 3
1
+5VS ACES_85201-0605N 2 4
JPOWER CONN@
1 SMT1-05_4P

6
5
PWR_ON_LED# 1
2
38,43 PWR_ON_LED# ON/OFFBTN# 2
3
3
4
CAPS_LED# 4
43 CAPS_LED# 5
NUM_LED# 5 D83
6
43 NUM_LED# 6 ON/OFFBTN#
7 2
7
1 8 1
C471 8 PWR_ON_LED#
9 3
GND
10
0.1U_0402_25V6 GND PJSOT05C_SOT23-3
2 ACES_85201-08051 <BOM Structure>
CONN@

For EMI request Screw Hole

C C

H1 H2 H3 H4 H5 H6 H25 H26
H_4P5 H_3P1X3P6N H_3P1N H_4P5 H_4P5 H_4P5 H_4P5 H_4P5

1
H12 H16 H17 H18
H_3P0 H_3P0 H_3P0

1
H_4P0X5P0N

H19 H20 H21 H23

H_3P0 H_3P0 H_3P0 H_3P0

1
H24
H_1P1 H22
H_3P0

1
B B

PCB Fedical Mark PAD

FD1 FD2 FD3 FD4

@ @ @ @

1
ISPD

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR/Cap./TP/LED/LP/LS/Screw
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Wednesday, April 14, 2010 Sheet 45 of 57
5 4 3 2 1
 A B C D E

+3VALW +3VS +5VALW +5VS +1.5V +1.5VS

4.7U_0805_10V4Z
4.7U_0805_10V4Z +5VS
1 1 1 1 1 1
Q29 C459 C460 4.7U_0805_10V4Z Q30 C461 C462 Q31 C463 C464
8 D S 1 8 D S 1 8 D S 1

2
7 2 7 2 1U_0402_6.3V4Z 7 2
D S 2 2 R406 D S 2 2 R407 D S 2 2 R408

0.1U_0402_16V4Z

0.1U_0402_16V4Z
6 D S 3 6 D S 3 6 D S 3
5 4 470_0603_5% 5 4 470_0603_5% 2 2 5 4 470_0603_5%
D G 1U_0402_6.3V4Z D G C822 C821 D G 1U_0402_6.3V4Z
1 1
SI4800BDY_SO8 1 R409 2 +VSB SI4800BDY_SO8 1 R410 2 +VSB SI4800BDY_SO8 1 R411 2 +VSB

3 1

3 1

3 1
220K_0402_5% R413 220K_0402_5% @ @ 220K_0402_5%
0.022U_0402_25V7K

0.01U_0402_25V7K
4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z
1 1 1 1 1 1

6
C466 R412 1 1

0.1U_0402_25V6
C470
C465 Q10A C467 C468 Q11A C469 R414 Q12A

820K_0402_5%
Q10B Q11B 820K_0402_5% Q12B
2 2 2 2 2 2
820K_0402_5%
2 SUSP 5 2 SUSP 5 2 SUSP 5
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6
2

2
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6

4
+3VL VL

+3VALW
R422 R441

100K_0402_5%
2
10K_0402_5%
+0.75VS

1
@
+1.5V +VRAM_1.5VS R425

2
100K_0402_5%
R421 R421

1
470_0805_5% 47_0805_5%

2
1 1 @
0.75VR_EN# 53
Q43

1
3
8 1 C478 C475 SUSP
D S 9,53 SUSP
2

7 2 1U_0402_6.3V4Z 4.7U_0805_10V4Z
D S 2 OPT@ 2 OPT@ R429 Q44B
6 D S 3

1
2 470_0603_5% 0.75VR_EN 2N7002DW-T/R7_SOT363-6 D Q189 2
5 D G 4 5,51 VTTPWROK 1 2 5

1
D
OPT@ R158 100K_0402_5% Q6 2 SUSP
FDS6676AS_SO8 1 R431 2 +VSB 2 G
43,52,56 SUSP#
3 1

4
6
1 OPT@ 220K_0402_5% Q44A G 2N7002_SOT23-3
4.7U_0805_10V4Z

1 S

3
1

6
0.1U_0402_25V6

OPT@ 2N7002DW-T/R7_SOT363-6 2N7002_SOT23-3 S

3
C473 C481 R430 Q13A
OPT@ OPT@ 820K_0402_5% OPT@ Q13B SUSP 2
2 2 OPT@ 2 VGA_PWROK# 5 2N7002DW-T/R7_SOT363-6
OPT@
2

1
2N7002DW-T/R7_SOT363-6
1

+5VALW

R146 1 2 100K_0402_5%
OPT@
1

D
2 Q188
28,32,56 VGA_PWROK
G 2N7002_SOT23-3
S OPT@
3

+3VS
+3VALW

2
2
R433 C491
100K_0402_5% 0.1U_0402_16V7K
OPT@ OPT@

2
1

3
S
3 R426 Q54 PJ32 3

2
G
DGPU_PWR_EN# 1 2 2 JUMP_43X79
+VTT
+5VALW @ +3VS_DGPU

1
47K_0402_5% 2 AO3413_SOT23 D

1
6
+1.05VS_DGPU OPT@ OPT@

1
Q206A C492
OPT@ @ 0.01U_0402_25V7K
2

2 1
2 13,33,56 DGPU_PWR_EN 1
R460 R434 C493 2N7002DW-T/R7_SOT363-6 1
470_0603_5% 47K_0402_5% 0.1U_0402_16V7K C684

1
OPT@ OPT@ @ C683 1U_0402_6.3V4Z
2

1 4.7U_0805_10V4Z 2 OPT@
1

D PJ33 @ 2
2

2 Q56 JUMP_43X79
G @
1

D D
1

Q57 +1.05VS_DGPU
0.01U_0402_25V7K

2 S
3

2DGPU_PWR_EN# 2 Q36 AO3416_SOT23-3

1

G G C494
S S OPT@ +3VS_DGPU +VGA_CORE
3

OPT@ 2N7002_SOT23-3 1
1
2N7002_SOT23-3 1
2

2
C686
C685 1U_0402_6.3V4Z R458 R459
4.7U_0805_10V4Z 2 OPT@ 470_0603_5% 470_0603_5%
@ 2 OPT@ OPT@
3 1

1
1
Change to N MOS at DVT and add R434, Q36 Q206B Q55 D
2N7002DW-T/R7_SOT363-6 5 DGPU_PWR_EN# 2
4 OPT@ G 4
2N7002_SOT23-3 S
4

3
OPT@

Security Classification Compal Secret Data

Issued Date 200910/9 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC-DC INTERFACE
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL60/61 LA-6321P M/B
Date: Monday, April 19, 2010 Sheet 46 of 57
A B C D E
 A B C D

DCIN jack P/N:DC301009U00,

need doble confirm P/N with ME VIN
PL1
SMB3025500YA_2P
DC_IN_S1 1 2

1
PJPDC1 1

1000P_0402_50V7K

1000P_0402_50V7K

680P_0402_50V7K
680P_0402_50V7K

100P_0402_50V8J

100P_0402_50V8J
4 4

1
PC5
3 3

1
PC1

PC2

PC3

PC4

PC6
2 2
1

2
1
@

2
@ SINGA_4TRJWT-R2513 @

Modify the VIN_DET, Pre-charge, RTC_charge

VIN
RTC Battery

2
2
PD2 2

RLS4148_LL34-2 - PBJ1 + PR21

560_0603_5%
PR22
560_0603_5%

1
2 1 1 2 1 2 +RTCBATT
BATT+ 2 1

1
@
PD3 PR9 PR10
RLS4148_LL34-2 PQ1 68_1206_5% 68_1206_5% MAXEL_ML1220T10
TP0610K-T1-E3_SOT23-3 change RTC charge to
@
prevent can't power on
@

2
when overdischarge issue
N1 Astro_03_15
3 1
@ @
VS SP093MX0000
1

1
PC10
PR13 PC9 0.1U_0603_25V7K
100K_0402_1% 0.22U_0603_25V7K
2

2
2

+3VL
1 2 @ @
45 51_ON#
PR15 @
22K_0402_1%
@
PJ666 3.3V
@ +CHGRTC 2 2 1 1

unmount for cut in new @ JUMP_43X39

EC code Astro_0315 Modify

3 3

PJ11
PJ1 PJ2 PJ3 2 1
2 1
+3VALWP 2 2 1 1 +3VALW 2 2 1 1 +1.8VSP 2 2 1 1 +1.8VS
@ JUMP_43X118
@ JUMP_43X118 @ JUMP_43X118 @ JUMP_43X79
(5A,200mils ,Via NO.= 10) (2A,80mils ,Via NO.= 4) PJ13
PJ4 +VTTP 2 1 +VTT
2 1
+1.5VP 2 2 1 1 +1.5V
PJ5 @ JUMP_43X118
+5VALWP 2 2 1 1 +5VALW @ JUMP_43X118 PJ12 (18A,720mils ,Via NO.=36)
2 2 1 1
@ JUMP_43X118 (15A,600mils ,Via NO.= 30)
(5A,200mils ,Via NO.= 10) @ JUMP_43X118

PJ7 PJ9
PJ16 PJ14
+VSBP 2 2 1 1 +VSB +0.75VSP 2 2 1 1 +0.75VS +VGA_COREP 2 2 1 1 +VGA_CORE +3VLP 2 2 1 1 +3VL
@ JUMP_43X39 @ JUMP_43X79 @ JUMP_43X118 @ JUMP_43X39
(1.5A,60mils ,Via NO.= 4) (100mA,40mils ,Via NO.= 2)
(120mA,40mils ,Via NO.= 1) (26A,1040mils ,Via NO.=52)

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN / DETECTOR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NCL61 LA-6321P M/B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 14, 2010 Sheet 47 of 59
A B C D
 A B C D

Rset = 3 * Rtmh
Rhyst = (Rset* Rtml) / (3*Rtml - Rset)
Rtmh at 92C = 7.3092K, Rtml at 70C =15.423K
Rset = 3 * 7.3092K = 21.9276K ==> 22K
Rhyst = (21.9276K * 15.423K) / (3 * 15.423K - 21.9276K) = 13.98K ==> 14K
need confirm: ME give us battery change tempreture setting Astro1231
connector P/N is DC040001V00 PL30
changed on 1231 Astro HCB2012KF-121T50_0805
1 2
1 1
VMB
PL2
PH1 under CPU botten side :
PJP1 @ HCB2012KF-121T50_0805
1 BATT_S1 1 2
CPU thermal protection at 92 degree C
1 BATT+
PR29 @
2 2
3 BATT_P3 1 2
Recovery at 70 degree C
3 +3VLP
4 BATT_P4 1 2
4 +3VLP

1
5 5 100K_0402_1%
PH2 near main Battery CONN : Reserve

1
6 PC16 PC17
6 100K_0402_1% @ PR28 @ PC18 1000P_0402_50V7K 0.01U_0402_25V7K
7 BAT. thermal protection at 90 degree C

2
7

1
8 PR45 1K_0402_1% 0.1U_0402_25V6K

2
8 PR30
9 9
10 1K_0402_1%
Recovery at 53 degree C

2
G1
G2 11

2
SUYIN_200275MR009G180ZR
VL HW add VGATE connect to EC
so VL not charge to Alway
Change to small size
1

PD6 PD7

2
2

1
1 PR31
3 PC19 22K_0402_1%
0.1U_0603_25V7K

2
@ PJSOT24CW_SOT323-3 @ PJSOT24CW_SOT323-3 PR32 PR33
2

1
2 1 10K_0402_1%
+3VLP

2
6.49K_0402_1%
PR34

1
1

14K_0402_1%
PR35 PU3
2
1K_0402_1% 1 8 2

1
VCC TMSNS1

1
2 7
2

GND RHYST1
2

PR36 PR37
BATT_TEMPA 43 3 OT1 TMSNS2 6 P/N:SD034140280 PH1
100_0402_1% 100_0402_1% 100K_0402_1%_NCP15WF104F03RC

1
4 5

2
OT2 RHYST2 @ PR38
1

50 VS_ON G718TM1U_SOT23-8 47K_0402_1%

EC_SMB_DA1 43

2
EC_SMB_CK1 43

1
PH2
@ 100K_0402_1%_NCP15WF104F03RC

2
PJ10 Add
2 2 1 1
HW SUSP was Pull high by +3VL @ JUMP_43X39

@ PQ4
TP0610K-T1-E3_SOT23-3

B+ 3 1 +VSBP
3 3
100K_0402_1%

0.22U_0603_25V7K

0.1U_0603_25V7K
1

1
PR39

PC20

PC21
2

@ @ @
2

VL @ PR40
22K_0402_1%
1 2
2

@ PR41
100K_0402_1%

PR42 @
1

0_0402_5% D
1 2 2 PQ5 @
50 POK
G SSM3K7002FU_SC70-3 Reserve
.1U_0402_16V7K

S
3
1

PC22
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NCL61 LA-6321P M/B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 14, 2010 Sheet 48 of 59
A B C D
 A B C D

B+
PQ6
AO4407A_SO8
1 8
2 7

PQ7 P2 PQ8 P3 PR43

B+ CHG_B+
3 6
5
AO4407A_SO8 SI4483ADY_SO8 0.02_1206_1% PJ17
VIN 8 1 1 8 1 4 2 1

4
2 1
7 2 2 7
CSIN

0.1U_0402_25V6K
@ JUMP_43X118

4.7U_0805_25V6-K
6 3 3 6 2 3

change 4.7uF*2 to 10uF*1

5 5
CSIP

4
1 1

Change SE000009R80 to SE000006900

10U_1206_25V6M
VIN

1
Modify

PC25
5600P_0402_25V7K
PQ9 PR44 PR223

2
0.1U_0603_25V7K
DTA144EUA_SC70-3 200K_0402_1% 191K_0402_1%

2
PC23
6251VDD 1 2 ACSETIN

2
1

PC26

PC24
PR48

2.2U_0603_6.3V6K
2

2
PC28

PC29
47K_0402_1%

2
PD13
PR46

RB751V-40_SOD323-2
1 2

2
VIN

14.3K_0402_1%
47K_0402_1% PC214 @

2
1000P_0402_25V8J
2

PR228
PR50 PD9
1

1
1

PD10 PR229 10K_0402_1% 1 2 ACOFF

1SS355_SOD323-2 1 2

2
1 2 PD14 @ 1SS355_SOD323-2

1
10_1206_5% GLZ27D_LL34-2 PR52
2 PR51 ACSETIN 1 2 200K_0402_1%

1
PQ12 10K_0402_1% 1 2 VIN
DTC115EUA_SC70-3 2 1 PU4 PC63

DCIN
43 FSTCHG 1U_0603_25V6

100K_0402_1%
1 2 1 24 1 2 PQ13 PD11
3

VDD DCIN
1

1
DTC115EUA_SC70-3 2 1 2

PR54
PC30
PR53 .1U_0402_16V7K 2 23 ACPRN 1SS355_SOD323-2
ACSET ACPRN
1

D 150K_0402_1% PR55

change to AO7408L
2 PQ14 20_0603_5%
2

3
PQ16

1
G SSM3K7002FU_SC70-3 6251_EN CSON D
3 EN CSON 22 1 2

1
S @ PC34 PC32 PC33 2 PACIN
3

680P_0402_50V7K 0.047U_0603_16V7K AON7408L_DFN8-5 0.1U_0603_25V7K G

CSON
SSM3K7002FU_SC70-3

1 2 4 21 1 2 S PQ15

3
CELLS CSOP PR56 SSM3K7002FU_SC70-3
2
PC35 6800P_0402_25V7K 20_0603_5% change to footfrint 2
1 2 5 ICOMP CSIN 20 2 1 4 TOKO_D104C-919AS_2P
1

2
D PR57
for charger
PQ17

2 PC37 PR58 6.81K_0402_1% PC36 20_0603_5%

G 1 2 1 2 6 19 0.1U_0603_25V7K1 2

1
VCOMP CSIP PL3 PR61
S
3

3
2
1
0.01U_0402_25V7K 1 2 PR60 47K_0402_1% PR59 10U_LF919AS-100M-P3_5.3A_20% 0.02_1206_1% BATT+
PR62 1 2 7 18 LX_CHG 2.2_0603_1% 1 2 CHG 1 4
ICM PHASE

4.7_1206_5%
22K_0402_5% @ PC38 100P_0402_50V8J

5
6
7
8

PR63
PACIN 1 2 1 2 2 3

10U_1206_25V6M

10U_1206_25V6M
PC39 6251VREF 8 17 DH_CHG PQ18
PR64 .1U_0402_16V7K VREF UGATE PR65 PC40 @
150K_0402_1% 43 ADP_I 0_0603_5% 0.1U_0603_25V7K
Remove AC_ON

1
PC41

PC43
2 1 9 16 BST_CHG 1 2 BST_CHGA 2 1
43 IREF CHLIM BOOT
1

1
PR66 4

680P_0603_50V8J
12.4K_0402_1% PD12
0.01U_0402_25V7K

2
PC42
6251VREF 1 2 6251aclim 10 15 6251VDDP RB751V-40TE17_SOD323-2
ACLIM VDDP
1

2
1

1
PC44

ACOFF 2 PQ19 PR67 Rtop 1 2 6251VDD AO4468L_SO8 @

43 ACOFF

3
2
1
DTC115EUA_SC70-3 140K_0402_1% PR68 11 14 DL_CHG
VADJ LGATE

2
20K_0402_1% PR69
2

4.7_0603_5%
2

12 13 PC45
3

1
GND PGND 4.7U_0805_6.3V6K
change to AO4468L
ISL6251AHAZ-T_QSOP24

Use old BIOS to charge as PR70

18.2K_0402_1%
below setting but need EC 1 2
modify the CP point(EC<-->Adp_I) 43 CHGVADJ
1

VIN
Astro_2010_01_19 PR71
3 3

31.6K_0402_1%
2

1
6251VDD
PR72
309K_0402_1% PR224
10K_0402_1%

1
PR73 1 2
2

ACIN 30,43
10K_0402_1% PR225
1 2 47K_0402_1% PR226
ADP_V 43 10K_0402_1%
PACIN

1 2
1

CP= 85%*Iada;
1

PR74 C

1
Iada=0~4.737A(90W);CP=4.03A;where Racdet=0.020ohm,where Rtop=12.4K 47K_0402_1% PC46 ACPRN
2 PQ36
.1U_0402_16V7K B PR227
90W for Dis:Rtop:SD00000AJ80
2

E 20K_0402_1%
Add
2

3
Iada=0~3.421A(65W);CP=2.91A;where Racdet=0.020ohm,where Rtop=226K MMBT3904W_SOT323-3
65W for UMA:Rtop:SD034226380

2
Astro2010_01_15 need confirm P/N

CP mode
Vaclim=VREF*(Rbot//Rinternal/(Rtop//Rinternal+Rbot//Rinternal))
when 90W Vaclim=2.39*(20K//152K/(20K//152K+12.4K//152K))=1.44966V
when 65W Vaclim=2.39*(20K//152K/(20K//152K+226K//152K))=0.38914V
Iinput=(1/Racdet)*((0.05*Vaclim/VREF+0.05))
If ACSET>=1.26V, ACPRN is Low level.
when 90W,Iinput=(1/0.02)*(0.05*1.44966/2.39+0.05)=4.02A If ACSET<1.26V, ACPRN is High level.
4 when 65W,Iinput=(1/0.02)*(0.05*0.38914/2.39+0.05)=2.92A ACSET is Input Pin 4

ACPRN is Open-drain

CC=0.25A~3A CHGVADJ=(Vcell-4)/0.10627
IREF=1.016*Icharge Vcell CHGVADJ
IREF=0.254V~3.048V 4V 0V
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title
VCHLIM need over 95mV 4.2V 1.882V CHARGER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NCL61 LA-6321P M/B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 19, 2010 Sheet 49 of 59
A B C D
 5 4 3 2 1

2VREF_51125

1U_0603_10V6K
D D

1
PC47

2
PR75 PR76
13K_0402_1% 30K_0402_1%
1 2 1 2

PR77 PR78
B++
20K_0402_1% 19.1K_0402_1%
change to no connection 1 2 1 2 B++
for IC define(Astro_2010_01_19)
@ PJ18

ENTRIP2

ENTRIP1
B+ 2 2 1 1 +3VLP
PR79 PR80
4.7U_0805_25V6-K

JUMP_43X118 110K_0402_1% 124K_0402_1%

1 2 1 2
1
PC49

10U_1206_25V6M
1

PC48
4.7U_0805_10V6K
2

1
PU5

5
PC50

ENTRIP2

FB2

TONSEL

FB1

ENTRIP1
REF
5

1
C 25 C
P PAD PQ21

2
PQ20 AON7408L_DFN8-5
AON7408L_DFN8-5 7 24 POK 48 4
VO2 VO1
4
8 23 PC52
PR81 VREG3 PGOOD PR82 .1U_0402_16V7K
1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2

3
2
1
0_0603_5% BOOT2 BOOT1 0_0603_5%
1
2
3

PL4 PC51 UG_3V 10 21 UG_5V PL5

4.7UH_PCMC063T-4R7MN_5.5A_20% .1U_0402_16V7K UGATE2 UGATE1 4.7UH_PCMC063T-4R7MN_5.5A_20% +5VALWP
1 2 LX_3V 11 20 LX_5V 1 2
+3VALWP PHASE2 PHASE1
1

1
LG_3V LG_5V
4.7_1206_5%

4.7_1206_5%
12 LGATE2 LGATE1 19
PR83

PR84
SKIPSEL
PQ23

VREG5
@ @
220U_6.3V_M

220U_6.3V_M
1 1

GND

VIN
EN0 RT8205EGQW_WQFN24_4X4 RJK03D0DNS_DFN8-5

NC
EN
2

2
+ +
PC53

PC54
4 4
PR85

13

14

15

16

17

18
1

1
499K_0402_1%
680P_0603_50V8J

680P_0603_50V8J
2 2
PC55

PC56
PQ22 1 2 RT8205 Pin25 cannot connect to GND
AON7406L_DFN8-5 B+
2

1
2
3

3
2
1

2
1
@ @

100K_0402_5%
1
1U_0402_6.3V6K

PR86
1 2
VL
PC57

PC58
@ PR87

4.7U_0805_10V6K
2
B
0_0402_5% change to footfrint SI7326DN-T1-E3_PAK1212-8 B
need mount SB00000MU00

2
ENTRIP1 ENTRIP2 B++
Rdson=12.6mohm(Type);17.6mohm(Max)

0.1U_0603_25V7K
2
PC59
D D
1

2VREF_51125
PQ24 2 2 PQ25
SSM3K7002FU_SC70-3 G G SSM3K7002FU_SC70-3
S S
3

PQ20,PQ21,and PQ22 change to AO7408L

and AO7406L;Rdson=19mohm(Type):
23.5mohm(Max)
PL4,PL5 change to SH000006J80
2 1
VL
PR88
change on 0316 Astro 100K_0402_1%
PR105
10K_0402_1%
1 2
Reserve the EC_ON control singnal,
43,45 EC_ON
need confirm with EC
D
1

48 VS_ON
VS 1 2 2 PQ26
A
G SSM3K7002FU_SC70-3 A
@ PR89 S
0.01U_0402_16V7K

3
1

100K_0402_1%
100K_0402_5%

PC60
PR90

@
2

Security Classification Compal Secret Data Compal Electronics, Inc.

2

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3VALWP/5VALWP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NCL61 LA-6321P M/B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 19, 2010 Sheet 50 of 59
5 4 3 2 1
 A B C D

1 1

change to SM01000C000
B+ PL6
HCB2012KF-121T50_0805
1 2+VTTP_B+
+5VS

change 4.7uF*2 to 10uF*1

4.7U_0805_25V6-K

VTTPWROK 5,46

10U_1206_25V6M
1

1
PR91
change to 0ohm
PC62

VTTPWROK_CPU 5
PC61

3.4K_0402_1% PR93 0_0603_5%

2

1 2 1 2 1 2

BST_+VTTP
PR92 0_0402_5% PC64

DH_+VTTP
LX_+VTTP
0.1U_0603_25V7K

change to AO4406L
1 2 1 2
+5VALW
PR94 2.1K_0402_1% PR95 4.53K_0402_1%

DH_+VTTP

5
6
7
8
PR96
0_0402_5% PR97 PQ27

16

15
8

1
PU6 4.7_0603_5%
1 2

UG
GND

PGOOD

PHASE

BOOT
+VTTP_VCC

2
4
3 VIN PVCC 14 1 2 PC65
+VTTP_VCC 2.2U_0603_6.3V6K
2 AO4406AL_SO8 2

3
2
1
4 13 DL_+VTTP PL7
VCC LG 0.36UH_PCMC104T-R36MN1R05_30A_20%
1

PC66 1 2
2.2U_0603_6.3V6K
+VTTP
12
2

PGND

4.7_1206_5%
1

1
+

PR99
PC67
1 2 5 11 SE_+VTTP 1 2 change to SH00000HK00 330U_D2_2V_Y
43 VTTP_EN EN ISEN PR98 PQ28
PR100 DCR=1.0ohm+-5%
COMP

FSET
10.5K_0402_1%
0_0402_5%

2
VO
FB
4

680P_0603_50V8J
.1U_0402_16V7K

1
ISL6268CAZ-T_SSOP16~N AON6718L_DFN8-5
6

10
1

PC69
SA00001HT80 need

3
2
1

2
PC68

+VTTP
FB_+VTTP
2

double confirm P/N

@ Astro_0315 Material Note:
0.01U_0402_16V7K
1

330uF/ 9mohm, number are 3,

27.4K_0402_1%

1
PR101

49.9K_0402_1%

change to AON6718L power x1, HW x2

PR102

PC70

Rdson=4.1mohm(type);5mohm(Max)
2
1

2200P_0402_50V7K
2

PC71
22P_0402_50V8J
2

change APW7138 to ISL6268

PC72

3 3

for transient issue(output ripple change to SD034442280 on 0316 Astro

2

worse). Need mount compensation F=302KHZ

RC parts(need confirm these
component value) Astro_0315
1 2 1 2+VTTP
PR103 PR104
change PC72 material for 2.21K_0402_1% 10_0402_5%
1

PM request Astro_0317

PR106 1 2
2.94K_0402_1% PR108 VTT_SENSE 8
0_0402_5%
2

change

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+VTTP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NCL61 LA-6321P M/B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 19, 2010 Sheet 51 of 59
A B C D
 A B C D

1 1

PJ20
PU7 PL8 <Vo=1.8V> VFB=0.6V

4
1UH_FMJ-0630T-1R0 HF_11A_20%
2 1 10 2 LX_SY8033B 1 2
Vo=VFB*(1+PR114/PR115)=0.6*(1+40.2K/20K)=1.806V
+5VALW

PG
2 1 PVIN LX +1.8VSP
Ipeak=2.64A, Imax=1.848A

22P_0402_50V8J
JUMP_43X79 9 3
PVIN LX

1
4.7_1206_5%
1

1
PC76
PC75 8 SVIN

PR115
22U_0805_6.3VAM PR116
6 20K_0402_1%
2

2
FB

22U_0805_6.3VAM

22U_0805_6.3VAM
2
5 @ 2

2
EN

1
NC

NC
TP

PC79

PC80
FB_SY8033B
43,46,56 SUSP#

11

2
1 2 EN_SY8033B

1
1

680P_0603_50V7K
PR117 0_0402_5%
0.1U_0402_10V7K
2

PC77

PC78
SY8033BDBC_DFN10_3X3 PR114
1

PR118 10K_0402_1%

2
1M_0402_5%

2
@
2

@
1

change from 47K to 1M

change From MP2121 to SY8033
Astro2010_01_04

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.05VSP / +1.8VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NCL61 LA-6321P M/B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 19, 2010 Sheet 52 of 59
A B C D
 5 4 3 2 1

PJ21
1.5V_B+ 2 1 B+
2 1
@ JUMP_43X118

10U_1206_25V6M
1

PC83
D D

2
PQ31
AON7408L_DFN8-5

PR119
255K_0402_1% 4
1 2 Rdson=12mohm(type);15mohm(Max)
PR120
0_0402_5%
1 2 BST_1.5V 1 2
43 SYSON

3
2
1
PR121

1
2.2_0603_1% PC86 PL9

15

14
1
@PC85
@ PC85 PU8 0.1U_0603_25V7K 1UH_PCMC063T-1R0MN_11A_20%
.1U_0402_16V7K 1 2 1 2

EN/DEM

NC

BOOT
+1.5VP

2
DH_1.5V

4.7_1206_5%
2 TON UGATE 13

1
PR123 LX_1.5V

PR122
3 VOUT PHASE 12 1

5
6
7
8
316_0402_1%
1 2 4 11 1 2 +5VALW PQ32 + PC87
+5VALW VDD CS PR124 330U_2.5V_M

2
5 10 15.4K_0402_1%
FB VDDP 2
1

1
6 9 DL_1.5V 4

680P_0603_50V8J
PGOOD LGATE

PGND

PC89
PC88

GND
1U_0603_10V6K
2

2
1
C C
RT8209BGQW_WQFN14_3P5X3P5 PC90 FDS6690AS-G_SO8

3
2
1
4.7U_0805_10V6K

2
N11M
PQ32 PL9 PC87 PR124
PR125 UMA: SB00000E310;SH000006I80
10.2K_0402_1% SF000002Y00;SD034150280
1 2 N11M: SB000004J10;SH000006O00
SF000002M00;SD034154280
N11P: SB00000ID00;SH000006O00
SF000002M00;SD034100280
10K_0402_1%
1
PR126

+1.5V
1

PJ22
1

@ JUMP_43X79
2

B B
2

PU9
1 VIN VCNTL 6 +5VALW
4.7U_0805_6.3V6K

2 GND NC 5
1

3 VREF NC 7

1
PC91

1K_0402_1%
PR127

PR128 4 8 PC92
2

47k_0402_5% VOUT NC 1U_0603_10V6K

2
1 2 9
9,46 SUSP
2

TP
G2992F1U_SO8

@ PR129
0.1U_0402_10V7K

D D +0.75VSP
1

0_0402_5%
1K_0402_1%
PQ33

PQ666

PC94

SUSP
PR130

1 2 2 2
SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

46 0.75VR_EN# G G
1

S S
3

3
1

@ PC95
2

@ PC93 10U_0805_6.3V6M
2

1U_0402_16V7K
2

A A
Add PQ668(HW request)
Astro_0316

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/23 Title
2009/01/23 Deciphered Date
+1.5VP/0.75VSP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom NCL61 LA-6321P M/B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 19, 2010 Sheet 53 of 59
5 4 3 2 1
 8 7 6 5 4 3 2 1

CPU_VID0 2 1 PR131 1K_0402_1% @ CPU_VID0 2 1 PR132 1K_0402_1%

CPU_VID1 2 1 PR133 1K_0402_1% @ CPU_VID1 2 1 PR134 1K_0402_1%

CPU_VID2 2 1 PR135 1K_0402_1% CPU_VID2 2 1 @ PR136 1K_0402_1%

CPU_VID3 2 1@ PR137 1K_0402_1% CPU_VID3 2 1 PR138 1K_0402_1%

H 8 CPU_VID0 H
CPU_VID4 2 1@ PR140 1K_0402_1% CPU_VID4 2 1 PR141 1K_0402_1% +CPU_B+
PL10 B+
8 CPU_VID1
CPU_VID5 2 1 PR144 1K_0402_1% CPU_VID5 2 1 @ PR143 1K_0402_1% HCB2012KF-121T50_0805
8 CPU_VID2 1 2
CPU_VID6 2 1@ PR147 1K_0402_1% CPU_VID6 2 1 PR146 1K_0402_1% PL15
HCB2012KF-121T50_0805
8 CPU_VID3
H_DPRSLPVR 2 1 PR149 1K_0402_1% H_DPRSLPVR 2 1 @ PR150 1K_0402_1% 1 2 1 1

10U_1206_25V6M

10U_1206_25V6M
2200P_0402_50V7K
470P_0603_50V8J

0.1U_0603_25V7K

100U_25V_M_R0.44

100U_25V_M_R0.44
8 CPU_VID4 + +
H_PSI# PR152 1K_0402_1%

PC102

PC103
2 1

change to AO4406L

1
0010010---->1.275V

PC97

PC98

@ PC99
PC100
8 CPU_VID5

PC101
+VTT 2 2

2
8 CPU_VID6

5
6
7
8
PR155 PC104 PQ34
0_0603_5% 0.22U_0603_25V7K
PR156 0_0402_5% BOOT2 1 2 BOOT2_2 1 2 @
43 VR_ON 1 2
UGATE2 4
G PR157 0_0402_5% G

8 H_DPRSLPVR 1 2

AO4406AL_SO8

3
2
1
25 CLK_ENABLE#

+3VS PR162 0.36UH_PCMC104T-R36MN1R05_30A_20%

1.91K_0402_1%
PL11
1 2 CLK_ENABLE#
PHASE2 4 1 +CPU_CORE
2

PR163 3 2 V2N

PR158
1.91K_0402_1%

4.7_1206_5%

10K_0402_5%
1

1
PR165 PQ35

3.65K_0805_1%
0_0402_5% PR161
30 VGATE
1

1_0402_5%

PR159

PR160
1 2

LGATE2 4

2
@ PR166 1K_0402_1%
F F
+VTT 1 2
RJK0392DPA-00-J53_WPAK8-5
PR167 0_0402_5% VSUM+

3
2
1

1
1 2

680P_0603_50V8J
8 H_PSI#
PR168 VSUM-

PC105
1 2

2
147K_0402_1%
PC106 +5VALW
1U_0603_10V6K ISEN2
40
39
38
37
36
35
34
33
32
31

1 2
CLK_EN#

VID6
VID5
VID4
VID3
VID2
VID1
VID0
DPRSLPVR
VR_ON

2
30 PR169
BOOT2
29 0_0402_5%
UGATE2
1 28
PGOOD PHASE2
2 27

1
PSI# VSSP2
3 26
RBIAS LGATE2
4 25
VR_TT# VCCP
E 5 24 E
NTC PWM3
6
VW LGATE1
23 change to footfrint SI7840DP-T1-E3_SO8
7 22
COMP VSSP1
8
FB PHASE1
21 need mount SB00000IG00
9
ISEN3 Rdson=3.4mohm(Type);4.8mohm(Max)
UGATE1

1 2 10 PR170 0_0402_5%
BOOT1
ISUM+

ISEN2
ISEN1

ISUM-
VSEN

IMON

1 2
249K_0402_1%

8.06K_0402_1%

VDD
1000P_0402_50V7K

RTN

VIN

PC107 41
AGND
1

22P_0402_50V8J PL11,PL12 change to SH00000HK00

PC108

PC109
PR171

PR172

11
12
13
14
15
16
17
18
19
20

PR173 PU10 1U_0603_10V6K DCR=1.10mohm+-5%

2

562_0402_1% PC110
@ 1 2 1 2 ISL62883C
2

390P_0402_50V7K
PR174 PR175 0_0402_5%
3.01K_0402_1% 1 2
1 2 1 2 8 IMVP_IMON
PC111 PR176 0_0402_5%
D 10P_0402_50V8J 1 2 +CPU_B+ D
0.047U_0603_16V7K

1 2 1 2
PR178 1_0402_5%
PC112 PR177 1 2 +5VALW +CPU_B+
150P_0402_50V8J 412K_0402_1% ISEN2 1 2
1

1
PC113

PC114

PC115
1U_0603_10V6K

0.22U_0603_25V7K

PR179 0_0402_5%
PC116 0.22U_0402_6.3V6K

PC117 0.22U_0402_6.3V6K

ISEN1 1 2 PR180
2

10.5K_0402_1%
BOOT1

change to AO4406L

470P_0603_50V8J
5
6
7
8
Layout Note: PR181 0_0402_5%

10U_1206_25V6M

10U_1206_25V6M
2

PQ37
PH3 place near
1

1
VSSSENSE

PC118
Phase1 L-MOS

PC119

PC120
2

2
VSUM+ UGATE1 4

+CPU_CORE 1 2
PR184 PC121
1

C @ PR182 10_0402_5% 0_0603_5% 0.22U_0603_25V7K AO4406AL_SO8 C

3
2
1
0.047U_0402_16V7K

1
VSUM-

1 2 BOOT1_1 1 2
2.61K_0402_1%
0.22U_0603_10V7K

0.36UH_PCMC104T-R36MN1R05_30A_20%
PR185

PR183 @
PL12
1

82.5_0402_1%
PC122

PC123

8 VCCSENSE 1 2
2

PHASE1 4 1 +CPU_CORE
2

PR186 0_0402_5%
2

2
1

3 2 V1N
1

5
PC124
330P_0402_50V7K PQ38

4.7_1206_5%
2

1
PC125 @

PR187

10K_0402_5%
3.65K_0805_1%
2

1
0.01U_0402_25V7K PR190
1_0402_5%
LGATE1

PR189
4
330P_0402_50V7K

PR188
11K_0402_1%

2
1

PC126 PH3
PC127

PR193

2
1000P_0402_50V7K 1 2 RJK0392DPA-00-J53_WPAK8-5
PR194 0_0402_5% 10K_0402_1%_ERTJ0EG103FA
2

3
2
1

1
1 2 PR191 VSUM-

680P_0603_50V8J
2

B 8 VSSSENSE B
1.3K_0402_1%

PC128
2
@ PR195 10_0402_5%
1 2 1 2 1 2 VSUM- VSUM+
@ PC129 @ PR196 ISEN1
Layout Note:
1200P_0402_50V7K 100_0402_1%
Place near Phase1 Choke
.1U_0402_16V7K
1

change to footfrint SI7840DP-T1-E3_SO8

PC130

need mount SB00000IG00

2

A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C NCL61 LA-6321P M/B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 14, 2010 Sheet 54 of 57
8 7 6 5 4 3 2 1
 A B C D E F G H

1 1

9
GFXVR_VID_0

GFXVR_VID_1

GFXVR_VID_2

GFXVR_VID_3

GFXVR_VID_4

GFXVR_VID_5

GFXVR_VID_6
9
GFXVR_EN
change From 1812*1 to 0805*2

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%
+5VS
9 GFXVR_IMON
+GFX_B+
PL13

2
+VTT

PR200

PR201

PR197

PR202

PR203

PR198

PR204

PR205
2 1 B+
Add an reverse resistor

PR206
PL20
@ PR199 10_0603_1%
2

HCB2012KF-121T50_0805
300K_0402_5% 2 1

10U_1206_25V6M

10U_1206_25V6M
1

1
PR501 change from 25V

PC131

PC132
0_0402_5%

GFX_EN
to 10V tolerance
2

HCB2012KF-121T50_0805

change to AO4406L
@

2
GFX_IMON
1

1
GFX_VCC
+3VS PC133
1

5
6
7
8
1U_0603_10V6K

32

31

30

29

28

27

26

25
0.056U_0402_16V7K

2
1

PR207 PQ40
DCR=1.61mohm+-7%
PC134

6.98K_0402_1%

VID0

VID1

VID2

VID3

VID4

VID5

VID6
EN
1
2

24 PR209 PC135 Rdson=4.1mohm(type);5mohm(Max)

2

PR208 VCC 0_0603_5% 0.22U_0603_25V7K

1 4
10K_0402_1% PWRGD
23 GFX_BOOST 1 2GFX_BOOST-11 2
1

GFX_IMON BST
2
2

PC136 IMON GFX_DRVH PL14

22
1000P_0402_50V7K DRVH AO4406AL_SO8 .56UH +-20% ETQP4LR56 WFC 21A
2 3 2
2

3
2
1
VSS_AXG_SENSE CLKEN# GFX_SW
21 1 4
4
SW +GFX_CORE
FBRTN ADP3211AMNR2G_QFN32_5X5 20 +5VS 2 3
PVCC

1
1 2 GFX_FB 5
FB PU11 GFX_DRVL
19 2 1 1

AON6718L_DFN8-5
1

PC137 PC139 GFX_COMP DRVL PR210

6

330U_D2_2V_Y
220P_0402_50V7K 47P_0402_50V8J COMP PC138 4.7_1206_5% +

PC140
18
GFX_VCC 7 PGND 2.2U_0603_10V6K
2

2
GPU
2GFX_COMP-1

PQ41
1 2 1 1 2 17 4
GFX_ILIM 8 AGND 2

CSCOMP
ILIM

1
PR211 PC142 PR212 33

CSREF
AGND

RAMP

LLINE

CSFB
1K_0402_1% 470P_0402_50V8J 20K_0402_1% PC141

IREF

RPM
680P_0603_50V7K

RT

3
2
1

2
9

10

11

12

13

14

15

16
2

PR213
10.7K_0402_1% change to AON6718L
GFX_IREF

change to SGA20331E10

GFX_RAMP

GFX_CSCOMP

GFX_CSFB

GFX_CSCOMP
GFX_RT
2 GFX_RPM

PH4
9mohm Power*1,HW*1
GFX_CSCOMP 1

220K_0402_5%_ERTJ0EV224J~D

1 2
80.6K_0402_1%

237K_0402_1%

340K_0402_1%
2

Avoid high dV/dt

PR214

Place RTH1 close to inductor

PR215

PR216

PR217
71.5K_0402_1% on the same layer
1

2 1
422K_0402_1%
1

1
2

PR220

1
PR218 PR219

1
0_0402_5% 0_0402_5%
PR221
2

PC143 PC144 165K_0402_1%

1

2
1200P_0402_50V7K 680P_0402_50V7K

2
PR502 100_0402_5%

2 1
100_0402_5%
Add

PR222
2

3 3
+GFX_B+ 1 2 GFX_RAMP-1 change PC143,PC144,PR222 53.6K_0603_1%
PR503

PR510
from 1000P,560P,34.8K
to 1200P,390P,51.1K
Add

1K_0402_1%
@
1

1
9

Connect to input caps

VSS_AXG_SENSE

VCC_AXG_SENSE

@ PC145 PC146
1000P_0402_50V7K 1000P_0402_50V7K
2

2
+GFX_CORE

Shortest the
Switchable -- mount
net trace Non Swithchable--non mount @

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/02 Deciphered Date 2010/10/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+GFX_COREP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NCL61 LA-6321P M/B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, April 19, 2010 Sheet 55 of 59
A B C D E F G H
 5 4 3 2 1

PR703 @
0_0402_5%
1 2
43,46,52 SUSP#

HW ICE Required
PR701
1 2
33,46 DGPU_PWR_EN
100K_0402_1%

1
PC701 PL701
.1U_0402_16V7K
HCB2012KF-121T50_0805

2
VGA_B+ 1 2 B+
D D

2200P_0402_25V7K

0.1U_0402_25V6

4.7U_0805_25V6-K

10U_1206_25V6M

4.7U_0805_25V6-K
1

1
PC712

PC708

PC703

PC704

PC705
2

2
@

5
6
7
8
+5VALW
1+5VALW

BST_VGA 1 2 1 2

PR704 PC706 SB00000CG80

2.2_0603_5% 0.1U_0603_16V7K 4 PQ701
PR702 AO4466L_SO8

15

14
1
316_0402_1% PU701 SH00000FB00
PR705

NC

BOOT
EN/DEM
255K_0402_1% PL702
2

3
2
1
1 2 2 13 DH_VGA
TON UGATE 0.88UH_PCMC104T-R88MN_20A_20%
+VGA_COREP 3 12 LX_VGA PR706 1 2 +VGA_COREP
VOUT PHASE 11K_0402_1%

330U_D2_2V_Y
4 11 1 2
VDD CS

1
1
5 10 +5VALW
FB VDDP

PC709
PR720 +
1

1
6 9 PC707 4.7_1206_5%
PGOOD LGATE

PGND
PC702 4.7U_0805_10V6K

GND

2
1U_0603_10V6K 2
28,32,46 VGA_PWROK
2

1
DL_VGA 4 N11M-GE2

8
PC716
RT8209BGQW_WQFN14_3P5X3P5 680P_0603_50V7K PQ701: AO4466 SB00000CG80

2
PQ702 PL702: 0.88uH SH00000FB00

3
2
1
10P_0402_50V8J RJK0392DPA-00-J53_WPAK8-5
@ PR706:SD034110280
PC713
C 2 1
1
PR717
2 +VGA_COREP reserve PC705 C
PR709 10_0402_5%
Material Note: N11P
10K_0402_1%
2 1 2 1 +VGA_COREP1 1 2 +NVVDD_SENSE
VDD_SENSE 14 330uF/ 9mohm, number are 3, PQ701: TPC8037 SB00000IS00
PL702: 0.56uH SH05056BM00
1.37K_0402_1% PR718 power x1, HW x2
1

PR708 0_0402_5% PR706:SD034130280

PR740 SGA20331E10 mount PC705
5.76K_0402_1%
+3VS_DGPU
2

N11M-GE2 N11P-LP
2

PQ712
SSM3K7002FU_SC70-3 PR741 @
GPU_VID0 13
PR737 10K_0402_5% GPU_VID0 +VGA_COREP GPU_VID0 +VGA_COREP
1

D
2 2 1
21

G
0 0.85V 0 0.8V
2

S 15K_0402_1% PR738
3

PC717 10K_0402_5%
0.022U_0402_16V7K 1 1.03V 1 0.85V
1

1
1

PR743 @ Need double confirm with HW

5.76K_0402_1%
+3VS_DGPU
about the voltage level setting
2

PQ713
SSM3K7002FU_SC70-3 PR739 PR742
@ 10K_0402_5%
1

D 15K_0402_1%
2 2 1 GPU_VID1 13
21

@ G
2

S @ PR744
3

B B
@ PC718 @
0.022U_0402_16V7K
10K_0402_5% Reserve for 3 phase VGA_Core
1

A A

Title
VGA_COREP

Size Document Number Rev

NCL61 LA-6321P M/B 0.1

Date: Wednesday, April 14, 2010 Sheet 56 of 59

5 4 3 2 1
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