Simulation Driven ESD Current Density Check

Ulrich Glaser (1), Radu Stoica (2), Radu Ionescu (2), Marcel Preda (2),
Haiko Morgenstern (1), Doaa Nassar (3), and Hartmut Marquardt (4)
(1) Infineon Technologies AG, Am Campeon 1-15, 85579 Neubiberg, Germany
tel.: +49-89-234-22047, fax: +49-89-234-955 6781, e-mail: Ulrich.Glaser@infineon.com
(2) Infineon Technologies Romania & Co. Societate in Comandita, Bd. Dimitrie Pompeiu 6, Sector 2,
020337 Bucharest, Romania
(3) Vendito Software Solutions GmbH, Landshuter Allee 8-10, 80637 Munich, Germany
(4) Mentor Graphics Deutschland GmbH, Arnulfstrasse 201, 80634 Munich, Germany

Abstract - The presented current density check tool identifies the ESD current paths itself and checks the
interconnection layers for realistic ESD currents depending on all available ESD paths and the applied
ESD stress. It achieves highest flexibility and coverage with practically no false errors and without any
need for marking.

I. Introduction and Goals
Successful implementation of ESD protection in
integrated circuit applications must also ensure that
the current density in ESD paths does not exceed the
technology current density limits. The risks as well as
the challenges increase with advancing technologies
which enable more complex designs.
Various commercial software tools are already
available to assist the design community, for example
[1,2,3]. They all have decent use models and
advantages. However, they all could not meet the
complete set of our requirements and goals:
1) No need for marking of ESD protection structures.
The intended products have a significant amount of
analogue design, e.g. for automotive applications. The
ESD protection structures can be adjusted for each
application and hence vary typically. Many ESD
protection structures [e.g. 4] utilize the same library
devices as the functional circuitry and do not have a
special or even a frozen layout. Hence any marking
requirement induces significant effort or restrictions,
and is prone to errors much like a manual review.
2) Automated inspection of the full ESD current path
including functional, unintended or parasitic paths.
Functional devices can be part of the ESD protection.
Unintended or parasitic device paths are often
overseen in a manual review. It is considered as
essential advantage of a tool approach that it does not
limit its coverage to the obvious range like the direct
path from a pad to the next ESD protection structure.
Any such limitation of the verified ESD path is an
unnecessary risk.
3) Applicability for various ESD hardness
requirements and ESD stress models. The intended
applications have often different ESD hardness
requirements for their pins. The same product also
requires typically ESD robustness according to
different stress models like HBM component level [5]
or system level ESD stress models [6,7]. A versatile
tool shall be capable of handling all these required
ESD stresses with the real ESD stress currents and
distribute this ESD stress current over the possible
ESD stress paths.
4) Maximum reuse of and compatibility with existing
tools, data and models. The solution shall fit into the
existing design and verification landscape. For
example, a simulation approach shall be compatible
with the existing SPICE device models. This target is
most important for the business case. It avoids new
software license costs but enables short development
time, fast time to productive use and low maintenance
effort.
 II. Approach
The chosen approach uses advanced design
automation and data processing with two major steps /
two tools. Figure 1 illustrates the used flow.
CLEX Schematic
Simulation
environment
Setup
Critical
Path Data
Calibre Current
Density Check Layout +
Schematic
Figure 1: Illustration of the used flow with the two tools, Chip
Level ESD Extraction (CLEX) environment and Calibre®
PERC™ Current Density Check (CDC).
The first step comprises a SPICE based circuit
simulation of the ESD stress within the Chip Level
ESD Extraction (CLEX) environment. The second
step reads the simulation output data and performs the
desired Current Density Check (CDC). Both tools are
already available and used in our verification flow.
The combination of two available simulation and
physical verification tools generates added value
while enabling all defined requirements. The next two
sections outline the details for the respective tools,
input and output data.
A. Critical ESD Path Search Using
Circuit Simulation
The first step consists mainly of a SPICE circuit
simulation based on schematics. The simulation can
be run on module-level as well as top-level. A top-
level simulation is normally executed and considered
in this work because of the intention to emulate the
real ESD test of the complete hardware. Top-level
simulations of complex mixed-signal ICs are able to
be executed in acceptable computing time (maximum
~8-10 hours) due to the performance of state-of-the-
art SPICE simulators. It helps that the simulation time
in case of an ESD pulse is normally limited to the
range of ~100 ns in contrast to simulation of analog
performances, e.g. signal-to-noise ratio of an analog-
to-digital converter. Of course, if the design
complexity exceeds the capabilities of a SPICE
simulator, analog or digital behavior models are used
to substitute dedicated blocks (e.g. radio frequency or
digital circuitry) and speed-up the simulation.
CLEX was developed inside Infineon Technologies
AG more than 10 years ago to automate the entire
verification flow. This ESD verification methodology
comprises
 Enhanced standard device models, e.g. for
efficient breakdown modelling
 Tool chain to post-process / extract the device
failures and resulting current paths
This verification framework is based on Cadence
Virtuoso® environment and its script language
SKILL®. SKILL allows access to the internal
databases of the design and simulator to
 Control the SPICE simulation (define analysis
settings, start simulation, read and evaluate
results)
 Extract the schematic/layout connectivity for
current path analysis
 Automate testbench creation for all intended
ESD stress pin combinations
Further details and background information about the
CLEX framework are described in [8].
The simulator receives special ESD models for
functional and ESD devices. These enhanced device
models are checking overstress using parameterized
voltage, current and power assertions. Additional
current paths are opened by special turn-on sub-
circuits. The turn-on/off limits are extracted via TLP
measurements during device characterization. The
characteristics of the devices show, for example, the
device behavior which is only feasible for the typical
ESD stress duration ranges. The models also account
for certain dynamic effects – such as voltage
overshoot – and parasitic device behavior, resulting in
significantly improved results compared to a static
approach.
In Figure 2, the transient nature of the ESD current
path is demonstrated by an easy example circuit.
“short”
parasitic
Figure 2: Example demonstrating two subsequent damages caused
by dynamic switching behavior.
The upper part of the figure shows the full circuit
consisting of an HBM source (according to [5]), an
ESD protection diode, two low voltage (LVx)
transistors and one high voltage (HV) transistor. The
lower part of the figure focusses on the protected
transistors. In the first phase of the ESD pulse around
1ns, the drain node of the HV device is capacitively
coupled to ground and device LV1 is therefore
damaged. After this, the gate-drain capacitance of HV
causes a current flow, which enables this transistor
and damages LV2 as a consequence. The models
appropriately consider such dynamic effects.
Figure 3 illustrates an example of parasitic devices in
the model context using a PMOS transistor in a p-
substrate technology. A suitable model comprises all
relevant parasitic devices. Then the simulation can
identify both intended and parasitic ESD paths. The
described enhanced models are already available in
the technologies for functional and ESD simulations.
Gate
PMOS
p+ Source Drain p+
Q1
Q2 Q3
n-well
p-substrate
Figure 3: Example of parasitic devices of a PMOS transistor build
in a p-substrate technology. The p+diffusions create with the n-
well a parasitic pnp bipolar transistor Q1. Each p+diffusion builds
with the n-well and p-substrate a parasitic pnp bipolar transistor
Q2 and Q3. More parasitic devices exist like pn-junction diodes or
capacitances of the pn-junctions.
The user next defines the ESD stress source. Various
ESD stress sources are available and cover the typical
ESD requirements. The most relevant ESD stresses
comprise HBM component level [5] and system level
ESD stress models [6,7]. The energy impact of CDM
[9] stresses on metal connection lines is – despite the
higher currents – typically less than the impact from
HBM stresses because of the shorter stress durations.
CDM typically leads to overvoltage and gate oxide
rather than connection line damages.
The CLEX environment also enables different ESD
stress pin combinations to be simulated with one
mouse click only.
The simulation identifies the ESD current paths and
quantifies the ESD currents in the respective paths. It
delivers an accurate answer about the distribution of
the ESD current due to the complete and elaborated
model set taking all modelled devices into account
including ESD, functional and parasitic devices. The
simulation also depicts the transient behavior.
The CLEX environment provides some post-
processing steps after the simulation. The user selects
the ESD stress pin combinations (see Figure 4) for
which he wants to perform the current density check
in the next step. All ESD stress pin combinations are
required for sign off, of course. The feature is
however beneficial for reexamination after a small,
local modification for example.
The tool then determines the critical terminals (e.g.
device pins exceeding a defined current value which
depends on technology, e.g. on minimum size of the
via/wire and maximum current density per area/width)
for each simulation. The critical terminals are
received via specific dynamic assertions used during
the SPICE simulation. To reduce the amount of data,
only schematic nets which are connected to at least
one critical terminal are considered relevant and are
processed further. Next the tool determines the ESD
currents through all device pins of relevant nets. For
the purpose of the check, current is averaged over a
defined time window.
After processing simulation results, the following data
are saved into a csv file:
 Schematic names of the relevant nets
 Schematic instance names of devices
connected on the respective net
 Pin names of the devices
 The current through the pins of devices
connected on the respective net
Later this data can be read by the Calibre® PERC™
CDC.
Figure 4: Graphical user interface (GUI) for CDC data creation of
selected ESD stress pin combinations. Note that the number of
fails in this GUI refers to voltage, current and power assertions;
they do not relate to current density violations which are not
known at this point of time. The parameter Vsel is used to select
the ESD stress pin combinations which are indicated further in the
pins column.
 B. Layout Based Current Density
Check
The reliability verification tool Calibre® PERC™ [1]
from Mentor® performs the Current Density Check
(CDC) based on the layout view in the second step.
The combination of this tool with the data from circuit
simulation fulfils the complete set of our requirements
and goals.
The CDC is part of the default functionality of
Calibre® PERC™. Since it works only on the layout
data, the main implementation effort has been in
translating the critical path information generated by
CLEX from the source netlist to the layout netlist.
After this conversion, the tool adds sources and sinks
for forcing the simulated currents into the connection
layers at the correct locations.
The CDC tool then uses resistance values and current
density limits given in a technology input file to
calculate and check the current densities in the metal
lines and vias. It does so for the input data from
multiple simulations as selected in the CDC data
creation within one run.
The results of the CDC are finally stored in a
database. The engineer reviews these results
subsequently using Calibre RVE. This tool displays
all results sorted by simulated ESD stress pin
combinations and nets (see Figure 5). It allows further
filtering and sorting after selection of a dedicated ESD
stress pin combination or net. It also highlights the
results in the layout with an easy to understand color
map. This allows the review engineer to quickly spot
the weakness and define corrective measures.
Two experiments Result overview in table
= (sorting)
two simulations
All data of
one result
Figure 5: Results review with Calibre RVE providing extensive
selecting, filtering and sorting features.
C. Requirements and Limitations
The link between schematic based simulation and
current density check on layout requires a layout-vs.-
schematic (LVS) clean state of the project. This is not
a major limitation since a layout check anyway makes
most sense when the layout is ready, close to tape-out.
The simulation does not have any information from
the layout in the current tool version. This is
beneficial for the run time of the simulation.
However, it might introduce some inaccuracy of the
simulated current distribution across parallel paths,
for example due to resistive impact of the metal
connection lines.
In order to transfer results from simulation to layout,
one needs to take into account the fact that a simple
one-to-one relationship between schematic and layout
devices does not exist in general. A one-to-one
relationship only exists for reduced (sometimes also
called “smashed”) devices. Typical examples are
multi-finger transistors. Each finger is represented by
one device in the layout netlist, but the set of fingers
is represented by one single device in the source
netlist. In order to find the correspondence between
layout and source netlist, the multi-finger transistors
are reduced to a single device which then can be
unambiguously related to the schematic device. The
device reduction scheme is defined in the LVS rule
deck. Therefore, in our current tool implementation, if
a schematic device is drawn as a multi finger device,
the current simulated for a given schematic device pin
is divided by the number of corresponding layout
device fingers. This effective current is then imposed
on each finger of the layout device. This approach
may cause inaccuracies for the current distribution if
the parasitic resistances of the different fingers are not
well matched. Calibre PERC has been upgraded after
the flow has been implemented. It now allows to
virtually connect a single current source to all
individual layout devices belonging to the same
schematic device. With this feature, the current
distribution over a multi finger device will depend
correctly on the parasitic resistance of each finger, i.e.
there are no more inaccuracies caused by LVS device
reduction.
These potential inaccuracies due to multi finger
devices and resistive impact of the metal connection
lines have been acceptable so far. It is indeed a major
outcome of this work that more accurate simulations
are not needed. Some reasons for this are (without
aiming at a 100% proof): the current density limits
contain a margin and the inaccuracies typically lead to
stronger violations in critical cases like a resistive
bottle neck in one of several paths or in a finger which
is smaller than the average width of all parallel
fingers. Furthermore, ESD rules also limit the
resistance of the metal connection in ESD paths.
Functional paths which conduct significant currents Figure 6 and Figure 7 show an example of the current
during normal operation and ESD stresses are density histogram and the corresponding metal shapes
unlikely to have a relevant resistance in their metal for one of the simulations.
connection for functional reasons. Hence the main
ESD current flows in the correct paths, possibly with 3 2 2 2
acceptable underestimation of currents. As a final (22.2%) (22.2%) (22.2%)

Result Count
(33.3%)

solution in case of serious concerns about the metal

connection resistance impact, the described approach
can be applied also on an extracted view containing
Error (%)
the metal connection resistances. However, again, our
experiences indicate that simulation with extracted Figure 6: Histogram of current density violations. The “Error (%)”
view is unnecessary. specifies how much the technology limits are exceeded in percent.
The “Results Count” specifies the number of shapes with this
The consideration of a device in simulation requires it violation. The colors correspond to the colors of the shapes in
to be present in the models. The quality of the CDC Figure 7. The histogram hence supports the engineer to match the
results also depends significantly on the models. This colors to the violations/severity.
is not a limitation but just a requirement one needs to
be aware of. The advantage of the presented approach
is the fact that the CDC benefits from any model
improvement of other simulation tools and vice versa
because there is just one model set for all simulation-
based tools.

III. Application Example

A design having known ESD weaknesses (based on
lab measurements) at 2 kV HBM stress level was used
to validate the check implementation. The details of
this test case (focusing on ESD stress combinations of
the known weaknesses and related combinations) are
as follows:
 Chip size: ~30000 schematic devices, 4 metal
layer stack
 Number of circuit simulations/ESD stress pin
combinations: 8
 Source/sink pairs checked: ~200.000
 Total runtime for CLEX and CDC (machine
CPU: Intel® Xeon® Gold 6142 CPU @
2.60 GHz, 4 cores): ~34000 s Figure 7: Color map of current density violations. The colors of
the shapes correspond to the colors and hence the amount of
 Peak memory used: 8 GB violation in the histogram in Figure 6.
The total runtime depends heavily on the number of
circuit simulations; each simulation generates a
separate ESD current density extraction.
Conclusions
A total of 17 violations were highlighted using the The presented simulation driven ESD current density
default technology current density limits. The check was successfully implemented and turned out to
violations come from two of the eight simulations and be especially useful for the intended products with
include the weaknesses observed during significant analogue design. The test case proved that
measurements. The check proved to have a very high this CDC detects all known weaknesses with a very
success rate, all highlighted shapes being potential high success rate, i.e. the number of false errors is
weaknesses and considered violations of ESD rules. much lower than the number of real errors. The
The ratio of false to real errors is 0. simulations and current density checks require some
execution/computing time, but the final current
density check is reliable and the result review is very
efficient due to the high automation, the
realistic/small number of reported errors and
additional debug information extracted from the
simulation results. No current density issues occurred
so far in checked products since the CDC tool has
been in productive use.
References
[1] Calibre® PERC™,
https://www.mentor.com/products/ic_nanometer_
design/reliability-verification/calibre-perc
[2] Magwel® ESDi®,
https://www.magwel.com/products/esdi/
[3] Ansys Pathfinder, https://www.apache-
da.com/products/redhawk/pathfinder
[4] Y. Cao, U. Glaser, “Statically Triggered Active
ESD Clamps for High-Voltage Applications“,
EOS/ESD 2012.
[5] ANSI/ESDA/JEDEC JS-001-2017,
“ESDA/JEDEC Joint Standard for Electrostatic
Discharge Sensitivity Testing – Human Body
Model (HBM) – Component Level”, May 2017.
[6] IEC 61000-4-2, “Electromagnetic compatibility
(EMC) – Part 4-2: Testing and measurement
techniques – Electrostatic discharge immunity
test”, Ed. 2.0, 2008.
[7] ANSI/ESD SP5.6-2009, “ESD Association
Standard Practice for Electrostatic Discharge
Sensitivity Testing – Human Metal Model
(HMM) – Component Level”, 2009.
[8] H. Morgenstern, “Effiziente Verifikation der
Robustheit komplexer integrierter Schaltungen”,
TU-Berlin, 2011.
[9] ANSI/ESDA/JEDEC JS-002-2018, “Joint
Standard for Electrostatic Discharge Sensitivity
Testing – Charged Device Model (CDM) –
Device Level”, Jan 2019.