FZL 4141D FZL 4145 D The switching threshold at inputs DI and ENA can be adjusted between 1.5 V and 7 V via connection TS: input threshold = 1.5 V (for 5 V logic) input threshold = Vy +1.5 V input threshold = 7 V (for 12/15 V and 24/28 V logic) If the output is disabled due to the logic states of inputs DI or ENA this disable is effective over the total supply voltage range between V; = 0 V and V, = 35 V. The inputs are protected with clamp diodes. Maximum Ratings Description Symbol | min max Unit | Notes Supply voltage Vs -03 35 Vv Supply voltage Vg -03 45 v 100 ms duration, 13 interval Input voltage at DI and ENA Vp, ena | —0.3 35 v » Voltage at TS and SQ Vis,so | -0.3 45 v Output voltage Vq and voltage at | Vo, Vo Vs VvFZL 4141D FZL 4145 D Characteristics Supply voltage 4.5 V< Ve<30V FZL4141D 0°CST<+70°C FZL 4145 D-25°C SS +85°C Description Symbol | Test conditions | min vp max Unit Supply current Js Vena=0V, Y= Ve 6 85 mA H input voltage at DI, ENA Vn Vis= OV 2 v H input voltage at Dl, ENA Yn Vis = Vs 8 v Linput voltage at Di, ENA Me Vis = 0V 07 v Linput voltage at Dl, ENA Va Vas = Ve 6 v Input current at DI, ENA Torena | 0.5VSVo,enaS30V| 50 200 HA output voltage at SQ Vea__| Isa=5mA 05 v Output current available!) | Jo 15 25 mA To 17 mA Current from TS rhs 2 40 HA Switching threshold at W | Vy Vs-0.6 | Vs—0.5 | Ve-0.4 | V Current in W Iw 100 pA Current from C ale 12 20 34 HA Current in Ie 06 1 WZ mA Upper switching threshold at C Vey T= 20°C 16 24 17 v Lower switching threshold at C Vou. T= 20°C 06 09 12 v Saturation voltage at T2) Vor Vw=Vg-2V, Ig=0 Vs-0.3 v H output voltage Vou | Venn=OV Vg-0.25 | Ve-0.02 v 1) The actual output current is typically 0.5 mA higher, a value which is required as current for the short-circuit protection. However, only the value specified above is available to drive the external output transistors. 2) See block diagram Siemens Aktiengeselischatt 286Pin Configuration top view Vs Q1 Wi Q2 W2 W3 G3 Wh O& wT 6 1S % B 2 MH 10 123 4 5 6 7 86 9 € 011 DIZ O13 O14 ENA SQ TS Os Block Diagram r--- 7 iD 7 Clock { generator] | ~_T I \ : wt [ lL +—a1 | on 1 { _— I 012 F- & W2 eee | a2 Dl Driver input ENA Enable input C Clock capacitor Q Output TS Input for threshold switching W_ Input for output current limiter SQ_ Signaling output Siemens Aktiengesellschaft 287 FZL 4141D FZL 4145 DFZL 4141D FZL 4145D Schematic Circuit Diagram of One Stage eee ! ! oVs 7 aa : | Dl Driver input ENA Enable input C Clock capacitor SQ _ Signaling output Q Output TS Input for threshold switching W Input for output current limiter Siemens Aktiengesellschaft 288F2ZL 4141D FZL 4145D Mode of Operation: Switching-On again after Overload with Key H ‘ RR & ° uo ree x mh oR 3 yoo voy " Yo cd clsea 2av age (aay X= Overload operation Overload pe : i 7 R= Rated operation operation aioe Mode of Operation: Automatic Switching-On again after Overload 50 XsOvertoad operation |____Overtoad _ Duty eyle R=Rated operation operation Siemens Aktiengeselischaft 289FZL 4141D FZL 4145D ‘Typical Application Circuits The load conditions at Q depend on the permissible power dissipation of the power transistors. used. The pulsed power dissipation in case of a short circuit must be observed. In order to suppress oscillations of the power stage in case of a short circuit, a capacitor C at Q1 to Q4 is necessary if e.g., fast switching transistors are used. Typical value C approx. 20 nF. The output circuit 1 is suited for currents up to approx. Iq = 100 mA. The output circuits 2 and 3 are suited for currents up to approx. Ig = 2 A. A minimum power dissipation can be achieved with circuit 3. A break key in parallel to Cy allows a manual switch-on in case of short circuit. vs kK G Re Rp ot WhiWs ore ENA FzL4ig1o [21:04 ie sa 2 3 os : Rp = Precision resistor (current measurement) Cr 0.8x ty (nF, us) tp = Short-circuit current pulse length Note Circuit 1 does not permit a capacitor between Q1 and Q4 and the collector. Circuit 2 does not permit a capacitor between Q1 and Q4 and base or emitter, respectively. Otherwise too high current spikes would arise in case of a short circuit. Siemens Aktiengesellschaft 290FZL 4141D FZL 4145D Typical Application of Short-Circuit Signaling Output SQ 1. LED Display « | c Asamox <8mA = 2. TTL/CMOS/LSL Driving If the pulses that appear at SQ during clocked operation disturb the remainder of the circuit, a lowpass filter will be necessary. Fora load current of Isq= 1 mAa capacitor C of approx. 10 nF is necessary to limit the output pulses of up to 10 ws (depending on Cy) to 1 V. Signaling occurs after approx. 50 ps. Siemens Aktiengesellschaft 291