MODULE-4

➢Design for Testability:

➢Introduction,
➢Fault Types and Models
➢Ad Hoc Testable Design Techniques,
➢Scan-Based Techniques,
➢Built-In Self-Test (BIST) Techniques,
➢Current Monitoring IDDQ Test.
Introduction
➢VLSI testing means checking of the manufactured IC to verify its
correctness.

➢when faulty chips pass an improperly designed test, they can

cause system failures and enormous difficulty in system
debugging.

➢It is known that the debugging cost increases by about tenfold

from chip level to board level, and also from board level to system
level. Thus, it is of great importance to detect faults as early as
possible.

➢Another important aspect of testing is the testing time. Let us

consider a combinational circuit having n inputs. To test this
circuit completely, we need 2n number of possible input
combinations (or test vectors). In case of sequential circuits, the
required test vectors would be 2n +m if there are m number of
registers.
Introduction
➢Testing is done at several stages. In the first stage, the die is
tested at the wafer level. A test program is used to test the die. The
test program applies a set of input bit patterns which are known
as test vectors, and checks the test response. Any chip that fails
this test is marked as a bad chip. This test is often called the
production test.

➢In the second stage, the die is separated out from the wafer and
packaged, and it is again tested with the same test vectors. This is
called the final test or package level test.

➢At the customer end, the chip is placed in the board and the
board is tested. If any chip malfunctions at the board level test, it
is sent back to the manufacturer.

➢In the system level test, the board is placed in the system and
checked if the system works as specified. The last stage of testing
is done at the field level, when an end-user tests the system while
using a system.
Fault types & Models
➢Chip testing, in the conventional sense, is usually multi-purpose
and attempts to detect faults in fabrication, design, and failures
due to stressful operating conditions, namely the reliability
problems. Input test vectors are devised and applied to the device
under test (DUT) or circuit under test (CUT) as its stimuli. Then
the measured outputs are compared with the expected correct
responses to determine whether DUT is good (go) or bad (no-go).

➢The main difficulty in testing is caused by the fact that only input
and output pins of DUT are accessible, although at the test bench
in the development laboratory, the internal nodes of unpackaged
chips can be probed at the topmost metal level before passivation
is done.

➢As the operating clock frequency of the chips increases beyond

several tens of megahertz, the at-speed test has also become a
difficult problem.
Fault types & Models
➢The difficulty stems from the signal integrity problem in sending
test signals from the tester to DUT and in detecting response signals
from DUT due to impedance mismatch and transmission line
problems in the tester interconnects.

➢In addition to the tester problem, the generation of correct test

vectors to detect all modeled faults and design errors in complex
chips, either manually or through an automatic test patter generator
(ATPG), has become a difficult Task.

➢During the IC fabrication, the MOS devices could be fabricated

incorrectly, or the interconnect wires could have open-circuit or
short-circuit fault. All these defects lead to malfunctioning of the IC.
Fault types & Models

Examples of physical defects include:

* Defects in silicon substrate
* Photolithographic defects
* Mask contamination and scratches
* Process variations and abnormalities
* Oxide defects
Fault types & Models
The physical defects can cause electrical faults and logical faults.
The electrical faults include:
* Shorts (bridging faults)
* Opens
* Transistor stuck-on, stuck-open
* Resistive shorts and opens
* Excessive change in threshold voltage
•Excessive steady-state currents

The electrical faults in turn can be translated into logical faults.

The logical faults include:
* Logical stuck-at-0 or stuck-at-I
* Slower transition (delay fault)
* AND-bridging, OR-bridging
Fault types & Models
➢The logical faults can be classified into two main subclasses:
▪Degradation fault—this degrades the performance of the chip
▪Fatal fault—this causes the chip to malfunction

➢The open-circuit and short-circuit faults are often grouped under

fatal faults. A delay fault can be classified as a degradation fault,
as it may not cause any functionality failure, but causes the chip to
operate at a slower speed.

➢The open-circuit fault is caused by several reasons. Some of the

possible causes are as follows:
▪Bad contact
▪Over-etched metal
▪Break in poly silicon line
▪Void formed due to electro migration
Fault types & Models
➢The short-circuit fault is also caused by various reasons. Some of
the possible causes are as follows:
▪Under-etching of metal lines
▪Hillock formed due to electro migration
▪Junction spiking
▪Pinholes or shorts through the gate oxide
▪Diffusion shorts

➢Another important fault is the bridging fault that happens in

interconnects. It occurs mainly due to metal coverage problems.

➢The most popular fault model is the stuck-at fault model. In this model,
there are two types of logical faults:
▪Stuck-at-1 (abbreviated as SA1 or S@1)
▪Stuck-at-0 (abbreviated as SA0 or S@0)
Fault types & Models
➢The stuck-at-fault normally occurs due to the short circuit of the gate
of the MOS device to either the VDD or to the ground and metal-to-
metal shorts. The number of fault sites in a circuit is given by (Number
of principal inputs+ Number of gates + Number of fan-out branches).
The number of single stuck at-fault is equal to twice the number of fault
sites in the circuit.
Fault types & Models
➢In this circuit, the input line B can be stuck-at- 1 (s-a- 1), since some
part of the input line is shorted to the power rail. The pMOS transistor
of the first stage NOR2 gate is stuck-on due to a process problem that
causes a short between its source and drain terminals.
The top nMOS transistor in the NAND2 gate, on the other hand, is
stuck-open due to either an incomplete contact (open) of the source or
drain node or due to a large separation of drain or source diffusion
from the gate, which Causes permanent turn-off of the transistor
regardless of the input C value.
The bridging fault between the output line of the inverter and the
input line C can be due to a fabrication defect which causes a short
between any two parts of the two lines. Although in the circuit diagram,
these two lines are seemingly far apart, in the actual layout, some part
of these two lines can be close to each other.
Fault types & Models
➢The single stuck-at fault models are used frequently, although the DUT
can have defects that do not map to a single stuck-at fault.
Some of the reasons are:
* Complexity of test generation is greatly reduced.
* Single stuck-at fault is independent of technology, design style.
* Single stuck-at tests cover a large percentage of multiple stuck-at faults
•Single stuck-at tests cover a large percentage of unmodeled physical
defects.

➢In fact, it has been shown that in a two-level circuit with no

redundancy, any complete test set for all single stuck-at faults can
cover all stuck-at faults. Multiple stuck-at fault models find applications
for fuse or anti-fuse based programmable designs such as
programmable gate arrays, FPGAs, and RAMs.
Fault types & Models
➢The delay fault which causes timing failures at target speed can be
due to several factors. To name a few,
▪ improper estimation of on-chip interconnect delays and other
timing considerations,
▪ excessive variations in the fabrication process which cause
significant variations in circuit delays and clock skews,
▪ opens in metal lines connecting parallel transistors which make the
effective transistor size much smaller,
▪ aging effects such as hot-carrier induced delay increase.

➢The fault models mentioned above are used in fault simulation

aimed at
▪Test generation,
▪Construction of fault dictionaries, or
▪Circuit analysis in the presence of faults.
Each fault dictionary stores the expected output response of every
faulty circuit to a particular test vector corresponding to a particular
simulated fault.
 Ad Hoc Testable Design Techniques
The ad hoc testing is basically a combination of different simple test
strategies that are used to reduce the number of tests from a large set
of test patterns.
Listed below are some of the ad hoc testable design techniques:

1. Partition-and-Mux Technique
 Ad Hoc Testable Design Techniques
➢Since the sequence of many serial gates, functional blocks, or large
circuits are difficult to test, such circuits can be partitioned and
multiplexors (muxes) can be inserted such that some of the primary
inputs can be fed to partitioned parts through multiplexers with
accessible control signals. With this design technique, the number of
accessible nodes can be increased and the number of test patterns
can be reduced.
➢However, circuit partitioning and addition of multiplexers may
increase the chip area and circuit delay. This practice is not unique
and is similar to the divide-and-conquer approach to large, complex
problems.

2. Initialize Sequential Circuit

➢ When the sequential circuit is powered up, its initial state can be
a random, unknown state. In this case, it is not possible to start
the test sequence correctly. The state of a sequential circuit can
be brought to a known state through initialization.
 Ad Hoc Testable Design Techniques
➢In many designs, the initialization can be easily done by
connecting asynchronous preset or clear-input signals from primary
or controllable inputs to flip-flops or latches.

3. Disable Internal Oscillators and Clocks

➢To avoid synchronization problems during testing, internal
oscillators and clocks should be disabled. For example, rather than
connecting the circuit directly to the on-chip oscillator, the clock
signal can be ORed with a disabling signal followed by an insertion
of a testing signal .
 Ad Hoc Testable Design Techniques
4. Avoid Asynchronous Logic and Redundant Logic
The enhancement of testability requires serious tradeoffs. The speed
of an asynchronous logic circuit can be faster than that of the
synchronous logic circuit counterpart. However, the design and test
of an asynchronous logic circuit are more difficult than for a
synchronous logic circuit, and its state transition times are difficult
to predict. Also, the operation of an asynchronous logic circuit is
sensitive to input test patterns, often causing race problems and
hazards of having momentary signal values opposite to the expected
values.
Sometimes, designed-in logic redundancy is used to mask a static
hazard condition for reliability. However, the redundant node cannot
be observed since the primary output value cannot be made
dependent on the value of the redundant node. Hence, certain faults
on the redundant node cannot be tested or detected.
Ad Hoc Testable Design Techniques

➢Although it is unessential to test redundant nodes when they are

designed in as backup parts, either to enhance the circuit reliability
or to increase the fabrication yield, the use. of redundant circuits can
make test generation much more complex and difficult. In fact, test
generators, especially the random or deterministic test generators,
would not be able to recognize such design intent.
Ad Hoc Testable Design Techniques
5. Avoid Delay-Dependent Logic
➢Chains of inverters can be used to design in delay times and use
AND operation of their outputs along with inputs to generate pulses,
as shown in Figure. Most automatic test pattern generation (ATPG)
programs do not include logic delays to minimize the complexity of the
program. As a result, such delay-dependent logic is viewed as
redundant combinational logic, and the output of the reconvergent
gate is always set to logic 0, which is not correct. Thus, the use of
delay-dependent logic should be avoided in design for testability.
 Scan Based Techniques
➢As discussed earlier, the controllability and observability can be
enhanced by providing more accessible logic nodes with use of
additional primary input lines and multiplexors. However, the use of
additional I/O pins can be costly not only for chip fabrication but also
for packaging.

➢The scan design technique is a structured approach to design

sequential circuits for testability. The storage cells in registers are
used as observation points, control points, or both. By using the scan
design techniques, the testing of a sequential circuit is reduced to the
problem of testing a combinational circuit.

➢In general, a sequential circuit consists of a combinational circuit

and some storage elements. In the scan-based design, the storage
elements are connected to form a long serial shift register, the so-
called scan path, by using multiplexors and a mode (test/ normal)
control signal, as shown in Fig.
Scan Based Techniques
 Scan Based Techniques
➢In the test mode, the scan-in signal is clocked into the scan path, and
the output of the last stage latch is scanned out. In the normal mode,
the scan-in path is disabled and the circuit functions as a sequential
circuit. The testing sequence is as follows:

▪ Step 1: Set the mode to test and, let latches accept data from scan-in
input,
▪Step 2: Verify the scan path by shifting in and out the test data.
▪Step 3: Scan in (shift in) the desired state vector into the shift register.
▪Step 4: Apply the test pattern to the primary input pins.
▪ Step 5: Set the mode to normal and observe the primary outputs of
the circuit after sufficient time for propagation.,
▪Step 6: Assert the circuit clock, for one machine cycle to capture the
outputs of the combinational logic into the registers.
▪Step 7: Return to test mode; scan out the contents of the registers,
and at the same time scan in the next pattern.
▪Step 8: Repeat steps 3-7 until all test patterns are applied.
 Scan Based Techniques
➢In large high-speed circuits, optimizing a single clock signal for
skews, etc., both for normal operation and for shift operation, is
difficult. To overcome this difficulty, two separate clocks, one for
normal operation and one for shift operation, are used. Since the shift
operation does not have to be performed at the target speed, its clock
is much less constrained.
 Scan Based Techniques
➢An important approach among scan-based designs is the level
sensitive scan design (LSSD), which incorporates both the level
sensitivity and the scan path approach using shift registers. The level
sensitivity is to ensure that the sequential circuit response is
independent of the transient characteristics of the circuit, such as the
component and wire delays. Thus, LSSD removes hazards and races.
Its ATPG is also simplified since tests have to be generated only for
the combinational part of the circuit data from scan-in input.

➢The boundary scan test method is also used for testing printed
circuit boards (PCBs) and multichip modules (MCMs) carrying
multiple chips. Shift registers are placed in each chip close to I/O pins
in order to form a chain around the board for testing. With successful
implementation of the boundary scan method, a simpler tester can be
used for PCB testing. On the negative side, scan design uses more
complex latches, flip-flops, I/O pins, and interconnect wires and, thus,
requires more chip area. The testing time per test pattern is also
increased due to shift time in long registers.
 Built In Self Test (BIST)Techniques
➢In built-in self test (BIST) design, parts of the circuit are used to test
the circuit itself. Online BIST is used to perform the test under normal
operation, whereas off-line BIST is used to perform the test off-line.
The essential circuit modules required for BIST include:
▪ Pseudo random pattern generator (PRPG)
▪ Output response analyzer (ORA)
The implementation of both PRPG and ORA can be done with Linear
Feedback Shift Registers (LFSRs).
 Built In Self Test (BIST)Techniques
Pseudo Random Pattern Generator
➢To test the circuit, test patterns first have to be generated either by
using a pseudo random pattern generator, a weighted test generator,
an adaptive test generator, or other means. A pseudo random test
generator circuit can use an LFSR.
➢LFSR is used to generate pseudo-random test vectors in the chip.
The outputs at each stage of an LFSR are used as the input of the
circuit. The LFSR is clocked for a large number of cycles, and the
output is monitored. A PRSG is a sequence of a particular length (n).
The bit-pattern of the sequence is random in nature but has a
periodicity. That is why it is called pseudorandom sequence.
 Built In Self Test (BIST)Techniques
➢The length of the sequence is determined by the number of flip-flops
(N) and is given by

Linear Feedback Shift Register as an ORA

➢To reduce the chip area penalty, data compression schemes are used
to compare the compacted test responses instead of the entire raw test
data. One of the popular data compression schemes is the signature
analysis, which is based on the concept of cyclic redundancy checking.
➢It uses polynomial division, which divides the polynomial
representation of the test output data by a characteristic polynomial
and then finds the remainder as the signature. The signature is then
compared with the expected signature to determine whether the device
under test is faulty. It is known that compression can cause some loss
of fault coverage. It is possible that the output of a faulty circuit can
match the output of the fault-free circuit; thus, the fault can go
undetected in the signature analysis. Such a phenomenon is called
aliasing.
 Built In Self Test (BIST)Techniques

➢In its simplest form, the signature generator consists of a single-

input linear feedback shift register (LFSR), as shown in Fig., in which
all the latches are edge-triggered. In this case, the signature is the
content of this register after the last input bit has been sampled. The
input sequence {an) is represented by polynomial G(x) and the output
sequence by Q(x). It can be shown that G(x) = Q(x) P(x) + R(x),
where P(x) is the characteristic polynomial of LFSR and R(x) is the
remainder, the degree of which is lower than that of P(x). For the
simple case in Fig., the characteristic polynomial is
 Built In Self Test (BIST)Techniques

Output Response Analyzer

➢The on-chip storage of a fault dictionary containing all test inputs
with the corresponding outputs is prohibitively expensive in terms of
the chip area. A simple alternative method is to compare the outputs of
two identical circuits for the same input, with one of them regarded as
reference. However, if both circuits have the same faults, their outputs
can still match. Such faults cannot be detected with this technique,
although, the probability of two identical circuits having exactly the
same faults would be very low.
 Built In Self Test (BIST)Techniques
➢In addition to the above circuits for built-in self test, self-checking
design techniques can be used to detect faults autonomously during
on-line operation. Usually a checker circuit is inserted such that the
checker generates and sends out a signal when on-line faults occur.
The distribution of checkers throughout a very large digital circuit or
system can provide prompt detection of the fault location by tracing
the checker which sent the fault signal.

➢The use of self-checking circuits simplifies the development of

software diagnostic programs. However, some additional hardware is
required, and the checker itself needs to have self-checking capability.
When self-checking capability of the checker itself is required, a
single-output checker is not sufficient since that output may have a
stuck-at fault, thus preventing the detection of actual faults in the
circuit under test. A checker with a pair of outputs can be used instead
to overcome this problem.
 Built In Self Test (BIST)Techniques
Built-In Logic Block Observer
➢The built-in logic block observer (BILBO) register is a form of ORA
which can be used in each cluster of partitioned registers. A basic
BILBO circuit is shown in Fig, which allows four different modes
controlled by C0 and Cl signals.
➢The BILBO operation allows monitoring of circuit operation
through exclusiveORing into LFSR at multiple points, which
corresponds to the signature analyzer with multiple inputs.
 Current Monitoring IDDQ Test
➢An often-used technique for testing fabrication defects is the IDDQ
test. Under a bridging fault, the static currents drawn from the power
supply in CMOS circuits can be noticeably high, well beyond the
expected range of leakage currents.

➢It can also detect other fabrication defects not easily detected by
other test methods, including:
▪ Gate oxide short
▪Channel punch-through
▪ p-n diode leakage
▪ Transmission-gate defect

➢The IDDQ test consists of applying the test vector and then
monitoring the current drawn from the power supply rail in DC steady
state. Although this test requires more testing time, the fault detection
capability is greatly improved with small circuit overhead required to
monitor the IDDQ in various parts of DUT.
 Current Monitoring IDDQ Test
➢While stuck-at tests require both fault sensitization and fault effect
propagation, the IDPQ test requires only fault sensitization.

➢The design guidelines for IDDQ testability are as follows:

▪Low static current states, e.g., full CMOS is preferred
▪ No active pull-ups or pull-downs
▪ No internal drive conflicts, e.g., drivers share a bus
▪ No floating nodes in the circuit
▪ No degraded voltages, e.g., must have VOH = VDD and VOL = 0